forked from Imagelibrary/rtems
cpukit: Add basic riscv32 architecture port v3
Limitations: * NO FPU support [TODO] Update #3109
This commit is contained in:
Hesham Almatary
committed by
Hesham Almatary
Hesham Almatary
parent
f47dc8d58b
commit
660db8c86f
26
cpukit/score/cpu/riscv32/Makefile.am
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26
cpukit/score/cpu/riscv32/Makefile.am
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@@ -0,0 +1,26 @@
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include $(top_srcdir)/automake/compile.am
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include_rtemsdir = $(includedir)/rtems
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include_rtems_HEADERS = rtems/asm.h
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include_rtems_scoredir = $(includedir)/rtems/score
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include_rtems_score_HEADERS = rtems/score/cpu.h
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include_rtems_score_HEADERS += rtems/score/cpuatomic.h
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include_rtems_score_HEADERS += rtems/score/cpuimpl.h
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include_rtems_score_HEADERS += rtems/score/cpu_asm.h
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include_rtems_score_HEADERS += rtems/score/types.h
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include_rtems_score_HEADERS += rtems/score/riscv.h
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include_rtems_score_HEADERS += rtems/score/riscv-utility.h
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noinst_LIBRARIES = libscorecpu.a
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libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
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libscorecpu_a_SOURCES = cpu.c
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libscorecpu_a_SOURCES += riscv-exception-handler.S
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libscorecpu_a_SOURCES += riscv-exception-default.c
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libscorecpu_a_SOURCES += riscv-exception-frame-print.c
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libscorecpu_a_SOURCES += riscv-context-switch.S
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libscorecpu_a_SOURCES += riscv-context-initialize.c
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libscorecpu_a_SOURCES += riscv-context-validate.S
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libscorecpu_a_SOURCES += riscv-context-volatile-clobber.S
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/automake/local.am
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124
cpukit/score/cpu/riscv32/cpu.c
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124
cpukit/score/cpu/riscv32/cpu.c
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@@ -0,0 +1,124 @@
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/*
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* riscv32 CPU Dependent Source
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*
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* Copyright (c) 2015 University of York.
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* Hesham ALmatary <hesham@alumni.york.ac.uk>
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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#include <rtems/score/cpu.h>
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/* bsp_start_vector_table_begin is the start address of the vector table
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* containing addresses to ISR Handlers. It's defined at the BSP linkcmds
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* and may differ from one BSP to another.
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*/
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extern char bsp_start_vector_table_begin[];
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void init(void);
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void fini(void);
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void _init()
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{
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}
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void _fini()
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{
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}
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/**
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* @brief Performs processor dependent initialization.
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*/
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void _CPU_Initialize(void)
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{
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/* Do nothing */
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}
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void _CPU_ISR_Set_level(uint32_t level)
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{
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/* Do nothing */
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}
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uint32_t _CPU_ISR_Get_level( void )
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{
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/* Do nothing */
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return 0;
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}
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void _CPU_ISR_install_raw_handler(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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/* Do nothing */
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}
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void _CPU_ISR_install_vector(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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proc_ptr *table =
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(proc_ptr *) bsp_start_vector_table_begin;
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proc_ptr current_handler;
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ISR_Level level;
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_ISR_Local_disable( level );
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current_handler = table [vector];
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/* The current handler is now the old one */
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if (old_handler != NULL) {
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*old_handler = (proc_ptr) current_handler;
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}
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/* Write only if necessary to avoid writes to a maybe read-only
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* memory */
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if (current_handler != new_handler) {
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table [vector] = new_handler;
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}
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_ISR_Local_enable( level );
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}
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void _CPU_Install_interrupt_stack( void )
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{
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/* Do nothing */
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}
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void *_CPU_Thread_Idle_body( uintptr_t ignored )
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{
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do {
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} while (1);
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return NULL;
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}
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67
cpukit/score/cpu/riscv32/riscv-context-initialize.c
Normal file
67
cpukit/score/cpu/riscv32/riscv-context-initialize.c
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@@ -0,0 +1,67 @@
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/*
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*
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* Copyright (c) 2015 University of York.
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* Hesham Almatary <hesham@alumni.york.ac.uk>
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*
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* COPYRIGHT (c) 1989-2006.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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|
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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|
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <string.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/riscv-utility.h>
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#include <rtems/score/interr.h>
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void _CPU_Context_Initialize(
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Context_Control *context,
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void *stack_area_begin,
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size_t stack_area_size,
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uint32_t new_level,
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void (*entry_point)( void ),
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bool is_fp,
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void *tls_area
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)
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{
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uintptr_t stack = ((uintptr_t) stack_area_begin);
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/* Account for red-zone */
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uintptr_t stack_high = stack + stack_area_size - RISCV_GCC_RED_ZONE_SIZE;
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memset(context, 0, sizeof(*context));
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/* Stack Pointer - sp/x2 */
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context->x[2] = stack_high;
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/* Frame Pointer - fp/x8 */
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context->x[8] = stack_high;
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/* Return Address - ra/x1 */
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context->x[1] = (uintptr_t) entry_point;
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/* Enable interrupts and FP */
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context->mstatus = MSTATUS_FS | MSTATUS_MIE;
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}
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139
cpukit/score/cpu/riscv32/riscv-context-switch.S
Normal file
139
cpukit/score/cpu/riscv32/riscv-context-switch.S
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@@ -0,0 +1,139 @@
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/*
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* riscv32 CPU Dependent Source
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*
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* Copyright (c) 2015 University of York.
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* Hesham ALmatary <hesham@alumni.york.ac.uk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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|
* notice, this list of conditions and the following disclaimer.
|
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|
* 2. Redistributions in binary form must reproduce the above copyright
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|
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/score/cpu.h>
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.section .text, "ax"
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.align 4
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# define LREG lw
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# define SREG sw
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PUBLIC(_CPU_Context_switch)
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PUBLIC(_CPU_Context_restore)
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PUBLIC(_CPU_Context_restore_fp)
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PUBLIC(_CPU_Context_save_fp)
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PUBLIC(restore)
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SYM(_CPU_Context_switch):
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/* Disable interrupts and store all registers */
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csrr t0, mstatus
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SREG t0, (32 * CPU_SIZEOF_POINTER)(a0)
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csrci mstatus, MSTATUS_MIE
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SREG x1, (1 * CPU_SIZEOF_POINTER)(a0)
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SREG x2, (2 * CPU_SIZEOF_POINTER)(a0)
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SREG x3, (3 * CPU_SIZEOF_POINTER)(a0)
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SREG x4, (4 * CPU_SIZEOF_POINTER)(a0)
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SREG x5, (5 * CPU_SIZEOF_POINTER)(a0)
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SREG x6, (6 * CPU_SIZEOF_POINTER)(a0)
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SREG x7, (7 * CPU_SIZEOF_POINTER)(a0)
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SREG x8, (8 * CPU_SIZEOF_POINTER)(a0)
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SREG x9, (9 * CPU_SIZEOF_POINTER)(a0)
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SREG x10, (10 * CPU_SIZEOF_POINTER)(a0)
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SREG x11, (11 * CPU_SIZEOF_POINTER)(a0)
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SREG x12, (12 * CPU_SIZEOF_POINTER)(a0)
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SREG x13, (13 * CPU_SIZEOF_POINTER)(a0)
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SREG x14, (14 * CPU_SIZEOF_POINTER)(a0)
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SREG x15, (15 * CPU_SIZEOF_POINTER)(a0)
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SREG x16, (16 * CPU_SIZEOF_POINTER)(a0)
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SREG x17, (17 * CPU_SIZEOF_POINTER)(a0)
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SREG x18, (18 * CPU_SIZEOF_POINTER)(a0)
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SREG x19, (19 * CPU_SIZEOF_POINTER)(a0)
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SREG x20, (20 * CPU_SIZEOF_POINTER)(a0)
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SREG x21, (21 * CPU_SIZEOF_POINTER)(a0)
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SREG x22, (22 * CPU_SIZEOF_POINTER)(a0)
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SREG x23, (23 * CPU_SIZEOF_POINTER)(a0)
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SREG x24, (24 * CPU_SIZEOF_POINTER)(a0)
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SREG x25, (25 * CPU_SIZEOF_POINTER)(a0)
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SREG x26, (26 * CPU_SIZEOF_POINTER)(a0)
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SREG x27, (27 * CPU_SIZEOF_POINTER)(a0)
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SREG x28, (28 * CPU_SIZEOF_POINTER)(a0)
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SREG x29, (28 * CPU_SIZEOF_POINTER)(a0)
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SREG x30, (30 * CPU_SIZEOF_POINTER)(a0)
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SREG x31, (31 * CPU_SIZEOF_POINTER)(a0)
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SYM(restore):
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LREG x1, (1 * CPU_SIZEOF_POINTER)(a1)
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LREG x2, (2 * CPU_SIZEOF_POINTER)(a1)
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LREG x3, (3 * CPU_SIZEOF_POINTER)(a1)
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LREG x4, (4 * CPU_SIZEOF_POINTER)(a1)
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LREG x5, (5 * CPU_SIZEOF_POINTER)(a1)
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LREG x6, (6 * CPU_SIZEOF_POINTER)(a1)
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LREG x7, (7 * CPU_SIZEOF_POINTER)(a1)
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LREG x8, (8 * CPU_SIZEOF_POINTER)(a1)
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LREG x9, (9 * CPU_SIZEOF_POINTER)(a1)
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LREG x10, (10 * CPU_SIZEOF_POINTER)(a1)
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/* Skip a1/x11 */
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LREG x12, (12 * CPU_SIZEOF_POINTER)(a1)
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LREG x13, (13 * CPU_SIZEOF_POINTER)(a1)
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LREG x14, (14 * CPU_SIZEOF_POINTER)(a1)
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LREG x15, (15 * CPU_SIZEOF_POINTER)(a1)
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LREG x16, (16 * CPU_SIZEOF_POINTER)(a1)
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LREG x17, (17 * CPU_SIZEOF_POINTER)(a1)
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LREG x18, (18 * CPU_SIZEOF_POINTER)(a1)
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LREG x19, (19 * CPU_SIZEOF_POINTER)(a1)
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LREG x20, (20 * CPU_SIZEOF_POINTER)(a1)
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LREG x21, (21 * CPU_SIZEOF_POINTER)(a1)
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LREG x22, (22 * CPU_SIZEOF_POINTER)(a1)
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LREG x23, (23 * CPU_SIZEOF_POINTER)(a1)
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LREG x24, (24 * CPU_SIZEOF_POINTER)(a1)
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LREG x25, (25 * CPU_SIZEOF_POINTER)(a1)
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LREG x26, (26 * CPU_SIZEOF_POINTER)(a1)
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LREG x27, (27 * CPU_SIZEOF_POINTER)(a1)
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LREG x28, (28 * CPU_SIZEOF_POINTER)(a1)
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LREG x29, (29 * CPU_SIZEOF_POINTER)(a1)
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LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
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/* Load mstatus */
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LREG x31, (32 * CPU_SIZEOF_POINTER)(a1)
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csrw mstatus, x31
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LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
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||||||
|
|
||||||
|
LREG x11, (11 * CPU_SIZEOF_POINTER)(a1)
|
||||||
|
|
||||||
|
ret
|
||||||
|
|
||||||
|
SYM(_CPU_Context_restore):
|
||||||
|
mv a1, a0
|
||||||
|
j restore
|
||||||
|
|
||||||
|
/* TODO no FP support for riscv32 yet */
|
||||||
|
SYM(_CPU_Context_restore_fp):
|
||||||
|
nop
|
||||||
|
|
||||||
|
SYM(_CPU_Context_save_fp):
|
||||||
|
nop
|
||||||
201
cpukit/score/cpu/riscv32/riscv-context-validate.S
Normal file
201
cpukit/score/cpu/riscv32/riscv-context-validate.S
Normal file
@@ -0,0 +1,201 @@
|
|||||||
|
/*
|
||||||
|
* Copyrigh (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAVE_CONFIG_H
|
||||||
|
#include "config.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtems/asm.h>
|
||||||
|
#include <rtems/score/cpu.h>
|
||||||
|
|
||||||
|
.section .text
|
||||||
|
|
||||||
|
#define SREG sw
|
||||||
|
#define LREG lw
|
||||||
|
|
||||||
|
PUBLIC(_CPU_Context_validate)
|
||||||
|
SYM(_CPU_Context_validate):
|
||||||
|
addi sp, sp, -144
|
||||||
|
|
||||||
|
SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
/* Skip x2/sp */
|
||||||
|
SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
/* Fill */
|
||||||
|
|
||||||
|
/* t0 is used for temporary values */
|
||||||
|
mv t0, x0
|
||||||
|
|
||||||
|
/* x31 contains the stack pointer */
|
||||||
|
mv x31, sp
|
||||||
|
|
||||||
|
.macro fill_register reg
|
||||||
|
addi t0, t0, 1
|
||||||
|
mv \reg, t0
|
||||||
|
.endm
|
||||||
|
|
||||||
|
fill_register x1
|
||||||
|
fill_register x2
|
||||||
|
fill_register x3
|
||||||
|
fill_register x4
|
||||||
|
fill_register x5
|
||||||
|
fill_register x6
|
||||||
|
fill_register x7
|
||||||
|
fill_register x8
|
||||||
|
fill_register x9
|
||||||
|
fill_register x10
|
||||||
|
fill_register x11
|
||||||
|
fill_register x12
|
||||||
|
fill_register x13
|
||||||
|
fill_register x14
|
||||||
|
fill_register x15
|
||||||
|
fill_register x16
|
||||||
|
fill_register x17
|
||||||
|
fill_register x18
|
||||||
|
fill_register x19
|
||||||
|
fill_register x20
|
||||||
|
fill_register x21
|
||||||
|
fill_register x22
|
||||||
|
fill_register x23
|
||||||
|
fill_register x24
|
||||||
|
fill_register x25
|
||||||
|
fill_register x26
|
||||||
|
fill_register x27
|
||||||
|
fill_register x28
|
||||||
|
fill_register x29
|
||||||
|
fill_register x30
|
||||||
|
fill_register x31
|
||||||
|
|
||||||
|
/* Check */
|
||||||
|
check:
|
||||||
|
|
||||||
|
.macro check_register reg
|
||||||
|
addi t0, t0, 1
|
||||||
|
bne \reg, t0, restore
|
||||||
|
.endm
|
||||||
|
|
||||||
|
bne x31, sp, restore
|
||||||
|
|
||||||
|
mv t0, x0
|
||||||
|
|
||||||
|
check_register x1
|
||||||
|
check_register x2
|
||||||
|
check_register x3
|
||||||
|
check_register x4
|
||||||
|
check_register x5
|
||||||
|
check_register x6
|
||||||
|
check_register x7
|
||||||
|
check_register x8
|
||||||
|
check_register x9
|
||||||
|
check_register x10
|
||||||
|
check_register x11
|
||||||
|
check_register x12
|
||||||
|
check_register x13
|
||||||
|
check_register x14
|
||||||
|
check_register x15
|
||||||
|
check_register x16
|
||||||
|
check_register x17
|
||||||
|
check_register x18
|
||||||
|
check_register x19
|
||||||
|
check_register x20
|
||||||
|
check_register x21
|
||||||
|
check_register x22
|
||||||
|
check_register x23
|
||||||
|
check_register x24
|
||||||
|
check_register x25
|
||||||
|
check_register x26
|
||||||
|
check_register x27
|
||||||
|
check_register x28
|
||||||
|
check_register x29
|
||||||
|
check_register x30
|
||||||
|
check_register x31
|
||||||
|
|
||||||
|
j check
|
||||||
|
|
||||||
|
/* Restore */
|
||||||
|
restore:
|
||||||
|
LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
/* Skip sp/x2 */
|
||||||
|
LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
addi sp, sp, 144
|
||||||
|
ret
|
||||||
50
cpukit/score/cpu/riscv32/riscv-context-volatile-clobber.S
Normal file
50
cpukit/score/cpu/riscv32/riscv-context-volatile-clobber.S
Normal file
@@ -0,0 +1,50 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAVE_CONFIG_H
|
||||||
|
#include "config.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtems/asm.h>
|
||||||
|
|
||||||
|
.section .text
|
||||||
|
|
||||||
|
PUBLIC(_CPU_Context_volatile_clobber)
|
||||||
|
SYM(_CPU_Context_volatile_clobber):
|
||||||
|
|
||||||
|
.macro clobber_register reg
|
||||||
|
addi t0, t0, -1
|
||||||
|
mv \reg, t0
|
||||||
|
.endm
|
||||||
|
|
||||||
|
clobber_register a0
|
||||||
|
clobber_register a1
|
||||||
|
clobber_register a2
|
||||||
|
clobber_register a3
|
||||||
|
clobber_register a4
|
||||||
|
clobber_register a5
|
||||||
|
clobber_register a6
|
||||||
|
|
||||||
|
ret
|
||||||
39
cpukit/score/cpu/riscv32/riscv-exception-default.c
Normal file
39
cpukit/score/cpu/riscv32/riscv-exception-default.c
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAVE_CONFIG_H
|
||||||
|
#include "config.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtems/score/cpu.h>
|
||||||
|
#include <rtems/fatal.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
void _RISCV_Exception_default(uint32_t vector, CPU_Exception_frame *frame);
|
||||||
|
|
||||||
|
void _RISCV_Exception_default(uint32_t vector, CPU_Exception_frame *frame)
|
||||||
|
{
|
||||||
|
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
|
||||||
|
}
|
||||||
41
cpukit/score/cpu/riscv32/riscv-exception-frame-print.c
Normal file
41
cpukit/score/cpu/riscv32/riscv-exception-frame-print.c
Normal file
@@ -0,0 +1,41 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAVE_CONFIG_H
|
||||||
|
#include "config.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtems/score/cpu.h>
|
||||||
|
#include <rtems/bspIo.h>
|
||||||
|
#include <inttypes.h>
|
||||||
|
|
||||||
|
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for ( i = 0; i < 32; ++i ) {
|
||||||
|
printk( "x%02i = 0x%016" PRIx32 "\n", i, frame->x[i]);
|
||||||
|
}
|
||||||
|
}
|
||||||
220
cpukit/score/cpu/riscv32/riscv-exception-handler.S
Normal file
220
cpukit/score/cpu/riscv32/riscv-exception-handler.S
Normal file
@@ -0,0 +1,220 @@
|
|||||||
|
/**
|
||||||
|
* @file
|
||||||
|
*
|
||||||
|
* @ingroup ScoreCPU
|
||||||
|
*
|
||||||
|
* @brief riscv32 exception support implementation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015 University of York.
|
||||||
|
* Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAVE_CONFIG_H
|
||||||
|
#include "config.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtems/score/cpu.h>
|
||||||
|
|
||||||
|
#include <rtems/asm.h>
|
||||||
|
#include <rtems/score/percpu.h>
|
||||||
|
|
||||||
|
# define LREG lw
|
||||||
|
# define SREG sw
|
||||||
|
|
||||||
|
EXTERN(bsp_start_vector_table_begin)
|
||||||
|
EXTERN(_Thread_Dispatch)
|
||||||
|
PUBLIC(ISR_Handler)
|
||||||
|
|
||||||
|
.section .text, "ax"
|
||||||
|
.align 4
|
||||||
|
TYPE_FUNC(ISR_Handler)
|
||||||
|
SYM(ISR_Handler):
|
||||||
|
addi sp, sp, -144
|
||||||
|
|
||||||
|
SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
/* Skip x2/sp */
|
||||||
|
SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
/* Exception level related registers */
|
||||||
|
csrr a0, mstatus
|
||||||
|
SREG a0, (32 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
csrr a0, mcause
|
||||||
|
SREG a0, (33 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
csrr a1, mepc
|
||||||
|
SREG a1, (34 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
/* FIXME Only handle interrupts for now (MSB = 1) */
|
||||||
|
andi a0, a0, 0xf
|
||||||
|
|
||||||
|
/* Increment nesting level */
|
||||||
|
la t0, ISR_NEST_LEVEL
|
||||||
|
|
||||||
|
/* Disable multitasking */
|
||||||
|
la t1, THREAD_DISPATCH_DISABLE_LEVEL
|
||||||
|
|
||||||
|
LREG t2, (t0)
|
||||||
|
LREG t3, (t1)
|
||||||
|
addi t2, t2, 1
|
||||||
|
addi t3, t3, 1
|
||||||
|
SREG t2, (t0)
|
||||||
|
SREG t3, (t1)
|
||||||
|
|
||||||
|
/* Save interrupted task stack pointer */
|
||||||
|
addi t4, sp, 144
|
||||||
|
SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
/* Keep sp (Exception frame address) in s1 */
|
||||||
|
mv s1, sp
|
||||||
|
|
||||||
|
/* Call the exception handler from vector table */
|
||||||
|
|
||||||
|
/* First function arg for C handler is vector number,
|
||||||
|
* and the second is a pointer to exception frame.
|
||||||
|
* a0/mcause/vector number is already loaded above */
|
||||||
|
mv a1, sp
|
||||||
|
|
||||||
|
/* calculate the offset */
|
||||||
|
la t5, bsp_start_vector_table_begin
|
||||||
|
slli t6, a0, 2
|
||||||
|
add t5, t5, t6
|
||||||
|
LREG t5, (t5)
|
||||||
|
|
||||||
|
/* Do not switch stacks if we are in a nested interrupt. At
|
||||||
|
* this point t2 should be holding ISR_NEST_LEVEL value.
|
||||||
|
*/
|
||||||
|
li s0, 1
|
||||||
|
bgtu t2, s0, jump_to_c_handler
|
||||||
|
|
||||||
|
/* Switch to RTEMS dedicated interrupt stack */
|
||||||
|
la sp, INTERRUPT_STACK_HIGH
|
||||||
|
LREG sp, (sp)
|
||||||
|
|
||||||
|
jump_to_c_handler:
|
||||||
|
jalr t5
|
||||||
|
|
||||||
|
/* Switch back to the interrupted task stack */
|
||||||
|
mv sp, s1
|
||||||
|
|
||||||
|
/* Decrement nesting level */
|
||||||
|
la t0, ISR_NEST_LEVEL
|
||||||
|
|
||||||
|
/* Enable multitasking */
|
||||||
|
la t1, THREAD_DISPATCH_DISABLE_LEVEL
|
||||||
|
|
||||||
|
LREG t2, (t0)
|
||||||
|
LREG t3, (t1)
|
||||||
|
addi t2, t2, -1
|
||||||
|
addi t3, t3, -1
|
||||||
|
SREG t2, (t0)
|
||||||
|
SREG t3, (t1)
|
||||||
|
|
||||||
|
/* Check if _ISR_Nest_level > 0 */
|
||||||
|
bgtz t2, exception_frame_restore
|
||||||
|
|
||||||
|
/* Check if _Thread_Dispatch_disable_level > 0 */
|
||||||
|
bgtz t3, exception_frame_restore
|
||||||
|
|
||||||
|
/* Check if dispatch needed */
|
||||||
|
la x31, DISPATCH_NEEDED
|
||||||
|
LREG x31, (x31)
|
||||||
|
beqz x31, exception_frame_restore
|
||||||
|
|
||||||
|
la x31, _Thread_Dispatch
|
||||||
|
jalr x31
|
||||||
|
|
||||||
|
SYM(exception_frame_restore):
|
||||||
|
LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
/* Skip sp/x2 */
|
||||||
|
LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
/* Load mstatus */
|
||||||
|
LREG x31, (32 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
csrw mstatus, x31
|
||||||
|
/* Load mepc */
|
||||||
|
LREG x31, (34 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
csrw mepc, x31
|
||||||
|
|
||||||
|
LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
|
||||||
|
|
||||||
|
/* Unwind exception frame */
|
||||||
|
addi sp, sp, 144
|
||||||
|
|
||||||
|
mret
|
||||||
120
cpukit/score/cpu/riscv32/rtems/asm.h
Normal file
120
cpukit/score/cpu/riscv32/rtems/asm.h
Normal file
@@ -0,0 +1,120 @@
|
|||||||
|
/**
|
||||||
|
* @file rtems/asm.h
|
||||||
|
*
|
||||||
|
* This include file attempts to address the problems
|
||||||
|
* caused by incompatible flavors of assemblers and
|
||||||
|
* toolsets. It primarily addresses variations in the
|
||||||
|
* use of leading underscores on symbols and the requirement
|
||||||
|
* that register names be preceded by a %.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* NOTE: The spacing in the use of these macros
|
||||||
|
* is critical to them working as advertised.
|
||||||
|
*
|
||||||
|
* This file is based on similar code found in newlib available
|
||||||
|
* from ftp.cygnus.com. The file which was used had no copyright
|
||||||
|
* notice. This file is freely distributable as long as the source
|
||||||
|
* of the file is noted. This file is:
|
||||||
|
*
|
||||||
|
* Copyright (c) 2015 University of York.
|
||||||
|
* Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* COPYRIGHT (c) 1994-1997.
|
||||||
|
* On-Line Applications Research Corporation (OAR).
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __RISCV_ASM_H
|
||||||
|
#define __RISCV_ASM_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Indicate we are in an assembly file and get the basic CPU definitions.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ASM
|
||||||
|
#define ASM
|
||||||
|
#endif
|
||||||
|
#include <rtems/score/cpuopts.h>
|
||||||
|
#include <rtems/score/riscv.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Recent versions of GNU cpp define variables which indicate the
|
||||||
|
* need for underscores and percents. If not using GNU cpp or
|
||||||
|
* the version does not support this, then you will obviously
|
||||||
|
* have to define these as appropriate.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __USER_LABEL_PREFIX__
|
||||||
|
#define __USER_LABEL_PREFIX__ _
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __REGISTER_PREFIX__
|
||||||
|
#define __REGISTER_PREFIX__
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ANSI concatenation macros. */
|
||||||
|
|
||||||
|
#define CONCAT1(a, b) CONCAT2(a, b)
|
||||||
|
#define CONCAT2(a, b) a ## b
|
||||||
|
|
||||||
|
/* Use the right prefix for global labels. */
|
||||||
|
|
||||||
|
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
|
||||||
|
|
||||||
|
/* Use the right prefix for registers. */
|
||||||
|
|
||||||
|
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* define macros for all of the registers on this CPU
|
||||||
|
*
|
||||||
|
* EXAMPLE: #define d0 REG (d0)
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define macros to handle section beginning and ends.
|
||||||
|
*/
|
||||||
|
#define BEGIN_CODE_DCL .text
|
||||||
|
#define END_CODE_DCL
|
||||||
|
#define BEGIN_DATA_DCL .data
|
||||||
|
#define END_DATA_DCL
|
||||||
|
#define BEGIN_CODE .text
|
||||||
|
#define END_CODE
|
||||||
|
#define BEGIN_DATA
|
||||||
|
#define END_DATA
|
||||||
|
#define BEGIN_BSS
|
||||||
|
#define END_BSS
|
||||||
|
#define END
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Following must be tailor for a particular flavor of the C compiler.
|
||||||
|
* They may need to put underscores in front of the symbols.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PUBLIC(sym) .global SYM (sym)
|
||||||
|
#define EXTERN(sym) .extern SYM (sym)
|
||||||
|
#define TYPE_FUNC(sym) .type SYM (sym), %function
|
||||||
|
|
||||||
|
#endif
|
||||||
585
cpukit/score/cpu/riscv32/rtems/score/cpu.h
Normal file
585
cpukit/score/cpu/riscv32/rtems/score/cpu.h
Normal file
@@ -0,0 +1,585 @@
|
|||||||
|
/**
|
||||||
|
* @file rtems/score/cpu.h
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
*
|
||||||
|
* Copyright (c) 2015 University of York.
|
||||||
|
* Hesham Almatary <hesham@alumni.york.ac.uk>
|
||||||
|
*
|
||||||
|
* COPYRIGHT (c) 1989-1999.
|
||||||
|
* On-Line Applications Research Corporation (OAR).
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _RISCV_CPU_H
|
||||||
|
#define _RISCV_CPU_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rtems/score/riscv.h> /* pick up machine definitions */
|
||||||
|
#include <rtems/score/types.h>
|
||||||
|
#include <rtems/score/riscv-utility.h>
|
||||||
|
#ifndef ASM
|
||||||
|
#include <rtems/bspIo.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdio.h> /* for printk */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CPU_INLINE_ENABLE_DISPATCH FALSE
|
||||||
|
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
|
||||||
|
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
|
||||||
|
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
|
||||||
|
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
|
||||||
|
#define CPU_ISR_PASSES_FRAME_POINTER 1
|
||||||
|
#define CPU_HARDWARE_FP FALSE
|
||||||
|
#define CPU_SOFTWARE_FP FALSE
|
||||||
|
#define CPU_ALL_TASKS_ARE_FP FALSE
|
||||||
|
#define CPU_IDLE_TASK_IS_FP FALSE
|
||||||
|
#define CPU_USE_DEFERRED_FP_SWITCH FALSE
|
||||||
|
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
|
||||||
|
#define CPU_STACK_GROWS_UP FALSE
|
||||||
|
|
||||||
|
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64)))
|
||||||
|
#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
|
||||||
|
#define CPU_BIG_ENDIAN FALSE
|
||||||
|
#define CPU_LITTLE_ENDIAN TRUE
|
||||||
|
#define CPU_MODES_INTERRUPT_MASK 0x00000001
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Processor defined structures required for cpukit/score.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ASM
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
/* riscv32 has 32 32-bit general purpose registers (x0-x31). */
|
||||||
|
uint32_t x[32];
|
||||||
|
|
||||||
|
/* Special purpose registers */
|
||||||
|
uint32_t mstatus;
|
||||||
|
uint32_t mcause;
|
||||||
|
uint32_t mepc;
|
||||||
|
#ifdef RTEMS_SMP
|
||||||
|
/**
|
||||||
|
* @brief On SMP configurations the thread context must contain a boolean
|
||||||
|
* indicator to signal if this context is executing on a processor.
|
||||||
|
*
|
||||||
|
* This field must be updated during a context switch. The context switch
|
||||||
|
* to the heir must wait until the heir context indicates that it is no
|
||||||
|
* longer executing on a processor. The context switch must also check if
|
||||||
|
* a thread dispatch is necessary to honor updates of the heir thread for
|
||||||
|
* this processor. This indicator must be updated using an atomic test and
|
||||||
|
* set operation to ensure that at most one processor uses the heir
|
||||||
|
* context at the same time.
|
||||||
|
*
|
||||||
|
* @code
|
||||||
|
* void _CPU_Context_switch(
|
||||||
|
* Context_Control *executing,
|
||||||
|
* Context_Control *heir
|
||||||
|
* )
|
||||||
|
* {
|
||||||
|
* save( executing );
|
||||||
|
*
|
||||||
|
* executing->is_executing = false;
|
||||||
|
* memory_barrier();
|
||||||
|
*
|
||||||
|
* if ( test_and_set( &heir->is_executing ) ) {
|
||||||
|
* do {
|
||||||
|
* Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot();
|
||||||
|
*
|
||||||
|
* if ( cpu_self->dispatch_necessary ) {
|
||||||
|
* heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
|
||||||
|
* }
|
||||||
|
* } while ( test_and_set( &heir->is_executing ) );
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* restore( heir );
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
*/
|
||||||
|
volatile bool is_executing;
|
||||||
|
#endif
|
||||||
|
} Context_Control;
|
||||||
|
|
||||||
|
#define _CPU_Context_Get_SP( _context ) \
|
||||||
|
(_context)->x[2]
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
/** TODO FPU registers are listed here */
|
||||||
|
double some_float_register;
|
||||||
|
} Context_Control_fp;
|
||||||
|
|
||||||
|
typedef Context_Control CPU_Interrupt_frame;
|
||||||
|
|
||||||
|
#define CPU_CONTEXT_FP_SIZE 0
|
||||||
|
Context_Control_fp _CPU_Null_fp_context;
|
||||||
|
|
||||||
|
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
|
||||||
|
#define CPU_STACK_MINIMUM_SIZE 4096
|
||||||
|
#define CPU_ALIGNMENT 8
|
||||||
|
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
|
||||||
|
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
|
||||||
|
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
|
||||||
|
#define CPU_STACK_ALIGNMENT 8
|
||||||
|
#define _CPU_Initialize_vectors()
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Disable all interrupts for an RTEMS critical section. The previous
|
||||||
|
* level is returned in _level.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
static inline uint32_t riscv_interrupt_disable( void )
|
||||||
|
{
|
||||||
|
register uint32_t status = read_csr(mstatus);
|
||||||
|
clear_csr(mstatus, MSTATUS_MIE);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void riscv_interrupt_enable(uint32_t level)
|
||||||
|
{
|
||||||
|
write_csr(mstatus, level);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define _CPU_ISR_Disable( _level ) \
|
||||||
|
_level = riscv_interrupt_disable()
|
||||||
|
|
||||||
|
#define _CPU_ISR_Enable( _level ) \
|
||||||
|
riscv_interrupt_enable( _level )
|
||||||
|
|
||||||
|
#define _CPU_ISR_Flash( _level ) \
|
||||||
|
do{ \
|
||||||
|
_CPU_ISR_Enable( _level ); \
|
||||||
|
riscv_interrupt_disable(); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
|
||||||
|
{
|
||||||
|
return ( level & MSTATUS_MIE ) != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _CPU_ISR_Set_level( uint32_t level );
|
||||||
|
|
||||||
|
uint32_t _CPU_ISR_Get_level( void );
|
||||||
|
|
||||||
|
/* end of ISR handler macros */
|
||||||
|
|
||||||
|
/* Context handler macros */
|
||||||
|
#define RISCV_GCC_RED_ZONE_SIZE 128
|
||||||
|
|
||||||
|
void _CPU_Context_Initialize(
|
||||||
|
Context_Control *context,
|
||||||
|
void *stack_area_begin,
|
||||||
|
size_t stack_area_size,
|
||||||
|
uint32_t new_level,
|
||||||
|
void (*entry_point)( void ),
|
||||||
|
bool is_fp,
|
||||||
|
void *tls_area
|
||||||
|
);
|
||||||
|
|
||||||
|
#define _CPU_Context_Restart_self( _the_context ) \
|
||||||
|
_CPU_Context_restore( (_the_context) )
|
||||||
|
|
||||||
|
|
||||||
|
#define _CPU_Context_Fp_start( _base, _offset ) \
|
||||||
|
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
|
||||||
|
|
||||||
|
#define _CPU_Context_Initialize_fp( _destination ) \
|
||||||
|
{ \
|
||||||
|
*(*(_destination)) = _CPU_Null_fp_context; \
|
||||||
|
}
|
||||||
|
|
||||||
|
extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
|
||||||
|
RTEMS_NO_RETURN;
|
||||||
|
|
||||||
|
/* end of Fatal Error manager macros */
|
||||||
|
|
||||||
|
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
|
||||||
|
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
|
||||||
|
|
||||||
|
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
|
||||||
|
|
||||||
|
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
|
||||||
|
{ \
|
||||||
|
(_output) = 0; /* do something to prevent warnings */ \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* end of Bitfield handler macros */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This routine builds the mask which corresponds to the bit fields
|
||||||
|
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
|
||||||
|
* for that routine.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
|
||||||
|
|
||||||
|
#define _CPU_Priority_Mask( _bit_number ) \
|
||||||
|
(1 << _bit_number)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
|
||||||
|
|
||||||
|
#define _CPU_Priority_bits_index( _priority ) \
|
||||||
|
(_priority)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CPU_MAXIMUM_PROCESSORS 32
|
||||||
|
|
||||||
|
#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE
|
||||||
|
#define CPU_TIMESTAMP_USE_INT64 TRUE
|
||||||
|
#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
/* There is no CPU specific per-CPU state */
|
||||||
|
} CPU_Per_CPU_control;
|
||||||
|
#endif /* ASM */
|
||||||
|
|
||||||
|
#define CPU_SIZEOF_POINTER 4
|
||||||
|
#define CPU_EXCEPTION_FRAME_SIZE 128
|
||||||
|
#define CPU_PER_CPU_CONTROL_SIZE 0
|
||||||
|
|
||||||
|
#ifndef ASM
|
||||||
|
typedef uint16_t Priority_bit_map_Word;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
uint32_t x[32];;
|
||||||
|
} CPU_Exception_frame;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Prints the exception frame via printk().
|
||||||
|
*
|
||||||
|
* @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
|
||||||
|
*/
|
||||||
|
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
|
||||||
|
|
||||||
|
|
||||||
|
/* end of Priority handler macros */
|
||||||
|
|
||||||
|
/* functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Initialize
|
||||||
|
*
|
||||||
|
* This routine performs CPU dependent initialization.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_Initialize(
|
||||||
|
void
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_ISR_install_raw_handler
|
||||||
|
*
|
||||||
|
* This routine installs a "raw" interrupt handler directly into the
|
||||||
|
* processor's vector table.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_ISR_install_raw_handler(
|
||||||
|
uint32_t vector,
|
||||||
|
proc_ptr new_handler,
|
||||||
|
proc_ptr *old_handler
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_ISR_install_vector
|
||||||
|
*
|
||||||
|
* This routine installs an interrupt vector.
|
||||||
|
*
|
||||||
|
* NO_CPU Specific Information:
|
||||||
|
*
|
||||||
|
* XXX document implementation including references if appropriate
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_ISR_install_vector(
|
||||||
|
uint32_t vector,
|
||||||
|
proc_ptr new_handler,
|
||||||
|
proc_ptr *old_handler
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Install_interrupt_stack
|
||||||
|
*
|
||||||
|
* This routine installs the hardware interrupt stack pointer.
|
||||||
|
*
|
||||||
|
* NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
|
||||||
|
* is TRUE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_Install_interrupt_stack( void );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Thread_Idle_body
|
||||||
|
*
|
||||||
|
* This routine is the CPU dependent IDLE thread body.
|
||||||
|
*
|
||||||
|
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
|
||||||
|
* is TRUE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void *_CPU_Thread_Idle_body( uintptr_t ignored );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Context_switch
|
||||||
|
*
|
||||||
|
* This routine switches from the run context to the heir context.
|
||||||
|
*
|
||||||
|
* RISCV Specific Information:
|
||||||
|
*
|
||||||
|
* Please see the comments in the .c file for a description of how
|
||||||
|
* this function works. There are several things to be aware of.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_Context_switch(
|
||||||
|
Context_Control *run,
|
||||||
|
Context_Control *heir
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Context_restore
|
||||||
|
*
|
||||||
|
* This routine is generally used only to restart self in an
|
||||||
|
* efficient manner. It may simply be a label in _CPU_Context_switch.
|
||||||
|
*
|
||||||
|
* NOTE: May be unnecessary to reload some registers.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_Context_restore(
|
||||||
|
Context_Control *new_context
|
||||||
|
) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Context_save_fp
|
||||||
|
*
|
||||||
|
* This routine saves the floating point context passed to it.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_Context_save_fp(
|
||||||
|
void **fp_context_ptr
|
||||||
|
);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _CPU_Context_restore_fp
|
||||||
|
*
|
||||||
|
* This routine restores the floating point context passed to it.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_Context_restore_fp(
|
||||||
|
void **fp_context_ptr
|
||||||
|
);
|
||||||
|
|
||||||
|
/* The following routine swaps the endian format of an unsigned int.
|
||||||
|
* It must be static because it is referenced indirectly.
|
||||||
|
*
|
||||||
|
* This version will work on any processor, but if there is a better
|
||||||
|
* way for your CPU PLEASE use it. The most common way to do this is to:
|
||||||
|
*
|
||||||
|
* swap least significant two bytes with 16-bit rotate
|
||||||
|
* swap upper and lower 16-bits
|
||||||
|
* swap most significant two bytes with 16-bit rotate
|
||||||
|
*
|
||||||
|
* Some CPUs have special instructions which swap a 32-bit quantity in
|
||||||
|
* a single instruction (e.g. i486). It is probably best to avoid
|
||||||
|
* an "endian swapping control bit" in the CPU. One good reason is
|
||||||
|
* that interrupts would probably have to be disabled to insure that
|
||||||
|
* an interrupt does not try to access the same "chunk" with the wrong
|
||||||
|
* endian. Another good reason is that on some CPUs, the endian bit
|
||||||
|
* endianness for ALL fetches -- both code and data -- so the code
|
||||||
|
* will be fetched incorrectly.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
static inline unsigned int CPU_swap_u32(
|
||||||
|
unsigned int value
|
||||||
|
)
|
||||||
|
{
|
||||||
|
uint32_t byte1, byte2, byte3, byte4, swapped;
|
||||||
|
|
||||||
|
byte4 = (value >> 24) & 0xff;
|
||||||
|
byte3 = (value >> 16) & 0xff;
|
||||||
|
byte2 = (value >> 8) & 0xff;
|
||||||
|
byte1 = value & 0xff;
|
||||||
|
|
||||||
|
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
|
||||||
|
return ( swapped );
|
||||||
|
}
|
||||||
|
|
||||||
|
#define CPU_swap_u16( value ) \
|
||||||
|
(((value&0xff) << 8) | ((value >> 8)&0xff))
|
||||||
|
|
||||||
|
static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
|
||||||
|
{
|
||||||
|
/* TODO */
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void _CPU_Context_validate( uintptr_t pattern )
|
||||||
|
{
|
||||||
|
while (1) {
|
||||||
|
/* TODO */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
typedef uint32_t CPU_Counter_ticks;
|
||||||
|
|
||||||
|
CPU_Counter_ticks _CPU_Counter_read( void );
|
||||||
|
|
||||||
|
#ifdef RTEMS_SMP
|
||||||
|
/**
|
||||||
|
* @brief Performs CPU specific SMP initialization in the context of the boot
|
||||||
|
* processor.
|
||||||
|
*
|
||||||
|
* This function is invoked on the boot processor during system
|
||||||
|
* initialization. All interrupt stacks are allocated at this point in case
|
||||||
|
* the CPU port allocates the interrupt stacks. This function is called
|
||||||
|
* before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
|
||||||
|
* used.
|
||||||
|
*
|
||||||
|
* @return The count of physically or virtually available processors.
|
||||||
|
* Depending on the configuration the application may use not all processors.
|
||||||
|
*/
|
||||||
|
uint32_t _CPU_SMP_Initialize( void );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Starts a processor specified by its index.
|
||||||
|
*
|
||||||
|
* This function is invoked on the boot processor during system
|
||||||
|
* initialization.
|
||||||
|
*
|
||||||
|
* This function will be called after _CPU_SMP_Initialize().
|
||||||
|
*
|
||||||
|
* @param[in] cpu_index The processor index.
|
||||||
|
*
|
||||||
|
* @retval true Successful operation.
|
||||||
|
* @retval false Unable to start this processor.
|
||||||
|
*/
|
||||||
|
bool _CPU_SMP_Start_processor( uint32_t cpu_index );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Performs final steps of CPU specific SMP initialization in the
|
||||||
|
* context of the boot processor.
|
||||||
|
*
|
||||||
|
* This function is invoked on the boot processor during system
|
||||||
|
* initialization.
|
||||||
|
*
|
||||||
|
* This function will be called after all processors requested by the
|
||||||
|
* application have been started.
|
||||||
|
*
|
||||||
|
* @param[in] cpu_count The minimum value of the count of processors
|
||||||
|
* requested by the application configuration and the count of physically or
|
||||||
|
* virtually available processors.
|
||||||
|
*/
|
||||||
|
void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the index of the current processor.
|
||||||
|
*
|
||||||
|
* An architecture specific method must be used to obtain the index of the
|
||||||
|
* current processor in the system. The set of processor indices is the
|
||||||
|
* range of integers starting with zero up to the processor count minus one.
|
||||||
|
*/
|
||||||
|
uint32_t _CPU_SMP_Get_current_processor( void );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sends an inter-processor interrupt to the specified target
|
||||||
|
* processor.
|
||||||
|
*
|
||||||
|
* This operation is undefined for target processor indices out of range.
|
||||||
|
*
|
||||||
|
* @param[in] target_processor_index The target processor index.
|
||||||
|
*/
|
||||||
|
void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Broadcasts a processor event.
|
||||||
|
*
|
||||||
|
* Some architectures provide a low-level synchronization primitive for
|
||||||
|
* processors in a multi-processor environment. Processors waiting for this
|
||||||
|
* event may go into a low-power state and stop generating system bus
|
||||||
|
* transactions. This function must ensure that preceding store operations
|
||||||
|
* can be observed by other processors.
|
||||||
|
*
|
||||||
|
* @see _CPU_SMP_Processor_event_receive().
|
||||||
|
*/
|
||||||
|
void _CPU_SMP_Processor_event_broadcast( void );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Receives a processor event.
|
||||||
|
*
|
||||||
|
* This function will wait for the processor event and may wait forever if no
|
||||||
|
* such event arrives.
|
||||||
|
*
|
||||||
|
* @see _CPU_SMP_Processor_event_broadcast().
|
||||||
|
*/
|
||||||
|
static inline void _CPU_SMP_Processor_event_receive( void )
|
||||||
|
{
|
||||||
|
__asm__ volatile ( "" : : : "memory" );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets the is executing indicator of the thread context.
|
||||||
|
*
|
||||||
|
* @param[in] context The context.
|
||||||
|
*/
|
||||||
|
static inline bool _CPU_Context_Get_is_executing(
|
||||||
|
const Context_Control *context
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return context->is_executing;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the is executing indicator of the thread context.
|
||||||
|
*
|
||||||
|
* @param[in] context The context.
|
||||||
|
* @param[in] is_executing The new value for the is executing indicator.
|
||||||
|
*/
|
||||||
|
static inline void _CPU_Context_Set_is_executing(
|
||||||
|
Context_Control *context,
|
||||||
|
bool is_executing
|
||||||
|
)
|
||||||
|
{
|
||||||
|
context->is_executing = is_executing;
|
||||||
|
}
|
||||||
|
#endif /* RTEMS_SMP */
|
||||||
|
|
||||||
|
#endif /* ASM */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
90
cpukit/score/cpu/riscv32/rtems/score/cpu_asm.h
Normal file
90
cpukit/score/cpu/riscv32/rtems/score/cpu_asm.h
Normal file
@@ -0,0 +1,90 @@
|
|||||||
|
/**
|
||||||
|
* @file
|
||||||
|
*
|
||||||
|
* @brief riscv32 Assembly File
|
||||||
|
*
|
||||||
|
* Very loose template for an include file for the cpu_asm.? file
|
||||||
|
* if it is implemented as a ".S" file (preprocessed by cpp) instead
|
||||||
|
* of a ".s" file (preprocessed by gm4 or gasp).
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COPYRIGHT (c) 1989-1999.
|
||||||
|
* On-Line Applications Research Corporation (OAR).
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _RTEMS_SCORE_CPU_ASM_H
|
||||||
|
#define _RTEMS_SCORE_CPU_ASM_H
|
||||||
|
|
||||||
|
/* pull in the generated offsets */
|
||||||
|
|
||||||
|
/*
|
||||||
|
#include <rtems/score/offsets.h>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Hardware General Registers
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Hardware Floating Point Registers
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Hardware Control Registers
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Calling Convention
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Temporary registers
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Floating Point Registers - SW Conventions
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Temporary floating point registers
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* put something here */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* end of file */
|
||||||
31
cpukit/score/cpu/riscv32/rtems/score/cpuatomic.h
Normal file
31
cpukit/score/cpu/riscv32/rtems/score/cpuatomic.h
Normal file
@@ -0,0 +1,31 @@
|
|||||||
|
/*
|
||||||
|
* COPYRIGHT (c) 2012-2013 Deng Hengyi.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
|
||||||
|
#define _RTEMS_SCORE_ATOMIC_CPU_H
|
||||||
|
|
||||||
|
#include <rtems/score/cpustdatomic.h>
|
||||||
|
|
||||||
|
#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
|
||||||
51
cpukit/score/cpu/riscv32/rtems/score/cpuimpl.h
Normal file
51
cpukit/score/cpu/riscv32/rtems/score/cpuimpl.h
Normal file
@@ -0,0 +1,51 @@
|
|||||||
|
/**
|
||||||
|
* @file
|
||||||
|
*
|
||||||
|
* @brief CPU Port Implementation API
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2013 embedded brains GmbH
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _RTEMS_SCORE_CPUIMPL_H
|
||||||
|
#define _RTEMS_SCORE_CPUIMPL_H
|
||||||
|
|
||||||
|
#include <rtems/score/cpu.h>
|
||||||
|
|
||||||
|
#define CPU_PER_CPU_CONTROL_SIZE 0
|
||||||
|
|
||||||
|
#ifndef ASM
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* ASM */
|
||||||
|
|
||||||
|
#endif /* _RTEMS_SCORE_CPUIMPL_H */
|
||||||
1526
cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h
Normal file
1526
cpukit/score/cpu/riscv32/rtems/score/riscv-utility.h
Normal file
File diff suppressed because it is too large
Load Diff
66
cpukit/score/cpu/riscv32/rtems/score/riscv.h
Normal file
66
cpukit/score/cpu/riscv32/rtems/score/riscv.h
Normal file
@@ -0,0 +1,66 @@
|
|||||||
|
/**
|
||||||
|
* @file rtems/score/riscv.h
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This file contains information pertaining to the riscv32 processor.
|
||||||
|
*
|
||||||
|
* COPYRIGHT (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
|
||||||
|
*
|
||||||
|
* Based on code with the following copyright...
|
||||||
|
* COPYRIGHT (c) 1989-1999, 2010.
|
||||||
|
* On-Line Applications Research Corporation (OAR).
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _RTEMS_SCORE_RISCV_H
|
||||||
|
#define _RTEMS_SCORE_RISCV_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This file contains the information required to build
|
||||||
|
* RTEMS for a particular member of the RISCV family.
|
||||||
|
* It does this by setting variables to indicate which
|
||||||
|
* implementation dependent features are present in a particular
|
||||||
|
* member of the family.
|
||||||
|
*
|
||||||
|
* This is a good place to list all the known CPU models
|
||||||
|
* that this port supports and which RTEMS CPU model they correspond
|
||||||
|
* to.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define the name of the CPU family and specific model.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CPU_NAME "RISCV"
|
||||||
|
#define CPU_MODEL_NAME "RISCV"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _RTEMS_SCORE_RISCV_H */
|
||||||
70
cpukit/score/cpu/riscv32/rtems/score/types.h
Normal file
70
cpukit/score/cpu/riscv32/rtems/score/types.h
Normal file
@@ -0,0 +1,70 @@
|
|||||||
|
/**
|
||||||
|
* @file
|
||||||
|
*
|
||||||
|
* @brief riscv32 Architecture Types API
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This include file contains type definitions pertaining to the
|
||||||
|
* RISC-V processor family.
|
||||||
|
*
|
||||||
|
* COPYRIGHT (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _RTEMS_SCORE_TYPES_H
|
||||||
|
#define _RTEMS_SCORE_TYPES_H
|
||||||
|
|
||||||
|
#include <rtems/score/basedefs.h>
|
||||||
|
|
||||||
|
#ifndef ASM
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup ScoreCPU
|
||||||
|
*/
|
||||||
|
/**@{**/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This section defines the basic types for this processor.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** Type that can store a 32-bit integer or a pointer. */
|
||||||
|
typedef uintptr_t CPU_Uint32ptr;
|
||||||
|
|
||||||
|
typedef uint16_t Priority_bit_map_Word;
|
||||||
|
typedef void riscv_isr;
|
||||||
|
typedef void ( *riscv_isr_entry )( void );
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* !ASM */
|
||||||
|
|
||||||
|
#endif
|
||||||
Reference in New Issue
Block a user