forked from Imagelibrary/rtems
2010-12-29 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/include/cpuIdent.c, shared/include/cpuIdent.h: Added support for e500v2. Removed IVPR/IVOR/HWIVOR features since they are included in Book E. * new-exceptions/bspsupport/vectors.h, new-exceptions/bspsupport/ppc_exc.S, new-exceptions/bspsupport/ppc_exc_address.c, new-exceptions/bspsupport/ppc_exc_categories.c, new-exceptions/bspsupport/ppc_exc_initialize.c, new-exceptions/bspsupport/ppc_exc_prologue.c: Added support for e500v2. Added exception vector defines for Book E types. Removed e200 exception vector defines. Added e500 exception vector defines. Unified IVOR calculation for e200 and e500 (e200z1 has hard wired IVOR values).
This commit is contained in:
@@ -71,24 +71,6 @@ ppc_exc_min_prolog_auto:
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.global ppc_exc_tgpr_clr_prolog_size
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ppc_exc_tgpr_clr_prolog_size = . - ppc_exc_tgpr_clr_prolog
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/**
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* @brief Use vector offsets with 16 byte boundaries.
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*
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* This prologue is intended for cores with IVPR/IVOR registers. The e200z1
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* core has hard wired values for the IVOR, thus all values are calculated to
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* match its constraints. The link register will point to the next prologue.
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* This is all right for the vector number calculation due the IVOR offset
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* values.
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*
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* @see ppc_exc_min_prolog_auto();
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*/
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.global ppc_exc_min_prolog_auto_packed
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ppc_exc_min_prolog_auto_packed:
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stwu r1, -EXCEPTION_FRAME_END(r1)
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stw VECTOR_REGISTER, VECTOR_OFFSET(r1)
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mflr VECTOR_REGISTER
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bla wrap_auto_packed
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/*
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* Automatic vector, asynchronous exception; however,
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* automatic vector calculation is less efficient than
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@@ -156,14 +138,6 @@ wrap_auto:
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*/
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b wrap_no_save_frame_register_std
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/* See: wrap_auto */
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wrap_auto_packed:
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stw FRAME_REGISTER, FRAME_OFFSET(r1)
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mflr FRAME_REGISTER
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mtlr VECTOR_REGISTER
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rlwinm VECTOR_REGISTER, FRAME_REGISTER, 28, 26, 31
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b wrap_no_save_frame_register_std
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wrap_auto_async:
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stwu r1, -EXCEPTION_FRAME_END(r1)
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stw FRAME_REGISTER, FRAME_OFFSET(r1)
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@@ -36,6 +36,33 @@ bool bsp_exceptions_in_RAM = true;
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uint32_t ppc_exc_vector_base = 0;
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/*
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* XXX: These values are choosen to directly generate the vector offsets for an
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* e200z1 which has hard wired IVORs (IVOR0=0x00, IVOR1=0x10, IVOR2=0x20, ...).
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*/
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static const uint8_t ivor_values [] = {
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[ASM_BOOKE_CRIT_VECTOR] = 0,
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[ASM_MACH_VECTOR] = 1,
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[ASM_PROT_VECTOR] = 2,
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[ASM_ISI_VECTOR] = 3,
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[ASM_EXT_VECTOR] = 4,
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[ASM_ALIGN_VECTOR] = 5,
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[ASM_PROG_VECTOR] = 6,
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[ASM_FLOAT_VECTOR] = 7,
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[ASM_SYS_VECTOR] = 8,
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[ASM_BOOKE_APU_VECTOR] = 9,
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[ASM_BOOKE_DEC_VECTOR] = 10,
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[ASM_BOOKE_FIT_VECTOR] = 11,
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[ASM_BOOKE_WDOG_VECTOR] = 12,
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[ASM_BOOKE_DTLBMISS_VECTOR] = 13,
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[ASM_BOOKE_ITLBMISS_VECTOR] = 14,
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[ASM_BOOKE_DEBUG_VECTOR] = 15,
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[ASM_E500_SPE_UNAVAILABLE_VECTOR] = 32,
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[ASM_E500_EMB_FP_DATA_VECTOR] = 33,
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[ASM_E500_EMB_FP_ROUND_VECTOR] = 34,
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[ASM_E500_PERFMON_VECTOR] = 35
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};
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void *ppc_exc_vector_address(unsigned vector)
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{
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uintptr_t vector_base = 0xfff00000;
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@@ -65,12 +92,15 @@ void *ppc_exc_vector_address(unsigned vector)
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}
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}
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if (ppc_cpu_has_ivpr_and_ivor()) {
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/*
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* XXX: this directly matches the vector offsets in a e200z1,
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* which has hardwired IVORs (IVOR0=0,IVOR1=0x10,IVOR2=0x20...)
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*/
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vector_offset = (vector - 1) << 4;
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if (
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ppc_cpu_is_bookE() == PPC_BOOKE_STD
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|| ppc_cpu_is_bookE() == PPC_BOOKE_E500
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) {
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if (vector < sizeof(ivor_values) / sizeof(ivor_values [0])) {
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vector_offset = ((uintptr_t) ivor_values [vector]) << 4;
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} else {
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vector_offset = 0;
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}
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}
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if (bsp_exceptions_in_RAM) {
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@@ -150,29 +150,6 @@ static const ppc_exc_categories mpc_860_category_table = {
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[ASM_8XX_DEVPORT_VECTOR] = PPC_EXC_CLASSIC,
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};
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static const ppc_exc_categories e200_category_table = {
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[ASM_MACH_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
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[ASM_PROT_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_ISI_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_EXT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_ALIGN_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
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[ASM_BOOKE_ITLBMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_DTLBMISS_VECTOR] = PPC_EXC_CLASSIC,
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/* FIXME: Depending on HDI0 [DAPUEN] this is a critical or debug exception */
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[ASM_TRACE_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_BOOKE_CRITICAL,
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[ASM_E200_SPE_UNAVAILABLE_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E200_SPE_DATA_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E200_SPE_ROUND_VECTOR] = PPC_EXC_CLASSIC,
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};
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static const ppc_exc_categories e300_category_table = {
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[ASM_RESET_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_MACH_VECTOR] = PPC_EXC_CLASSIC,
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@@ -195,32 +172,49 @@ static const ppc_exc_categories e300_category_table = {
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[ASM_E300_SYSMGMT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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};
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static const ppc_exc_categories e500_category_table = {
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[ASM_MACH_VECTOR] = PPC_EXC_E500_MACHCHK,
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static const ppc_exc_categories e200_category_table = {
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[ASM_BOOKE_CRIT_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
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[ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
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[ASM_TRACE_VECTOR] = PPC_EXC_BOOKE_CRITICAL,
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[ASM_EXT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_MACH_VECTOR] = PPC_EXC_E500_MACHCHK,
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[ASM_PROT_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_ISI_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_EXT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_ALIGN_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
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[ /* APU unavailable */ 0x0b] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
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[ASM_BOOKE_DTLBMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_ITLBMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_60X_DLMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_60X_DSMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_60X_VEC_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_60X_PERFMON_VECTOR] = PPC_EXC_CLASSIC,
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/* FIXME: Depending on HDI0 [DAPUEN] this is a critical or debug exception */
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[ASM_BOOKE_DEBUG_VECTOR] = PPC_EXC_BOOKE_CRITICAL,
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[ /* emb FP data */ 0x15] = PPC_EXC_CLASSIC,
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[ /* emb FP round */ 0x16] = PPC_EXC_CLASSIC,
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[ASM_E500_SPE_UNAVAILABLE_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E500_EMB_FP_DATA_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E500_EMB_FP_ROUND_VECTOR] = PPC_EXC_CLASSIC
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};
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static const ppc_exc_categories e500_category_table = {
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[ASM_MACH_VECTOR] = PPC_EXC_E500_MACHCHK,
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[ASM_PROT_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_ISI_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_EXT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_ALIGN_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
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[ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
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[ASM_BOOKE_DTLBMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_ITLBMISS_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_BOOKE_DEBUG_VECTOR] = PPC_EXC_BOOKE_CRITICAL,
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[ASM_E500_SPE_UNAVAILABLE_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E500_EMB_FP_DATA_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E500_EMB_FP_ROUND_VECTOR] = PPC_EXC_CLASSIC,
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[ASM_E500_PERFMON_VECTOR] = PPC_EXC_CLASSIC
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};
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static const ppc_exc_categories psim_category_table = {
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@@ -274,6 +268,7 @@ const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu)
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case PPC_PSIM:
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return &psim_category_table;
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case PPC_8540:
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case PPC_e500v2:
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return &e500_category_table;
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case PPC_e200z0:
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case PPC_e200z1:
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@@ -33,13 +33,13 @@ uint32_t ppc_exc_cache_wb_check = 1;
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#define MTIVPR(prefix) asm volatile ("mtivpr %0" : : "r" (prefix))
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#define MTIVOR(x, vec) asm volatile ("mtivor"#x" %0" : : "r" (vec))
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static void ppc_exc_initialize_e500(void)
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static void ppc_exc_initialize_booke(void)
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{
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/* Interupt vector prefix register */
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MTIVPR(ppc_exc_vector_base);
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/* Interupt vector offset register */
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MTIVOR(0, ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR)); /* Critical input not (yet) supported; use reset vector */
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/* Interupt vector offset registers */
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MTIVOR(0, ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR));
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MTIVOR(1, ppc_exc_vector_address(ASM_MACH_VECTOR));
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MTIVOR(2, ppc_exc_vector_address(ASM_PROT_VECTOR));
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MTIVOR(3, ppc_exc_vector_address(ASM_ISI_VECTOR));
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@@ -48,45 +48,20 @@ static void ppc_exc_initialize_e500(void)
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MTIVOR(6, ppc_exc_vector_address(ASM_PROG_VECTOR));
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MTIVOR(7, ppc_exc_vector_address(ASM_FLOAT_VECTOR));
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MTIVOR(8, ppc_exc_vector_address(ASM_SYS_VECTOR));
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MTIVOR(9, ppc_exc_vector_address(0x0b));
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MTIVOR(9, ppc_exc_vector_address(ASM_BOOKE_APU_VECTOR));
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MTIVOR(10, ppc_exc_vector_address(ASM_BOOKE_DEC_VECTOR));
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MTIVOR(11, ppc_exc_vector_address(ASM_BOOKE_FIT_VECTOR));
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MTIVOR(12, ppc_exc_vector_address(ASM_BOOKE_WDOG_VECTOR));
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MTIVOR(13, ppc_exc_vector_address(ASM_60X_DSMISS_VECTOR));
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MTIVOR(14, ppc_exc_vector_address(ASM_60X_DLMISS_VECTOR));
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MTIVOR(15, ppc_exc_vector_address(ASM_TRACE_VECTOR));
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MTIVOR(32, ppc_exc_vector_address(ASM_60X_VEC_VECTOR));
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MTIVOR(33, ppc_exc_vector_address(0x16));
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MTIVOR(34, ppc_exc_vector_address(0x15));
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MTIVOR(35, ppc_exc_vector_address(ASM_60X_PERFMON_VECTOR));
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}
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static void ppc_exc_initialize_e200(void)
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{
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/* Interupt vector prefix register */
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MTIVPR(ppc_exc_vector_base);
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if (ppc_cpu_has_ivor()) {
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/* Interupt vector offset register */
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MTIVOR(0, 0); /* Critical input */
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MTIVOR(1, ppc_exc_vector_address( ASM_MACH_VECTOR));
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MTIVOR(2, ppc_exc_vector_address( ASM_PROT_VECTOR));
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MTIVOR(3, ppc_exc_vector_address( ASM_ISI_VECTOR));
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MTIVOR(4, ppc_exc_vector_address( ASM_EXT_VECTOR));
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MTIVOR(5, ppc_exc_vector_address( ASM_ALIGN_VECTOR));
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MTIVOR(6, ppc_exc_vector_address( ASM_PROG_VECTOR));
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MTIVOR(7, ppc_exc_vector_address( ASM_FLOAT_VECTOR));
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MTIVOR(8, ppc_exc_vector_address( ASM_SYS_VECTOR));
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MTIVOR(9, 0); /* APU unavailable */
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MTIVOR(10, ppc_exc_vector_address( ASM_BOOKE_DEC_VECTOR));
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MTIVOR(11, ppc_exc_vector_address( ASM_BOOKE_FIT_VECTOR));
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MTIVOR(12, ppc_exc_vector_address( ASM_BOOKE_WDOG_VECTOR));
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MTIVOR(13, ppc_exc_vector_address( ASM_BOOKE_ITLBMISS_VECTOR));
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MTIVOR(14, ppc_exc_vector_address( ASM_BOOKE_DTLBMISS_VECTOR));
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MTIVOR(15, ppc_exc_vector_address( ASM_TRACE_VECTOR));
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MTIVOR(32, ppc_exc_vector_address( ASM_E200_SPE_UNAVAILABLE_VECTOR));
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MTIVOR(33, ppc_exc_vector_address( ASM_E200_SPE_DATA_VECTOR));
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MTIVOR(34, ppc_exc_vector_address( ASM_E200_SPE_ROUND_VECTOR));
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MTIVOR(13, ppc_exc_vector_address(ASM_BOOKE_DTLBMISS_VECTOR));
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MTIVOR(14, ppc_exc_vector_address(ASM_BOOKE_ITLBMISS_VECTOR));
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MTIVOR(15, ppc_exc_vector_address(ASM_BOOKE_DEBUG_VECTOR));
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if (ppc_cpu_is_e200() || ppc_cpu_is_e500()) {
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MTIVOR(32, ppc_exc_vector_address(ASM_E500_SPE_UNAVAILABLE_VECTOR));
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MTIVOR(33, ppc_exc_vector_address(ASM_E500_EMB_FP_DATA_VECTOR));
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MTIVOR(34, ppc_exc_vector_address(ASM_E500_EMB_FP_ROUND_VECTOR));
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}
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if (ppc_cpu_is_e500()) {
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MTIVOR(35, ppc_exc_vector_address(ASM_E500_PERFMON_VECTOR));
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}
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}
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@@ -123,7 +98,7 @@ rtems_status_code ppc_exc_initialize(
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}
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/* Ensure proper interrupt stack alignment */
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interrupt_stack_pointer &= ~((uint32_t) CPU_STACK_ALIGNMENT - 1);
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interrupt_stack_pointer &= ~((uintptr_t) CPU_STACK_ALIGNMENT - 1);
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/* Tag interrupt stack bottom */
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*(uint32_t *) interrupt_stack_pointer = 0;
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@@ -142,11 +117,8 @@ rtems_status_code ppc_exc_initialize(
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ppc_exc_msr_bits |= MSR_VE;
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#endif
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if (ppc_cpu_is(PPC_e200z1) ||
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ppc_cpu_is(PPC_e200z6)) {
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ppc_exc_initialize_e200();
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} else if (ppc_cpu_is_bookE() == PPC_BOOKE_STD || ppc_cpu_is_bookE() == PPC_BOOKE_E500) {
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ppc_exc_initialize_e500();
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if (ppc_cpu_is_bookE() == PPC_BOOKE_STD || ppc_cpu_is_bookE() == PPC_BOOKE_E500) {
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ppc_exc_initialize_booke();
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}
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for (vector = 0; vector <= LAST_VALID_EXC; ++vector) {
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@@ -39,8 +39,6 @@ extern const uint32_t ppc_exc_tgpr_clr_prolog [];
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*/
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extern const uint32_t ppc_exc_min_prolog_auto [];
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extern const uint32_t ppc_exc_min_prolog_auto_packed [];
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/* Minimal prologue templates */
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extern const uint32_t ppc_exc_min_prolog_async_tmpl_std [];
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extern const uint32_t ppc_exc_min_prolog_sync_tmpl_std [];
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@@ -90,14 +88,10 @@ rtems_status_code ppc_exc_make_prologue(
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prologue_template_size = (size_t) ppc_exc_tgpr_clr_prolog_size;
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} else if (
|
||||
category == PPC_EXC_CLASSIC
|
||||
&& ((vector_address & 0xffU) == 0
|
||||
|| (ppc_cpu_has_ivpr_and_ivor() && (vector_address & 0xfU) == 0))
|
||||
&& ppc_cpu_is_bookE() != PPC_BOOKE_STD
|
||||
&& ppc_cpu_is_bookE() != PPC_BOOKE_E500
|
||||
) {
|
||||
if (ppc_cpu_has_ivpr_and_ivor()) {
|
||||
prologue_template = ppc_exc_min_prolog_auto_packed;
|
||||
} else {
|
||||
prologue_template = ppc_exc_min_prolog_auto;
|
||||
}
|
||||
prologue_template = ppc_exc_min_prolog_auto;
|
||||
prologue_template_size = (size_t) ppc_exc_min_prolog_size;
|
||||
} else {
|
||||
prologue_template = ppc_exc_prologue_templates [category];
|
||||
|
||||
@@ -59,18 +59,6 @@
|
||||
#define ASM_SYS_VECTOR 0x0C
|
||||
#define ASM_TRACE_VECTOR 0x0D
|
||||
|
||||
#define ASM_BOOKE_CRIT_VECTOR 0x01
|
||||
/* We could use the std. decrementer vector # on bookE, too,
|
||||
* but the bookE decrementer has slightly different semantics
|
||||
* so we use a different vector (which happens to be
|
||||
* the PIT vector on the 405 which is like the booke decrementer)
|
||||
*/
|
||||
#define ASM_BOOKE_DEC_VECTOR 0x10
|
||||
#define ASM_BOOKE_ITLBMISS_VECTOR 0x11
|
||||
#define ASM_BOOKE_DTLBMISS_VECTOR 0x12
|
||||
#define ASM_BOOKE_FIT_VECTOR 0x13
|
||||
#define ASM_BOOKE_WDOG_VECTOR 0x14
|
||||
|
||||
#define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR
|
||||
|
||||
#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
|
||||
@@ -103,19 +91,35 @@
|
||||
#define ASM_60X_VEC_ASSIST_VECTOR 0x16
|
||||
#define ASM_60X_ITM_VECTOR 0x17
|
||||
|
||||
/* e200 */
|
||||
#define ASM_E200_SPE_UNAVAILABLE_VECTOR 0x15
|
||||
#define ASM_E200_SPE_DATA_VECTOR 0x16
|
||||
#define ASM_E200_SPE_ROUND_VECTOR 0x17
|
||||
/* Book E */
|
||||
#define ASM_BOOKE_CRIT_VECTOR 0x01
|
||||
/* We could use the std. decrementer vector # on bookE, too,
|
||||
* but the bookE decrementer has slightly different semantics
|
||||
* so we use a different vector (which happens to be
|
||||
* the PIT vector on the 405 which is like the booke decrementer)
|
||||
*/
|
||||
#define ASM_BOOKE_DEC_VECTOR 0x10
|
||||
#define ASM_BOOKE_ITLBMISS_VECTOR 0x11
|
||||
#define ASM_BOOKE_DTLBMISS_VECTOR 0x12
|
||||
#define ASM_BOOKE_FIT_VECTOR 0x13
|
||||
#define ASM_BOOKE_WDOG_VECTOR 0x14
|
||||
#define ASM_BOOKE_APU_VECTOR 0x18
|
||||
#define ASM_BOOKE_DEBUG_VECTOR ASM_TRACE_VECTOR
|
||||
|
||||
/* e200 and e500 */
|
||||
#define ASM_E500_SPE_UNAVAILABLE_VECTOR ASM_60X_VEC_VECTOR
|
||||
#define ASM_E500_EMB_FP_DATA_VECTOR 0x19
|
||||
#define ASM_E500_EMB_FP_ROUND_VECTOR 0x1A
|
||||
#define ASM_E500_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR
|
||||
|
||||
/* e300 */
|
||||
#define ASM_E300_CRIT_VECTOR 0x0A
|
||||
#define ASM_E300_PERFMON_VECTOR 0x0F
|
||||
#define ASM_E300_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR
|
||||
#define ASM_E300_IMISS_VECTOR ASM_60X_IMISS_VECTOR /* Special case: Shadowed GPRs */
|
||||
#define ASM_E300_DLMISS_VECTOR ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */
|
||||
#define ASM_E300_DSMISS_VECTOR ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */
|
||||
#define ASM_E300_ADDR_VECTOR 0x13
|
||||
#define ASM_E300_SYSMGMT_VECTOR 0x14
|
||||
#define ASM_E300_ADDR_VECTOR ASM_60X_ADDR_VECTOR
|
||||
#define ASM_E300_SYSMGMT_VECTOR ASM_60X_SYSMGMT_VECTOR
|
||||
|
||||
/*
|
||||
* If you change that number make sure to adjust the wrapper code in ppc_exc.S
|
||||
|
||||
Reference in New Issue
Block a user