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ARM: Fix _ARMV4_Exception_fiq_default

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In _ARMV4_Exception_fiq_default, set the F bit of the SPSR so that when
it gets loaded back to the CPSR in save_more_context it won't re-enable
the FIQs.

Tested on a TMS570LS3137.
This commit is contained in:
Martin Galvan
2015-02-26 14:39:05 -03:00
committed by Sebastian Huber
parent 6357e14aac
commit 63e91fe689
1 changed files with 8 additions and 0 deletions
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8
cpukit/score/cpu/arm/armv4-exception-default.S
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@@ -99,6 +99,14 @@ _ARMV4_Exception_fiq_default:
stmdb sp!, {r0-r12}
mov r4, #7
/*
* Don't enable FIQs yet. Set the FIQ disable bit in the SPSR
* (which we'll load into the CPSR in save_more_context).
*/
mrs r2, spsr
orr r2, #ARM_PSR_F
msr spsr_c, r2
save_more_context:
/* Save more context */