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Remove stray white spaces.

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This commit is contained in:
Ralf Corsepius
2004-04-21 10:43:04 +00:00
parent 48ea3df90c
commit 6128a4aa5e
575 changed files with 8073 additions and 7970 deletions
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40
c/src/lib/libbsp/sparc/erc32/clock/ckinit.c
View File

@@ -15,10 +15,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -53,11 +53,11 @@ extern uint32_t CPU_SPARC_CLICKS_PER_TICK;
rtems_isr_entry Old_ticker;
void Clock_exit( void );
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
@@ -88,7 +88,7 @@ rtems_isr Clock_isr(
#if SIMSPARC_FAST_IDLE
ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
);
#endif
@@ -135,14 +135,14 @@ void Install_clock(
ERC32_MEC.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_TIMER_COUNTER_LOAD_SCALER |
ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_TIMER_COUNTER_LOAD_SCALER |
ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
);
ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO
ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO
);
atexit( Clock_exit );
@@ -167,12 +167,12 @@ void Clock_exit( void )
ERC32_Mask_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK );
ERC32_MEC_Set_Real_Time_Clock_Timer_Control(
ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING
ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING
);
/* do not restore old vector */
}
/*
* Clock_initialize
*
@@ -196,17 +196,17 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
/*
* Clock_control
*
@@ -231,15 +231,15 @@ rtems_device_driver Clock_control(
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args == 0)
goto done;
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(CLOCK_VECTOR);
@@ -250,7 +250,7 @@ rtems_device_driver Clock_control(
(void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
rtems_interrupt_enable( isrlevel );
}
done:
return RTEMS_SUCCESSFUL;
}

46
c/src/lib/libbsp/sparc/erc32/console/console.c
View File

@@ -20,7 +20,7 @@
/*
* Should we use a polled or interrupt drived console?
*
*
* NOTE: This is defined in the custom/erc32.cfg file.
*
* WARNING: In sis 1.6, it did not appear that the UART interrupts
@@ -28,7 +28,7 @@
* a character into the TX buffer, an interrupt was generated.
* This did not allow enough time for the program to put more
* characters in the buffer. So every character resulted in
* "priming" the transmitter. This effectively results in
* "priming" the transmitter. This effectively results in
* in a polled console with a useless interrupt per character
* on output. It is reasonable to assume that input does not
* share this problem although it was not investigated.
@@ -49,7 +49,7 @@ void console_outbyte_polled(
/* body is in debugputs.c */
/*
* console_inbyte_nonblocking
* console_inbyte_nonblocking
*
* This routine polls for a character.
*/
@@ -69,10 +69,10 @@ int console_inbyte_nonblocking( int port );
*/
#include <rtems/ringbuf.h>
Ring_buffer_t TX_Buffer[ 2 ];
boolean Is_TX_active[ 2 ];
void *console_termios_data[ 2 ];
/*
@@ -81,7 +81,7 @@ void *console_termios_data[ 2 ];
* This routine is the console interrupt handler for Channel A.
*
* Input parameters:
* vector - vector number
* vector - vector number
*
* Output parameters: NONE
*
@@ -91,10 +91,10 @@ void *console_termios_data[ 2 ];
rtems_isr console_isr_a(
rtems_vector_number vector
)
{
{
char ch;
int UStat;
if ( (UStat = ERC32_MEC.UART_Status) & ERC32_MEC_UART_STATUS_DRA ) {
if (UStat & ERC32_MEC_UART_STATUS_ERRA) {
ERC32_MEC.UART_Status = ERC32_MEC_UART_STATUS_CLRA;
@@ -104,7 +104,7 @@ rtems_isr console_isr_a(
rtems_termios_enqueue_raw_characters( console_termios_data[ 0 ], &ch, 1 );
}
if ( ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA ) {
if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) {
Ring_buffer_Remove_character( &TX_Buffer[ 0 ], ch );
@@ -112,7 +112,7 @@ rtems_isr console_isr_a(
} else
Is_TX_active[ 0 ] = FALSE;
}
ERC32_Clear_interrupt( ERC32_INTERRUPT_UART_A_RX_TX );
}
@@ -122,13 +122,13 @@ rtems_isr console_isr_a(
* This routine is the console interrupt handler for Channel B.
*
* Input parameters:
* vector - vector number
* vector - vector number
*
* Output parameters: NONE
*
* Return values: NONE
*/
rtems_isr console_isr_b(
rtems_vector_number vector
)
@@ -194,11 +194,11 @@ void console_exit()
* Now wait for all the data to actually get out ... the send register
* should be empty.
*/
while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA) !=
while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA) !=
ERC32_MEC_UART_STATUS_THEA );
while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB) !=
while ( (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB) !=
ERC32_MEC_UART_STATUS_THEB );
}
@@ -253,7 +253,7 @@ void console_initialize_interrupts( void )
*
* Return values: NONE
*/
void console_outbyte_interrupt(
int port,
char ch
@@ -300,7 +300,7 @@ int console_write_support (int minor, const char *buf, int len)
* Console Device Driver Entry Points
*
*/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -326,7 +326,7 @@ rtems_device_driver console_initialize(
/*
* Initialize Hardware
*/
#if (CONSOLE_USE_INTERRUPTS)
console_initialize_interrupts();
#endif
@@ -369,7 +369,7 @@ rtems_device_driver console_open(
assert( minor <= 1 );
if ( minor > 2 )
return RTEMS_INVALID_NUMBER;
#if (CONSOLE_USE_INTERRUPTS)
sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
@@ -380,7 +380,7 @@ rtems_device_driver console_open(
return RTEMS_SUCCESSFUL;
}
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -389,7 +389,7 @@ rtems_device_driver console_close(
{
return rtems_termios_close (arg);
}
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -398,7 +398,7 @@ rtems_device_driver console_read(
{
return rtems_termios_read (arg);
}
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -407,7 +407,7 @@ rtems_device_driver console_write(
{
return rtems_termios_write (arg);
}
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,

4
c/src/lib/libbsp/sparc/erc32/console/debugputs.c
View File

@@ -40,7 +40,7 @@ void console_outbyte_polled(
}
/*
* console_inbyte_nonblocking
* console_inbyte_nonblocking
*
* This routine polls for a character.
*/
@@ -104,7 +104,7 @@ void DEBUG_puts(
uint32_t old_level;
ERC32_Disable_interrupt( ERC32_INTERRUPT_UART_A_RX_TX, old_level );
for ( s = string ; *s ; s++ )
for ( s = string ; *s ; s++ )
console_outbyte_polled( 0, *s );
console_outbyte_polled( 0, '\r' );

6
c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c
View File

@@ -87,8 +87,8 @@ uint32_t erc32_sonic_read_register(
#define SONIC_VECTOR 0x1E
sonic_configuration_t erc32_sonic_configuration = {
SONIC_BASE_ADDRESS, /* base address */
SONIC_VECTOR, /* vector number */
SONIC_BASE_ADDRESS, /* base address */
SONIC_VECTOR, /* vector number */
SONIC_DCR, /* DCR register value */
SONIC_DC2, /* DC2 register value */
TDA_COUNT, /* number of transmit descriptors */
@@ -105,5 +105,5 @@ int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
ERC32_MEC.Control |= 0x10000; /* Enable DMA */
ERC32_MEC.Interrupt_Mask &= ~(1 << (SONIC_VECTOR - 0x10));
return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration ));
}

30
c/src/lib/libbsp/sparc/erc32/include/bsp.h
View File

@@ -10,10 +10,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -90,9 +90,9 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
#define Cause_tm27_intr() \
asm volatile( "ta 0x10; nop " );
#define Clear_tm27_intr()
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#define Lower_tm27_intr()
/*
* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
@@ -104,13 +104,13 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 ); \
set_vector( (handler), TEST_VECTOR2, 1 );
#define Cause_tm27_intr() \
do { \
ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
@@ -118,10 +118,10 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
nop(); \
nop(); \
} while (0)
#define Clear_tm27_intr() \
ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
#define Lower_tm27_intr()
#endif
@@ -144,28 +144,28 @@ extern void Clock_delay(uint32_t microseconds);
extern int RAM_START;
extern int RAM_END;
extern int RAM_SIZE;
extern int PROM_START;
extern int PROM_END;
extern int PROM_SIZE;
extern int CLOCK_SPEED;
extern int end; /* last address in the program */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/* miscellaneous stuff assumed to exist */
void bsp_cleanup( void );

4
c/src/lib/libbsp/sparc/erc32/include/coverhd.h
View File

@@ -11,10 +11,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$

58
c/src/lib/libbsp/sparc/erc32/include/erc32.h
View File

@@ -5,9 +5,9 @@
* 601/602 chipset. This CPU has a number of on-board peripherals and
* was developed by the European Space Agency to target space applications.
*
* NOTE: Other than where absolutely required, this version currently
* supports only the peripherals and bits used by the basic board
* support package. This includes at least significant pieces of
* NOTE: Other than where absolutely required, this version currently
* supports only the peripherals and bits used by the basic board
* support package. This includes at least significant pieces of
* the following items:
*
* + UART Channels A and B
@@ -26,20 +26,20 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
*/
#ifndef _INCLUDE_ERC32_h
#define _INCLUDE_ERC32_h
#include <rtems/score/sparc.h>
#ifdef __cplusplus
extern "C" {
#endif
@@ -47,7 +47,7 @@ extern "C" {
/*
* Interrupt Sources
*
* The interrupt source numbers directly map to the trap type and to
* The interrupt source numbers directly map to the trap type and to
* the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
* and the Interrupt Pending Registers.
*/
@@ -75,7 +75,7 @@ extern "C" {
*
* Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
*
* NOTE: The priority level for each source corresponds to the least
* NOTE: The priority level for each source corresponds to the least
* significant nibble of the trap type.
*/
@@ -88,12 +88,12 @@ extern "C" {
(_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
/*
* Structure for ERC32 memory mapped registers.
* Structure for ERC32 memory mapped registers.
*
* Source: Section 3.25.2 - Register Address Map
*
* NOTE: There is only one of these structures per CPU, its base address
* is 0x01f80000, and the variable MEC is placed there by the
* NOTE: There is only one of these structures per CPU, its base address
* is 0x01f80000, and the variable MEC is placed there by the
* linkcmds file.
*/
@@ -116,7 +116,7 @@ typedef struct {
volatile uint32_t Interrupt_Force; /* offset 0x54 */
volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */
/* offset 0x60 */
volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge;
volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge;
volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */
volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */
volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */
@@ -249,7 +249,7 @@ typedef struct {
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 )
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 )
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 )
/*
* The following defines the bits in the Timer Control Register.
*/
@@ -277,8 +277,8 @@ typedef struct {
*
*/
#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
/*
* The following defines the bits in the MEC UART Control Registers.
*/
@@ -324,7 +324,7 @@ typedef struct {
*/
extern ERC32_Register_Map ERC32_MEC;
/*
* Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
* and the Interrupt Pending Registers.
@@ -349,13 +349,13 @@ extern ERC32_Register_Map ERC32_MEC;
ERC32_MEC.Interrupt_Force = (1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)
#define ERC32_Is_interrupt_pending( _source ) \
(ERC32_MEC.Interrupt_Pending & (1 << (_source)))
#define ERC32_Is_interrupt_masked( _source ) \
(ERC32_MEC.Interrupt_Masked & (1 << (_source)))
#define ERC32_Mask_interrupt( _source ) \
do { \
uint32_t _level; \
@@ -364,7 +364,7 @@ extern ERC32_Register_Map ERC32_MEC;
ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)
#define ERC32_Unmask_interrupt( _source ) \
do { \
uint32_t _level; \
@@ -385,7 +385,7 @@ extern ERC32_Register_Map ERC32_MEC;
sparc_enable_interrupts( _level ); \
(_previous) &= _mask; \
} while (0)
#define ERC32_Restore_interrupt( _source, _previous ) \
do { \
uint32_t _level; \
@@ -405,9 +405,9 @@ extern ERC32_Register_Map ERC32_MEC;
* and status of the other timer.
*
* This code promotes the view that the two timers are completely independent.
* By exclusively using the routines below to access the Timer Control
* By exclusively using the routines below to access the Timer Control
* Register, the application can view the system as having a General Purpose
* Timer Control Register and a Real Time Clock Timer Control Register
* Timer Control Register and a Real Time Clock Timer Control Register
* rather than the single shared value.
*
* Each logical timer control register is organized as follows:
@@ -451,7 +451,7 @@ extern ERC32_Register_Map ERC32_MEC;
extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
/*
* This macros manipulate the General Purpose Timer portion of the
* This macros manipulate the General Purpose Timer portion of the
* Timer Control register and promote the view that there are actually
* two independent Timer Control Registers.
*/
@@ -480,11 +480,11 @@ extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
} while ( 0 )
/*
* This macros manipulate the Real Timer Clock Timer portion of the
* This macros manipulate the Real Timer Clock Timer portion of the
* Timer Control register and promote the view that there are actually
* two independent Timer Control Registers.
*/
#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
do { \
uint32_t _level; \
@@ -502,7 +502,7 @@ extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
ERC32_MEC.Timer_Control = _control; \
sparc_enable_interrupts( _level ); \
} while ( 0 )
#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
do { \
(_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
@@ -514,6 +514,6 @@ extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
#ifdef __cplusplus
}
#endif
#endif /* !_INCLUDE_ERC32_h */
/* end of include file */

16
c/src/lib/libbsp/sparc/erc32/startup/boardinit.S
View File

@@ -19,11 +19,11 @@ __bsp_board_init:
*/
set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals
ld [%g3], %g2
ld [%g3], %g2
set 0xfe080000, %g1
andcc %g1, %g2, %g0
bne 2f
/* Stop the watchdog */
st %g0, [%g3 + SYM(ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET)]
@@ -33,8 +33,8 @@ __bsp_board_init:
st %g0, [%g3 + SYM(ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET)]
/* Set the correct memory size in MEC memory config register */
set SYM(PROM_SIZE), %l0
set SYM(PROM_SIZE), %l0
set 0, %l1
srl %l0, 18, %l0
1:
@@ -43,8 +43,8 @@ __bsp_board_init:
bne,a 1b
inc %l1
sll %l1, 8, %l1
set SYM(RAM_SIZE), %l0
set SYM(RAM_SIZE), %l0
srl %l0, 19, %l0
1:
tst %l0
@@ -52,10 +52,10 @@ __bsp_board_init:
bne,a 1b
inc %l1
sll %l1, 10, %l1
! set the Memory Configuration
st %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
set SYM(RAM_START), %l1 ! Cannot use RAM_END due to bug in linker
set SYM(RAM_SIZE), %l2
add %l1, %l2, %sp

2
c/src/lib/libbsp/sparc/erc32/startup/erc32mec.c
View File

@@ -13,5 +13,5 @@
#include <rtems.h>
#include <bsp.h>
ERC32_Register_Map ERC32_MEC;

8
c/src/lib/libbsp/sparc/erc32/startup/setvec.c
View File

@@ -21,10 +21,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -44,13 +44,13 @@ rtems_isr_entry set_vector( /* returns old vector */
if ( type )
rtems_interrupt_catch( handler, vector, &previous_isr );
else
else
_CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
real_trap = SPARC_REAL_TRAP_NUMBER( vector );
if ( ERC32_Is_MEC_Trap( real_trap ) ) {
source = ERC32_TRAP_SOURCE( real_trap );
ERC32_Clear_interrupt( source );

26
c/src/lib/libbsp/sparc/erc32/startup/spurious.c
View File

@@ -1,11 +1,11 @@
/*
* ERC32 Spurious Trap Handler
*
* This is just enough of a trap handler to let us know what
* This is just enough of a trap handler to let us know what
* the likely source of the trap was.
*
* Developed as part of the port of RTEMS to the ERC32 implementation
* of the SPARC by On-Line Applications Research Corporation (OAR)
* Developed as part of the port of RTEMS to the ERC32 implementation
* of the SPARC by On-Line Applications Research Corporation (OAR)
* under contract to the European Space Agency (ESA).
*
* COPYRIGHT (c) 1995. European Space Agency.
@@ -60,33 +60,33 @@ rtems_isr bsp_spurious_handler(
* First the ones defined by the basic architecture
*/
case 0x00:
case 0x00:
DEBUG_puts( "reset" );
break;
case 0x01:
case 0x01:
DEBUG_puts( "instruction access exception" );
break;
case 0x02:
case 0x02:
DEBUG_puts( "illegal instruction" );
break;
case 0x03:
case 0x03:
DEBUG_puts( "privileged instruction" );
break;
case 0x04:
case 0x04:
DEBUG_puts( "fp disabled" );
break;
case 0x07:
case 0x07:
DEBUG_puts( "memory address not aligned" );
break;
case 0x08:
case 0x08:
DEBUG_puts( "fp exception" );
break;
case 0x09:
case 0x09:
strcpy(line, "data access exception at 0x " );
itos(ERC32_MEC.First_Failing_Address, &line[27]);
DEBUG_puts( line );
break;
case 0x0A:
case 0x0A:
DEBUG_puts( "tag overflow" );
break;
@@ -178,7 +178,7 @@ void bsp_spurious_initialize()
*/
if (( trap == 5 || trap == 6 ) ||
(( trap >= 0x11 ) && ( trap <= 0x1f )) ||
(( trap >= 0x11 ) && ( trap <= 0x1f )) ||
(( trap >= 0x70 ) && ( trap <= 0x83 )))
continue;

10
c/src/lib/libbsp/sparc/erc32/timer/timer.c
View File

@@ -11,10 +11,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -43,12 +43,12 @@ void Timer_initialize()
Timer_driver_Is_initialized = TRUE;
}
ERC32_MEC_Set_General_Purpose_Timer_Control(
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_Set_General_Purpose_Timer_Control(
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING |
ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER
);
ERC32_MEC_Set_General_Purpose_Timer_Control(
ERC32_MEC_Set_General_Purpose_Timer_Control(
ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING
);

34
c/src/lib/libbsp/sparc/leon/clock/ckinit.c
View File

@@ -14,10 +14,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to LEON implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -52,11 +52,11 @@ extern uint32_t CPU_SPARC_CLICKS_PER_TICK;
rtems_isr_entry Old_ticker;
void Clock_exit( void );
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
@@ -87,7 +87,7 @@ rtems_isr Clock_isr(
#if SIMSPARC_FAST_IDLE
LEON_REG.Real_Time_Clock_Counter = CPU_SPARC_CLICKS_PER_TICK;
LEON_REG_Set_Real_Time_Clock_Timer_Control(
LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
LEON_REG_TIMER_COUNTER_LOAD_COUNTER
);
#endif
@@ -131,11 +131,11 @@ void Install_clock(
LEON_REG.Timer_Reload_1 = CPU_SPARC_CLICKS_PER_TICK - 1;
LEON_REG.Timer_Control_1 = (
LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO |
LEON_REG_TIMER_COUNTER_LOAD_COUNTER
LEON_REG_TIMER_COUNTER_LOAD_COUNTER
);
atexit( Clock_exit );
}
@@ -165,7 +165,7 @@ void Clock_exit( void )
/* do not restore old vector */
}
}
/*
* Clock_initialize
*
@@ -189,17 +189,17 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
/*
* Clock_control
*
@@ -224,15 +224,15 @@ rtems_device_driver Clock_control(
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args == 0)
goto done;
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(CLOCK_VECTOR);
@@ -243,7 +243,7 @@ rtems_device_driver Clock_control(
(void) set_vector( args->buffer, CLOCK_VECTOR, 1 );
rtems_interrupt_enable( isrlevel );
}
done:
return RTEMS_SUCCESSFUL;
}

46
c/src/lib/libbsp/sparc/leon/console/console.c
View File

@@ -20,7 +20,7 @@
/*
* Should we use a polled or interrupt drived console?
*
*
* NOTE: This is defined in the custom/leon.cfg file.
*
* WARNING: In sis 1.6, it did not appear that the UART interrupts
@@ -28,7 +28,7 @@
* a character into the TX buffer, an interrupt was generated.
* This did not allow enough time for the program to put more
* characters in the buffer. So every character resulted in
* "priming" the transmitter. This effectively results in
* "priming" the transmitter. This effectively results in
* in a polled console with a useless interrupt per character
* on output. It is reasonable to assume that input does not
* share this problem although it was not investigated.
@@ -49,7 +49,7 @@ void console_outbyte_polled(
/* body is in debugputs.c */
/*
* console_inbyte_nonblocking
* console_inbyte_nonblocking
*
* This routine polls for a character.
*/
@@ -69,10 +69,10 @@ int console_inbyte_nonblocking( int port );
*/
#include <rtems/ringbuf.h>
Ring_buffer_t TX_Buffer[ 2 ];
boolean Is_TX_active[ 2 ];
void *console_termios_data[ 2 ];
/*
@@ -81,7 +81,7 @@ void *console_termios_data[ 2 ];
* This routine is the console interrupt handler for Channel 1.
*
* Input parameters:
* vector - vector number
* vector - vector number
*
* Output parameters: NONE
*
@@ -91,10 +91,10 @@ void *console_termios_data[ 2 ];
rtems_isr console_isr_a(
rtems_vector_number vector
)
{
{
char ch;
int UStat;
if ( (UStat = LEON_REG.UART_Status_1) & LEON_REG_UART_STATUS_DR ) {
if (UStat & LEON_REG_UART_STATUS_ERR) {
LEON_REG.UART_Status_1 = LEON_REG_UART_STATUS_CLR;
@@ -103,7 +103,7 @@ rtems_isr console_isr_a(
rtems_termios_enqueue_raw_characters( console_termios_data[ 0 ], &ch, 1 );
}
if ( LEON_REG.UART_Status_1 & LEON_REG_UART_STATUS_THE ) {
if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) {
Ring_buffer_Remove_character( &TX_Buffer[ 0 ], ch );
@@ -111,7 +111,7 @@ rtems_isr console_isr_a(
} else
Is_TX_active[ 0 ] = FALSE;
}
LEON_Clear_interrupt( LEON_INTERRUPT_UART_1_RX_TX );
}
@@ -121,13 +121,13 @@ rtems_isr console_isr_a(
* This routine is the console interrupt handler for Channel 2.
*
* Input parameters:
* vector - vector number
* vector - vector number
*
* Output parameters: NONE
*
* Return values: NONE
*/
rtems_isr console_isr_b(
rtems_vector_number vector
)
@@ -192,11 +192,11 @@ void console_exit()
* Now wait for all the data to actually get out ... the send register
* should be empty.
*/
while ( (LEON_REG.UART_Status_1 & LEON_REG_UART_STATUS_THE) !=
while ( (LEON_REG.UART_Status_1 & LEON_REG_UART_STATUS_THE) !=
LEON_REG_UART_STATUS_THE );
while ( (LEON_REG.UART_Status_2 & LEON_REG_UART_STATUS_THE) !=
while ( (LEON_REG.UART_Status_2 & LEON_REG_UART_STATUS_THE) !=
LEON_REG_UART_STATUS_THE );
LEON_REG.UART_Control_1 = 0;
@@ -260,7 +260,7 @@ void console_initialize_interrupts( void )
*
* Return values: NONE
*/
void console_outbyte_interrupt(
int port,
char ch
@@ -307,7 +307,7 @@ int console_write_support (int minor, const char *buf, int len)
* Console Device Driver Entry Points
*
*/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -333,7 +333,7 @@ rtems_device_driver console_initialize(
/*
* Initialize Hardware
*/
LEON_REG.UART_Control_1 |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE;
LEON_REG.UART_Control_2 |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE |
LEON_REG_UART_CTRL_RI; /* rx irq default enable for remote debugger */
@@ -381,7 +381,7 @@ rtems_device_driver console_open(
assert( minor <= 1 );
if ( minor > 2 )
return RTEMS_INVALID_NUMBER;
#if (CONSOLE_USE_INTERRUPTS)
sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
@@ -392,7 +392,7 @@ rtems_device_driver console_open(
return RTEMS_SUCCESSFUL;
}
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -401,7 +401,7 @@ rtems_device_driver console_close(
{
return rtems_termios_close (arg);
}
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -410,7 +410,7 @@ rtems_device_driver console_read(
{
return rtems_termios_read (arg);
}
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
@@ -419,7 +419,7 @@ rtems_device_driver console_write(
{
return rtems_termios_write (arg);
}
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,

4
c/src/lib/libbsp/sparc/leon/console/debugputs.c
View File

@@ -40,7 +40,7 @@ void console_outbyte_polled(
}
/*
* console_inbyte_nonblocking
* console_inbyte_nonblocking
*
* This routine polls for a character.
*/
@@ -100,7 +100,7 @@ void DEBUG_puts(
LEON_Disable_interrupt( LEON_INTERRUPT_UART_1_RX_TX, old_level );
LEON_REG.UART_Control_1 = LEON_REG_UART_CTRL_TE;
for ( s = string ; *s ; s++ )
for ( s = string ; *s ; s++ )
console_outbyte_polled( 0, *s );
console_outbyte_polled( 0, '\r' );

28
c/src/lib/libbsp/sparc/leon/include/bsp.h
View File

@@ -10,10 +10,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -91,9 +91,9 @@ extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *conf
#define Cause_tm27_intr() \
asm volatile( "ta 0x10; nop " );
#define Clear_tm27_intr()
#define Clear_tm27_intr()
#define Lower_tm27_intr()
#define Lower_tm27_intr()
/*
* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
@@ -106,11 +106,11 @@ extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *conf
#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
#define MUST_WAIT_FOR_INTERRUPT 1
#define Install_tm27_vector( handler ) \
set_vector( (handler), TEST_VECTOR, 1 ); \
set_vector( (handler), TEST_VECTOR2, 1 );
#define Cause_tm27_intr() \
do { \
LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
@@ -118,10 +118,10 @@ extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *conf
nop(); \
nop(); \
} while (0)
#define Clear_tm27_intr() \
LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
#define Lower_tm27_intr()
#endif
@@ -144,28 +144,28 @@ extern void Clock_delay(uint32_t microseconds);
extern int RAM_START;
extern int RAM_END;
extern int RAM_SIZE;
extern int PROM_START;
extern int PROM_END;
extern int PROM_SIZE;
extern int CLOCK_SPEED;
extern int end; /* last address in the program */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/* miscellaneous stuff assumed to exist */
void bsp_cleanup( void );

4
c/src/lib/libbsp/sparc/leon/include/coverhd.h
View File

@@ -11,10 +11,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$

50
c/src/lib/libbsp/sparc/leon/include/leon.h
View File

@@ -5,9 +5,9 @@
* This CPU has a number of on-board peripherals and
* was developed by the European Space Agency to target space applications.
*
* NOTE: Other than where absolutely required, this version currently
* supports only the peripherals and bits used by the basic board
* support package. This includes at least significant pieces of
* NOTE: Other than where absolutely required, this version currently
* supports only the peripherals and bits used by the basic board
* support package. This includes at least significant pieces of
* the following items:
*
* + UART Channels A and B
@@ -23,20 +23,20 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to LEON implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
*/
#ifndef _INCLUDE_LEON_h
#define _INCLUDE_LEON_h
#include <rtems/score/sparc.h>
#ifdef __cplusplus
extern "C" {
#endif
@@ -44,7 +44,7 @@ extern "C" {
/*
* Interrupt Sources
*
* The interrupt source numbers directly map to the trap type and to
* The interrupt source numbers directly map to the trap type and to
* the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
* and the Interrupt Pending Registers.
*/
@@ -72,7 +72,7 @@ extern "C" {
*
* Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
*
* NOTE: The priority level for each source corresponds to the least
* NOTE: The priority level for each source corresponds to the least
* significant nibble of the trap type.
*/
@@ -85,12 +85,12 @@ extern "C" {
(_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) )
/*
* Structure for LEON memory mapped registers.
* Structure for LEON memory mapped registers.
*
* Source: Section 6.1 - On-chip registers
*
* NOTE: There is only one of these structures per CPU, its base address
* is 0x80000000, and the variable LEON_REG is placed there by the
* NOTE: There is only one of these structures per CPU, its base address
* is 0x80000000, and the variable LEON_REG is placed there by the
* linkcmds file.
*/
@@ -107,7 +107,7 @@ typedef struct {
volatile unsigned int Leon_Configuration;
volatile unsigned int dummy2;
volatile unsigned int dummy3;
volatile unsigned int dummy4;
volatile unsigned int dummy4;
volatile unsigned int dummy5;
volatile unsigned int dummy6;
volatile unsigned int dummy7;
@@ -213,7 +213,7 @@ typedef struct {
#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00
/*
* The following defines the bits in the Timer Control Register.
*/
@@ -230,8 +230,8 @@ typedef struct {
*
*/
#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
/*
* The following defines the bits in the LEON UART Status Registers.
*/
@@ -245,7 +245,7 @@ typedef struct {
#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
/*
* The following defines the bits in the LEON UART Status Registers.
*/
@@ -269,7 +269,7 @@ typedef struct {
*/
extern LEON_Register_Map LEON_REG;
/*
* Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
* and the Interrupt Pending Registers.
@@ -289,13 +289,13 @@ extern LEON_Register_Map LEON_REG;
do { \
LEON_REG.Interrupt_Force = (1 << (_source)); \
} while (0)
#define LEON_Is_interrupt_pending( _source ) \
(LEON_REG.Interrupt_Pending & (1 << (_source)))
#define LEON_Is_interrupt_masked( _source ) \
(LEON_REG.Interrupt_Masked & (1 << (_source)))
#define LEON_Mask_interrupt( _source ) \
do { \
uint32_t _level; \
@@ -304,7 +304,7 @@ extern LEON_Register_Map LEON_REG;
LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
sparc_enable_interrupts( _level ); \
} while (0)
#define LEON_Unmask_interrupt( _source ) \
do { \
uint32_t _level; \
@@ -325,7 +325,7 @@ extern LEON_Register_Map LEON_REG;
sparc_enable_interrupts( _level ); \
(_previous) &= _mask; \
} while (0)
#define LEON_Restore_interrupt( _source, _previous ) \
do { \
uint32_t _level; \
@@ -349,7 +349,7 @@ extern LEON_Register_Map LEON_REG;
* 0 = stop counter at zero
*
* D2 - Counter Load
* 1 = load counter with preset value
* 1 = load counter with preset value
* 0 = no function
*
*/
@@ -373,6 +373,6 @@ extern LEON_Register_Map LEON_REG;
#ifdef __cplusplus
}
#endif
#endif /* !_INCLUDE_LEON_h */
/* end of include file */

4
c/src/lib/libbsp/sparc/leon/leon_open_eth/leon_open_eth.c
View File

@@ -27,8 +27,8 @@
#define OPEN_ETH_VECTOR 0x1C
open_eth_configuration_t leon_open_eth_configuration = {
OPEN_ETH_BASE_ADDRESS, /* base address */
OPEN_ETH_VECTOR, /* vector number */
OPEN_ETH_BASE_ADDRESS, /* base address */
OPEN_ETH_VECTOR, /* vector number */
TDA_COUNT, /* number of transmit descriptors */
RDA_COUNT /* number of receive descriptors */
};

2
c/src/lib/libbsp/sparc/leon/startup/boardinit.S
View File

@@ -20,7 +20,7 @@ __bsp_board_init:
set SYM(LEON_REG), %l0 ! %l0 = base address of peripherals
ld [%l0+LEON_REG_CACHECTRL_OFFSET], %l1 ! Check if LEON has been initialised
andcc %l1, 3, %g0
andcc %l1, 3, %g0
bne 2f
nop

8
c/src/lib/libbsp/sparc/leon/startup/setvec.c
View File

@@ -21,10 +21,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to LEON implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -44,13 +44,13 @@ rtems_isr_entry set_vector( /* returns old vector */
if ( type )
rtems_interrupt_catch( handler, vector, &previous_isr );
else
else
_CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
real_trap = SPARC_REAL_TRAP_NUMBER( vector );
if ( LEON_INT_TRAP( real_trap ) ) {
source = LEON_TRAP_SOURCE( real_trap );
LEON_Clear_interrupt( source );

26
c/src/lib/libbsp/sparc/leon/startup/spurious.c
View File

@@ -1,11 +1,11 @@
/*
* LEON Spurious Trap Handler
*
* This is just enough of a trap handler to let us know what
* This is just enough of a trap handler to let us know what
* the likely source of the trap was.
*
* Developed as part of the port of RTEMS to the LEON implementation
* of the SPARC by On-Line Applications Research Corporation (OAR)
* Developed as part of the port of RTEMS to the LEON implementation
* of the SPARC by On-Line Applications Research Corporation (OAR)
* under contract to the European Space Agency (ESA).
*
* COPYRIGHT (c) 1995. European Space Agency.
@@ -60,33 +60,33 @@ rtems_isr bsp_spurious_handler(
* First the ones defined by the basic architecture
*/
case 0x00:
case 0x00:
DEBUG_puts( "reset" );
break;
case 0x01:
case 0x01:
DEBUG_puts( "instruction access exception" );
break;
case 0x02:
case 0x02:
DEBUG_puts( "illegal instruction" );
break;
case 0x03:
case 0x03:
DEBUG_puts( "privileged instruction" );
break;
case 0x04:
case 0x04:
DEBUG_puts( "fp disabled" );
break;
case 0x07:
case 0x07:
DEBUG_puts( "memory address not aligned" );
break;
case 0x08:
case 0x08:
DEBUG_puts( "fp exception" );
break;
case 0x09:
case 0x09:
strcpy(line, "data access exception at 0x " );
itos(LEON_REG.Failed_Address, &line[27]);
DEBUG_puts( line );
break;
case 0x0A:
case 0x0A:
DEBUG_puts( "tag overflow" );
break;
@@ -160,7 +160,7 @@ void bsp_spurious_initialize()
*/
if (( trap == 5 || trap == 6 ) ||
(( trap >= 0x11 ) && ( trap <= 0x1f )) ||
(( trap >= 0x11 ) && ( trap <= 0x1f )) ||
(( trap >= 0x70 ) && ( trap <= 0x83 )))
continue;

8
c/src/lib/libbsp/sparc/leon/timer/timer.c
View File

@@ -10,10 +10,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to LEON implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -42,8 +42,8 @@ void Timer_initialize()
Timer_driver_Is_initialized = TRUE;
}
LEON_REG.Timer_Control_2 = (
LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
LEON_REG.Timer_Control_2 = (
LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
LEON_REG_TIMER_COUNTER_LOAD_COUNTER
);

4
c/src/lib/libbsp/sparc/shared/bspclean.c
View File

@@ -10,10 +10,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$

18
c/src/lib/libbsp/sparc/shared/bspstart.c
View File

@@ -12,10 +12,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -29,12 +29,12 @@
#include <bsp.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
@@ -62,8 +62,8 @@ uint32_t CPU_SPARC_CLICKS_PER_TICK;
*
* Try to speed those tests up by speeding up the clock when in the idle task.
*
* NOTE: At the current setting, 5 second delays in the tests take
* approximately 5 seconds of wall time.
* NOTE: At the current setting, 5 second delays in the tests take
* approximately 5 seconds of wall time.
*/
rtems_extension fast_idle_switch_hook(
@@ -98,7 +98,7 @@ rtems_extension fast_idle_switch_hook(
/*
* Use the shared implementations of the following routines
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, uint32_t, int );
extern void bsp_spurious_initialize();
@@ -148,7 +148,7 @@ void bsp_pretasking_hook(void)
rc = rtems_extension_create(
rtems_build_name('F', 'D', 'L', 'E'),
&fast_idle_extension,
&fast_idle_extension,
&extension_id
);
if (rc != RTEMS_SUCCESSFUL)
@@ -195,7 +195,7 @@ void bsp_start( void )
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
work_space_start =
work_space_start =
(unsigned char *)rdb_start - BSP_Configuration.work_space_size;
if ( work_space_start <= (unsigned char *)&end ) {

4
c/src/lib/libbsp/sparc/shared/gnatcommon.c
View File

@@ -56,7 +56,7 @@ rtems_isr __gnat_interrupt_handler
}
/*
* Default signal handler with error reporting
* Default signal handler with error reporting
*/
void
@@ -98,7 +98,7 @@ __gnat_install_handler_common (int t1, int t2)
* Skip window overflow, underflow, and flush as well as software
* trap 0 which we will use as a shutdown. Also avoid trap 0x70 - 0x7f
* which cannot happen and where some of the space is used to pass
* paramaters to the program. 0x80 for system traps and
* paramaters to the program. 0x80 for system traps and
* 0x81 - 0x83 by the remote debugging stub.
* Avoid two bsp specific interrupts which normally are used
* by the real-time clock and UART B.

24
c/src/lib/libbsp/sparc/shared/start.S
View File

@@ -36,10 +36,10 @@
SYM(start):
start:
/*
/*
* The trap table has to be the first code in a boot PROM. But because
* the Memory Configuration comes up thinking we only have 4K of PROM, we
* cannot have a full trap table and still have room left over to
* cannot have a full trap table and still have room left over to
* reprogram the Memory Configuration register correctly. This file
* uses an abbreviated trap which has every entry which might be used
* before RTEMS installs its own trap table.
@@ -49,8 +49,8 @@ start:
PUBLIC(trap_table)
SYM(trap_table):
RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap
BAD_TRAP; ! 01 instruction access
RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap
BAD_TRAP; ! 01 instruction access
! exception
BAD_TRAP; ! 02 illegal instruction
BAD_TRAP; ! 03 privileged instruction
@@ -68,7 +68,7 @@ SYM(trap_table):
BAD_TRAP; ! 0F undefined
BAD_TRAP; ! 10 undefined
/*
/*
* ERC32 defined traps
*/
@@ -115,7 +115,7 @@ SYM(trap_table):
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined
/*
/*
This is a sad patch to make sure that we know where the
MEC timer control register mirror is so we can stop the timers
from an external debugger. It is needed because the control
@@ -138,10 +138,10 @@ SYM(_ERC32_MEC_Timer_Control_Mirror):
SYM(CLOCK_SPEED):
.word 0x0a, 0, 0, 0 ! 7E (10 MHz default)
BAD_TRAP; ! 7F undefined
/*
/*
* Software traps
*
* NOTE: At the risk of being redundant... this is not a full
@@ -207,7 +207,7 @@ SYM(hard_reset):
and %g2, 0x7, %g2
set 1, %g3
sll %g3, %g2, %g3
mov %g3, %wim
mov %g3, %wim
or %g1, 0x20, %g1
wr %g1, %psr ! enable traps
@@ -233,11 +233,11 @@ SYM(hard_reset):
/*
* Copy the initialized data to RAM
*
* FROM: _endtext
* TO: _data_start
* FROM: _endtext
* TO: _data_start
* LENGTH: (__bss_start - _data_start) bytes
*/
sethi %hi(_endtext),%g2
or %g2,%lo(_endtext),%g2 ! g2 = start of initialized data in ROM