make sure cahce is ON when MMU is off (important for exception handling)

c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog

@@ -1,3 +1,8 @@
+2008-09-23	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* startup/cpuinit.c, startup/bspstart.c: initialize mmu, make sure
+	cache is ENABLED when MMU is disabled
+
 2008-09-09	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
 
 	* console/console.c: added printk support

c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c

@@ -53,8 +53,6 @@ bool       bsp_timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
  *  Use the shared implementations of the following routines.
  *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
  */
-extern void cpu_init( void);
-
 void BSP_panic( char *s)
 {
   rtems_interrupt_level level;
@@ -157,9 +155,6 @@ void bsp_start( void)
   myCpu = get_ppc_cpu_type();
   myCpuRevision = get_ppc_cpu_revision();
 
-  /* Basic CPU initialization */
-  cpu_init();
-
   /*
    * Enable instruction and data caches. Do not force writethrough mode.
    */

c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c

@@ -22,6 +22,7 @@
 void _InitTQM8xx (void)
 {
   register uint32_t   r1;
+  uint32_t msr;
 
   /*
    * Initialize the Instruction Support Control Register (ICTRL) to a
@@ -122,12 +123,23 @@ void _InitTQM8xx (void)
   r1 = 0x00000000;
   _mtspr( M8xx_TBU_WR, r1 );
   _mtspr( M8xx_TBL_WR, r1 );
-}
-/*
- * further initialization (called from bsp_start) 
- */
-void cpu_init(void)
-{
-  /* mmu initialization */
+  /* init the MMU */
   mmu_init();
+
+  /* 
+   * override setting from mmu_init:
+   * make sure the cache is ON(!!!) when the MMU is disabled
+   * otherwise the exception code will break
+   */
+  r1 = 0x04000e00;
+  _mtspr( M8xx_MD_CTR, r1 );
+
+  /* Read MSR */
+  msr = ppc_machine_state_register();
+
+  /* Enable data and instruction MMU in MSR */
+  msr |= MSR_DR | MSR_IR;
+
+  /* Update MSR */
+  ppc_set_machine_state_register( msr);
 }