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bsps/powerpc: Delete bsp_exceptions_in_RAM

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Delete ppc_exc_vector_base.  Add and use
ppc_exc_initialize_with_vector_base().
This commit is contained in:
Sebastian Huber
2013-06-20 11:17:23 +02:00
parent 6520aef1e3
commit 5f91272e9b
9 changed files with 93 additions and 88 deletions
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6
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
View File

@@ -105,11 +105,11 @@ void bsp_start(void)
bsp_clicks_per_usec = bsp_clock_speed / 1000000;
/* Initialize exceptions */
ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base;
ppc_exc_initialize(
ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
rtems_configuration_get_interrupt_stack_size(),
mpc55xx_exc_vector_base
);
#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);

10
c/src/lib/libbsp/powerpc/psim/startup/bspstart.c
View File

@@ -93,18 +93,14 @@ void bsp_start( void )
bsp_clicks_per_usec = BSP_bus_frequency;
BSP_time_base_divisor = 1;
/*
* The simulator likes the exception table to be at 0xfff00000.
*/
bsp_exceptions_in_RAM = FALSE;
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(
ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
rtems_configuration_get_interrupt_stack_size(),
(void *) 0xfff00000
);
/*

6
c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c
View File

@@ -107,11 +107,11 @@ void bsp_start(void)
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);
/* Initialize exception handler */
ppc_exc_vector_base = (uint32_t) bsp_exc_vector_base;
ppc_exc_initialize(
ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base
);
/* Now it is possible to make the code execute only */

6
c/src/lib/libbsp/powerpc/qoriq/startup/smp.c
View File

@@ -117,11 +117,11 @@ void qoriq_secondary_cpu_initialize(void)
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);
/* Initialize exception handler */
ppc_exc_vector_base = (uint32_t) bsp_exc_vector_base;
ppc_exc_initialize(
ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) _Per_CPU_Information[1].interrupt_stack_low,
rtems_configuration_get_interrupt_stack_size()
rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base
);
/* Now it is possible to make the code execute only */

6
c/src/lib/libbsp/powerpc/t32mppc/startup/bspstart.c
View File

@@ -64,11 +64,11 @@ void bsp_start(void)
get_ppc_cpu_revision();
/* Initialize exception handler */
ppc_exc_vector_base = (uint32_t) bsp_exc_vector_base;
ppc_exc_initialize(
ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base
);
/* Initalize interrupt support */

13
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c
View File

@@ -30,10 +30,6 @@
#include <bsp/vectors.h>
bool bsp_exceptions_in_RAM = true;
uint32_t ppc_exc_vector_base = 0;
/*
* XXX: These values are choosen to directly generate the vector offsets for an
* e200z1 which has hard wired IVORs (IVOR0=0x00, IVOR1=0x10, IVOR2=0x20, ...).
@@ -61,9 +57,8 @@ static const uint8_t ivor_values [] = {
[ASM_E500_PERFMON_VECTOR] = 19
};
void *ppc_exc_vector_address(unsigned vector)
void *ppc_exc_vector_address(unsigned vector, void *vector_base)
{
uintptr_t vector_base = 0xfff00000;
uintptr_t vector_offset = vector << 8;
if (ppc_cpu_has_altivec()) {
@@ -101,9 +96,5 @@ void *ppc_exc_vector_address(unsigned vector)
}
}
if (bsp_exceptions_in_RAM) {
vector_base = ppc_exc_vector_base;
}
return (void *) (vector_base + vector_offset);
return (void *) ((uintptr_t) vector_base + vector_offset);
}

61
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
View File

@@ -100,10 +100,10 @@ uint32_t ppc_exc_cache_wb_check = 1;
#define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
#define MTIVOR(x, vec) __asm__ volatile ("mtivor"#x" %0" : : "r" (vec))
static void ppc_exc_initialize_booke(void)
static void ppc_exc_initialize_booke(void *vector_base)
{
/* Interupt vector prefix register */
MTIVPR(ppc_exc_vector_base);
MTIVPR((uint32_t) vector_base);
if (
ppc_cpu_is_specific_e200(PPC_e200z0)
@@ -117,29 +117,29 @@ static void ppc_exc_initialize_booke(void)
}
/* Interupt vector offset registers */
MTIVOR(0, ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR));
MTIVOR(1, ppc_exc_vector_address(ASM_MACH_VECTOR));
MTIVOR(2, ppc_exc_vector_address(ASM_PROT_VECTOR));
MTIVOR(3, ppc_exc_vector_address(ASM_ISI_VECTOR));
MTIVOR(4, ppc_exc_vector_address(ASM_EXT_VECTOR));
MTIVOR(5, ppc_exc_vector_address(ASM_ALIGN_VECTOR));
MTIVOR(6, ppc_exc_vector_address(ASM_PROG_VECTOR));
MTIVOR(7, ppc_exc_vector_address(ASM_FLOAT_VECTOR));
MTIVOR(8, ppc_exc_vector_address(ASM_SYS_VECTOR));
MTIVOR(9, ppc_exc_vector_address(ASM_BOOKE_APU_VECTOR));
MTIVOR(10, ppc_exc_vector_address(ASM_BOOKE_DEC_VECTOR));
MTIVOR(11, ppc_exc_vector_address(ASM_BOOKE_FIT_VECTOR));
MTIVOR(12, ppc_exc_vector_address(ASM_BOOKE_WDOG_VECTOR));
MTIVOR(13, ppc_exc_vector_address(ASM_BOOKE_DTLBMISS_VECTOR));
MTIVOR(14, ppc_exc_vector_address(ASM_BOOKE_ITLBMISS_VECTOR));
MTIVOR(15, ppc_exc_vector_address(ASM_BOOKE_DEBUG_VECTOR));
MTIVOR(0, ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR, vector_base));
MTIVOR(1, ppc_exc_vector_address(ASM_MACH_VECTOR, vector_base));
MTIVOR(2, ppc_exc_vector_address(ASM_PROT_VECTOR, vector_base));
MTIVOR(3, ppc_exc_vector_address(ASM_ISI_VECTOR, vector_base));
MTIVOR(4, ppc_exc_vector_address(ASM_EXT_VECTOR, vector_base));
MTIVOR(5, ppc_exc_vector_address(ASM_ALIGN_VECTOR, vector_base));
MTIVOR(6, ppc_exc_vector_address(ASM_PROG_VECTOR, vector_base));
MTIVOR(7, ppc_exc_vector_address(ASM_FLOAT_VECTOR, vector_base));
MTIVOR(8, ppc_exc_vector_address(ASM_SYS_VECTOR, vector_base));
MTIVOR(9, ppc_exc_vector_address(ASM_BOOKE_APU_VECTOR, vector_base));
MTIVOR(10, ppc_exc_vector_address(ASM_BOOKE_DEC_VECTOR, vector_base));
MTIVOR(11, ppc_exc_vector_address(ASM_BOOKE_FIT_VECTOR, vector_base));
MTIVOR(12, ppc_exc_vector_address(ASM_BOOKE_WDOG_VECTOR, vector_base));
MTIVOR(13, ppc_exc_vector_address(ASM_BOOKE_DTLBMISS_VECTOR, vector_base));
MTIVOR(14, ppc_exc_vector_address(ASM_BOOKE_ITLBMISS_VECTOR, vector_base));
MTIVOR(15, ppc_exc_vector_address(ASM_BOOKE_DEBUG_VECTOR, vector_base));
if (ppc_cpu_is_e200() || ppc_cpu_is_e500()) {
MTIVOR(32, ppc_exc_vector_address(ASM_E500_SPE_UNAVAILABLE_VECTOR));
MTIVOR(33, ppc_exc_vector_address(ASM_E500_EMB_FP_DATA_VECTOR));
MTIVOR(34, ppc_exc_vector_address(ASM_E500_EMB_FP_ROUND_VECTOR));
MTIVOR(32, ppc_exc_vector_address(ASM_E500_SPE_UNAVAILABLE_VECTOR, vector_base));
MTIVOR(33, ppc_exc_vector_address(ASM_E500_EMB_FP_DATA_VECTOR, vector_base));
MTIVOR(34, ppc_exc_vector_address(ASM_E500_EMB_FP_ROUND_VECTOR, vector_base));
}
if (ppc_cpu_is_specific_e200(PPC_e200z7) || ppc_cpu_is_e500()) {
MTIVOR(35, ppc_exc_vector_address(ASM_E500_PERFMON_VECTOR));
MTIVOR(35, ppc_exc_vector_address(ASM_E500_PERFMON_VECTOR, vector_base));
}
}
@@ -151,10 +151,11 @@ static void ppc_exc_fatal_error(void)
);
}
void ppc_exc_initialize(
void ppc_exc_initialize_with_vector_base(
uint32_t interrupt_disable_mask,
uintptr_t interrupt_stack_begin,
uintptr_t interrupt_stack_size
uintptr_t interrupt_stack_size,
void *vector_base
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
@@ -208,18 +209,24 @@ void ppc_exc_initialize(
#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */
if (ppc_cpu_is_bookE() == PPC_BOOKE_STD || ppc_cpu_is_bookE() == PPC_BOOKE_E500) {
ppc_exc_initialize_booke();
ppc_exc_initialize_booke(vector_base);
}
for (vector = 0; vector <= LAST_VALID_EXC; ++vector) {
ppc_exc_category category = ppc_exc_category_for_vector(categories, vector);
if (category != PPC_EXC_INVALID) {
void *const vector_address = ppc_exc_vector_address(vector);
void *const vector_address = ppc_exc_vector_address(vector, vector_base);
uint32_t prologue [16];
size_t prologue_size = sizeof(prologue);
sc = ppc_exc_make_prologue(vector, category, prologue, &prologue_size);
sc = ppc_exc_make_prologue(
vector,
vector_base,
category,
prologue,
&prologue_size
);
if (sc != RTEMS_SUCCESSFUL) {
ppc_exc_fatal_error();
}

14
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c
View File

@@ -63,6 +63,7 @@ static const uint32_t *const ppc_exc_prologue_templates [] = {
static bool ppc_exc_create_branch_op(
unsigned vector,
void *vector_base,
uint32_t *prologue,
size_t prologue_size
)
@@ -72,7 +73,8 @@ static bool ppc_exc_create_branch_op(
static const uintptr_t BRANCH_OP_ABS = 0x2;
static const uintptr_t BRANCH_OP_MSK = 0x3ffffff;
size_t branch_op_index = prologue_size / 4 - 1;
uintptr_t vector_address = (uintptr_t) ppc_exc_vector_address(vector);
uintptr_t vector_address =
(uintptr_t) ppc_exc_vector_address(vector, vector_base);
uintptr_t branch_op_address = vector_address + 4 * branch_op_index;
/* This value may have BRANCH_OP_LINK set */
@@ -101,6 +103,7 @@ static bool ppc_exc_create_branch_op(
rtems_status_code ppc_exc_make_prologue(
unsigned vector,
void *vector_base,
ppc_exc_category category,
uint32_t *prologue,
size_t *prologue_size
@@ -152,7 +155,14 @@ rtems_status_code ppc_exc_make_prologue(
memcpy(prologue, prologue_template, prologue_template_size);
if (!ppc_exc_create_branch_op(vector, prologue, prologue_template_size)) {
if (
!ppc_exc_create_branch_op(
vector,
vector_base,
prologue,
prologue_template_size
)
) {
return RTEMS_INVALID_ADDRESS;
}

55
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
View File

@@ -303,32 +303,12 @@ static inline bool ppc_exc_is_valid_category(ppc_exc_category category)
}
/**
* @brief Indicates if exception entry table resides in a writable memory.
* @brief Returns the entry address of the vector.
*
* This variable is initialized to 'TRUE' by default;
* BSPs which have their vectors in ROM should set it
* to FALSE prior to initializing raw exceptions.
*
* I suspect the only candidate is the simulator.
* After all, the value of this variable is used to
* determine where to install the prologue code and
* installing to ROM on anyting that's real ROM
* will fail anyways.
*
* This should probably go away... (T.S. 2007/11/30)
* @param[in] vector The vector number.
* @param[in] vector_base The vector table base address.
*/
extern bool bsp_exceptions_in_RAM;
/**
* @brief Vector base address for CPUs (for example e200 and e500) with IVPR
* and IVOR registers.
*/
extern uint32_t ppc_exc_vector_base;
/**
* @brief Returns the entry address of the vector @a vector.
*/
void *ppc_exc_vector_address(unsigned vector);
void *ppc_exc_vector_address(unsigned vector, void *vector_base);
/**
* @brief Returns the category set for a CPU of type @a cpu, or @c NULL if
@@ -358,8 +338,8 @@ ppc_exc_category ppc_exc_category_for_vector(
* @brief Makes a minimal prologue for the vector @a vector with the category
* @a category.
*
* The minimal prologue will be copied to @a prologue. Not more than @a
* prologue_size bytes will be copied. Returns the actual minimal prologue
* The minimal prologue will be copied to @a prologue. Not more than
* @a prologue_size bytes will be copied. Returns the actual minimal prologue
* size in bytes in @a prologue_size.
*
* @retval RTEMS_SUCCESSFUL Minimal prologue successfully made.
@@ -369,11 +349,24 @@ ppc_exc_category ppc_exc_category_for_vector(
*/
rtems_status_code ppc_exc_make_prologue(
unsigned vector,
void *vector_base,
ppc_exc_category category,
uint32_t *prologue,
size_t *prologue_size
);
/**
* @brief Initializes the exception handling.
*
* @see ppc_exc_initialize().
*/
void ppc_exc_initialize_with_vector_base(
uint32_t interrupt_disable_mask,
uintptr_t interrupt_stack_begin,
uintptr_t interrupt_stack_size,
void *vector_base
);
/**
* @brief Initializes the exception handling.
*
@@ -387,11 +380,19 @@ rtems_status_code ppc_exc_make_prologue(
* SVR4/EABI, or
* - the minimal prologue creation failed.
*/
void ppc_exc_initialize(
static inline void ppc_exc_initialize(
uint32_t interrupt_disable_mask,
uintptr_t interrupt_stack_begin,
uintptr_t interrupt_stack_size
)
{
ppc_exc_initialize_with_vector_base(
interrupt_disable_mask,
interrupt_stack_begin,
interrupt_stack_size,
NULL
);
}
/**
* @brief High-level exception handler type.