RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2001-11-27 Joel Sherrill <joel@OARcorp.com>,

Browse Source 
This was tracked as PR39.
	* include/bsp.h, start/cpuboot.c, start/reset.S, startup/debugger,
	startup/linkcmds, startup/rom: Eliminated required definition of
	macros in the custom file for the BSP to compile.  The ROM and ROM
	address and size settings are now linker script items.
This commit is contained in:
Joel Sherrill
2001-11-27 23:38:03 +00:00
parent dda8f5dc30
commit 5e2dce08b0
9 changed files with 67 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
c/src/lib/libbsp/m68k/ods68302/ChangeLog
View File

@@ -1,3 +1,11 @@
2001-11-27 Joel Sherrill <joel@OARcorp.com>,
This was tracked as PR39.
* include/bsp.h, start/cpuboot.c, start/reset.S, startup/debugger,
startup/linkcmds, startup/rom: Eliminated required definition of
macros in the custom file for the BSP to compile. The ROM and ROM
address and size settings are now linker script items.
2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Add autom4te.cache for autoconf > 2.52.

3
c/src/lib/libbsp/m68k/ods68302/include/bsp.h
View File

@@ -38,6 +38,9 @@ extern "C" {
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
#ifndef VARIANT
#define VARIANT bare
#endif
#if defined(VARIANT)
#define __bsp_cat(x, y) x ## y

16
c/src/lib/libbsp/m68k/ods68302/start/cpuboot.c
View File

@@ -41,14 +41,22 @@
Open the address, reset all registers
*/
extern int ROM_SIZE, ROM_BASE;
extern int RAM_SIZE, RAM_BASE;
#define _ROM_SIZE ((unsigned int)&ROM_SIZE)
#define _ROM_BASE ((unsigned int)&ROM_BASE)
#define _RAM_SIZE ((unsigned int)&RAM_SIZE)
#define _RAM_BASE ((unsigned int)&RAM_BASE)
void boot_phase_1()
{
M302_SCR = SCR_DEFAULT;
WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_ROM, _ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_ROM, _RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_RAM, _RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_RAM, _ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#if defined(CSEL_1)
WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);

9
c/src/lib/libbsp/m68k/ods68302/start/reset.S
View File

@@ -357,7 +357,14 @@ start:
|
moveq #0,%d0
move.w #(MC68302_BASE >> 12),%d0
| Joel: With the change of MC68302_BASE from a #define to a linker
| symbol, the following 4 instructions replace this one:
| move.w #(MC68302_BASE >> 12),%d0
move.l #MC68302_BASE,%d0
moveq.l #12,%d1
lsr.l %d1,%d0
and.l #0xFFFF,%d0
or.w #(MC68302_BAR_FC_CFC << 12),%d0
move.l #MC68302_BAR,%a0
move.w %d0,%a0@(0)

16
c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
View File

@@ -41,14 +41,22 @@
Open the address, reset all registers
*/
extern int ROM_SIZE, ROM_BASE;
extern int RAM_SIZE, RAM_BASE;
#define _ROM_SIZE ((unsigned int)&ROM_SIZE)
#define _ROM_BASE ((unsigned int)&ROM_BASE)
#define _RAM_SIZE ((unsigned int)&RAM_SIZE)
#define _RAM_BASE ((unsigned int)&RAM_BASE)
void boot_phase_1()
{
M302_SCR = SCR_DEFAULT;
WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_ROM, _ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_ROM, _RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_RAM, _RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_RAM, _ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#if defined(CSEL_1)
WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);

6
c/src/lib/libbsp/m68k/ods68302/startup/debugger
View File

@@ -48,6 +48,12 @@ SECTIONS
}
}
RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00010000;
ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
m302 = MC68302_BASE;
_VBR = 0; /* location of the VBR table (in RAM) */

5
c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
View File

@@ -170,6 +170,11 @@ SECTIONS
/* These must appear regardless of . */
}
RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00C00000;
ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
m302 = MC68302_BASE;
_VBR = ADDR(.vtable); /* location of the VBR table (in RAM) */

5
c/src/lib/libbsp/m68k/ods68302/startup/rom
View File

@@ -50,6 +50,11 @@ SECTIONS
}
}
RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00C00000;
ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
m302 = MC68302_BASE;
_VBR = 0; /* location of the VBR table (in RAM) */