RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

arm: Fix CPU context validation for Cortex-R4

Browse Source 
Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.

Close #3092.
This commit is contained in:
Sebastian Huber
2017-03-09 14:32:04 +01:00
parent 7e91901303
commit 5cc276e7c1
2 changed files with 4 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
cpukit/score/cpu/arm/arm-context-validate.S
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -99,12 +99,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate)
#ifdef ARM_MULTILIB_VFP
/* R3 contains the FPSCR */
vmrs r3, FPSCR
movs r4, #0x001f
#ifdef ARM_MULTILIB_ARCH_V7M
movt r4, #0xf000
#else
movt r4, #0xf800
#endif
ldr r4, =0xf000001f
bic r3, r3, r4
and r4, r4, r0
orr r3, r3, r4

5
cpukit/score/cpu/arm/arm-context-volatile-clobber.S
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -29,8 +29,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber)
#ifdef ARM_MULTILIB_VFP
vmrs r1, FPSCR
movs r2, #0x001f
movt r2, #0xf800
ldr r2, =0xf000001f
bic r1, r1, r2
and r2, r2, r0
orr r1, r1, r2