forked from Imagelibrary/rtems
arm: Fix CPU context validation for Cortex-R4
Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4. Close #3092.
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
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* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
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*
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*
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* embedded brains GmbH
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* embedded brains GmbH
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* Dornierstr. 4
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* Dornierstr. 4
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@@ -99,12 +99,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate)
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#ifdef ARM_MULTILIB_VFP
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#ifdef ARM_MULTILIB_VFP
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/* R3 contains the FPSCR */
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/* R3 contains the FPSCR */
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vmrs r3, FPSCR
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vmrs r3, FPSCR
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movs r4, #0x001f
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ldr r4, =0xf000001f
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#ifdef ARM_MULTILIB_ARCH_V7M
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movt r4, #0xf000
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#else
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movt r4, #0xf800
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#endif
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bic r3, r3, r4
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bic r3, r3, r4
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and r4, r4, r0
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and r4, r4, r0
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orr r3, r3, r4
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orr r3, r3, r4
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
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* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
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*
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*
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* embedded brains GmbH
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* embedded brains GmbH
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* Dornierstr. 4
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* Dornierstr. 4
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@@ -29,8 +29,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber)
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#ifdef ARM_MULTILIB_VFP
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#ifdef ARM_MULTILIB_VFP
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vmrs r1, FPSCR
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vmrs r1, FPSCR
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movs r2, #0x001f
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ldr r2, =0xf000001f
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movt r2, #0xf800
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bic r1, r1, r2
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bic r1, r1, r2
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and r2, r2, r0
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and r2, r2, r0
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orr r1, r1, r2
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orr r1, r1, r2
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