irq/arm-gicv3.h: Customize CPU Interface init

Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers.  This fixes the build for the AArch32 target.

Add BSP options which define the initial values of CPU Interface registers.

spec/build/bsps/dev/irq/objarmgicv3.yml

@@ -0,0 +1,31 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: objects
+cflags: []
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+cxxflags: []
+enabled-by: true
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}/dev/irq
+  source:
+  - bsps/include/dev/irq/arm-gicv3.h
+links:
+- role: build-dependency
+  uid: optarmgic-icc-bpr0
+- role: build-dependency
+  uid: optarmgic-icc-bpr1
+- role: build-dependency
+  uid: optarmgic-icc-ctrl
+- role: build-dependency
+  uid: optarmgic-icc-igrpen0
+- role: build-dependency
+  uid: optarmgic-icc-igrpen1
+- role: build-dependency
+  uid: optarmgic-icc-pmr
+- role: build-dependency
+  uid: optarmgic-icc-sre
+source:
+- bsps/shared/dev/irq/arm-gicv3.c
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml

@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 2
+default-by-variant:
+- value: null
+  variants:
+  - aarch64/.*
+description: |
+  Defines the initial value of the ICC_BPR0 register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_BPR0
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 3
+default-by-variant: []
+description: |
+  Defines the initial value of the ICC_BPR1 register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_BPR1
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 0
+default-by-variant: []
+description: |
+  Defines the initial value of the ICC_CTRL register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_CTRL
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml

@@ -0,0 +1,21 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 1
+default-by-variant:
+- value: null
+  variants:
+  - aarch64/.*
+description: |
+  Defines the initial value of the ICC_IGRPEN0 register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_IGRPEN0
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 1
+default-by-variant: []
+description: |
+  Defines the initial value of the ICC_IGRPEN1 register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_IGRPEN1
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 255
+default-by-variant: []
+description: |
+  Defines the initial value of the ICC_PMR register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_PMR
+type: build

spec/build/bsps/dev/irq/optarmgic-icc-sre.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+default: 3
+default-by-variant: []
+description: |
+  Defines the initial value of the ICC_SRE register of the ARM GIC CPU
+  Interface.  The value is optional.  If it is not defined, then the register
+  is not initialized.
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_ARM_GIC_ICC_SRE
+type: build