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Much renamed, most stuff automatically generated now.

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This commit is contained in:
Joel Sherrill
1998-10-19 18:59:35 +00:00
parent 16a1fd9c33
commit 5ab187b256
11 changed files with 26 additions and 352 deletions
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47
doc/supplements/i960/Makefile
View File

@@ -20,16 +20,12 @@ dirs:
COMMON_FILES=../../common/cpright.texi ../../common/setup.texi
#GENERATED_FILES=\
# cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \
# bsp.texi cputable.texi timing.texi wksheets.texi timeFORCE386.texi
GENERATED_FILES= \
timing.texi wksheets.texi
GENERATED_FILES=\
cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \
bsp.texi cputable.texi timing.texi wksheets.texi timeCVME961.texi
FILES= $(PROJECT).texi \
bsp.texi callconv.texi cpumodel.texi cputable.texi fatalerr.texi \
intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \
preface.texi \
$(GENERATED_FILES)
info: dirs c_i960
@@ -48,8 +44,6 @@ $(PROJECT).ps: $(PROJECT).dvi
$(PROJECT).dvi: $(FILES)
$(TEXI2DVI) $(PROJECT).texi
replace: timedata.texi
#
# Chapters which get automatic processing
#
@@ -65,7 +59,7 @@ callconv.texi: callconv.t Makefile
-n "Memory Model" ${*}.t
memmodel.texi: memmodel.t Makefile
$(BMENU) -p "Calling Conventions User-Provided Routines" \
$(BMENU) -p "Calling Conventions Leaf Procedures" \
-u "Top" \
-n "Interrupt Processing" ${*}.t
@@ -126,19 +120,25 @@ timing.texi: timing.t Makefile
-u "Top" \
-n "CVME961 Timing Data" ${*}.t
# Timing Chapter
# Timing Data for BSP Chapter:
# 1. Copy the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
timetbl.t: ../../common/timetbl.t
sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \
<../../common/timetbl.t >timetbl.t
timeCVME961_.t: ../../common/timetbl.t timeCVME961.t
cat timeCVME961.t ../../common/timetbl.t >timeCVME961_.t
@echo >>timeCVME961_.t
@echo "@tex" >>timeCVME961_.t
@echo "\\global\\advance \\smallskipamount by 4pt" >>timeCVME961_.t
@echo "@end tex" >>timeCVME961_.t
${REPLACE} -p CVME961_TIMES timeCVME961_.t
mv timeCVME961_.t.fixed timeCVME961_.t
timetbl.texi: timetbl.t CVME961_TIMES
${REPLACE} -p CVME961_TIMES timetbl.t
mv timetbl.t.fixed timetbl.texi
timedata.texi: timedata.t CVME961_TIMES
${REPLACE} -p CVME961_TIMES timedata.t
mv timedata.t.fixed timedata.texi
timeCVME961.texi: timeCVME961_.t Makefile
$(BMENU) -p "Timing Specification Terminology" \
-u "Top" \
-n "Command and Variable Index" timeCVME961_.t
mv timeCVME961_.texi timeCVME961.texi
html: dirs $(FILES)
-mkdir -p $(WWW_INSTALL)/c_i960
@@ -150,7 +150,8 @@ clean:
rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE)
rm -f $(PROJECT) $(PROJECT)-*
rm -f c_i960 c_i960-*
rm -f timedata.texi timetbl.texi timetbl.t intr.t $(GENERATED_FILES)
rm -f intr.t $(GENERATED_FILES)
rm -f wksheets.t wksheets_NOTIMES.t
rm -f *.fixed _* timing.t timing.texi
rm -f timeCVME961_.t timeCVME961_.texi

19
doc/supplements/i960/bsp.t
View File

@@ -6,21 +6,8 @@
@c $Id$
@c
@ifinfo
@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top
@end ifinfo
@chapter Board Support Packages
@ifinfo
@menu
* Board Support Packages Introduction::
* Board Support Packages System Reset::
* Board Support Packages Processor Initialization::
@end menu
@end ifinfo
@ifinfo
@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages
@end ifinfo
@section Introduction
An RTEMS Board Support Package (BSP) must be designed
@@ -30,9 +17,6 @@ issues. For more information on developing a BSP, refer to the
chapter titled Board Support Packages in the RTEMS
Applications User's Guide.
@ifinfo
@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages
@end ifinfo
@section System Reset
An RTEMS based application is initiated when the
@@ -45,9 +29,6 @@ initial bus configuration data, the address of the first
instruction to execute after reset, the address of the PRCB, and
the checksum used by the processor's self-test.
@ifinfo
@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
@end ifinfo
@section Processor Initialization
The PRCB contains the base addresses for system data

35
doc/supplements/i960/callconv.t
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@@ -6,25 +6,8 @@
@c $Id$
@c
@ifinfo
@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Floating Point Unit, Top
@end ifinfo
@chapter Calling Conventions
@ifinfo
@menu
* Calling Conventions Introduction::
* Calling Conventions Processor Background::
* Calling Conventions Calling Mechanism::
* Calling Conventions Register Usage::
* Calling Conventions Parameter Passing::
* Calling Conventions User-Provided Routines::
* Calling Conventions Leaf Procedures::
@end menu
@end ifinfo
@ifinfo
@node Calling Conventions Introduction, Calling Conventions Processor Background, Calling Conventions, Calling Conventions
@end ifinfo
@section Introduction
Each high-level language compiler generates
@@ -47,9 +30,6 @@ target processor are the same, different compilers may use
different calling conventions. As a result, calling conventions
are both processor and compiler dependent.
@ifinfo
@node Calling Conventions Processor Background, Calling Conventions Calling Mechanism, Calling Conventions Introduction, Calling Conventions
@end ifinfo
@section Processor Background
All members of the i960 architecture family support
@@ -80,18 +60,12 @@ retain the last five to sixteen recent register caches. When
the register cache is full, the oldest cached register set is
written to the stack.
@ifinfo
@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Processor Background, Calling Conventions
@end ifinfo
@section Calling Mechanism
All RTEMS directives are invoked using either a call
or callx instruction and return to the user via the ret
instruction.
@ifinfo
@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions
@end ifinfo
@section Register Usage
As discussed above, the call and callx instructions
@@ -101,9 +75,6 @@ be restored as part of returning to the application. The
contents of global registers G0 through G7 are not preserved by
RTEMS directives.
@ifinfo
@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions
@end ifinfo
@section Parameter Passing
RTEMS uses the standard i960 family C parameter
@@ -111,18 +82,12 @@ passing mechanism in which G0 contains the first parameter, G1
the second, and so on for the remaining parameters. No RTEMS
directive requires more than six parameters.
@ifinfo
@node Calling Conventions User-Provided Routines, Calling Conventions Leaf Procedures, Calling Conventions Parameter Passing, Calling Conventions
@end ifinfo
@section User-Provided Routines
All user-provided routines invoked by RTEMS, such as
user extensions, device drivers, and MPCI routines, must also
adhere to these calling conventions.
@ifinfo
@node Calling Conventions Leaf Procedures, Memory Model, Calling Conventions User-Provided Routines, Calling Conventions
@end ifinfo
@section Leaf Procedures
RTEMS utilizes leaf procedures internally to improve

19
doc/supplements/i960/cpumodel.t
View File

@@ -6,21 +6,8 @@
@c $Id$
@c
@ifinfo
@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
@end ifinfo
@chapter CPU Model Dependent Features
@ifinfo
@menu
* CPU Model Dependent Features Introduction::
* CPU Model Dependent Features CPU Model Name::
* CPU Model Dependent Features Floating Point Unit::
@end menu
@end ifinfo
@ifinfo
@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features, CPU Model Dependent Features
@end ifinfo
@section Introduction
Microprocessors are generally classified into
@@ -62,18 +49,12 @@ The set of CPU model feature macros are defined in the file
c/src/exec/score/cpu/i960/i960.h based upon the particular CPU
model defined on the compilation command line.
@ifinfo
@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Introduction, CPU Model Dependent Features
@end ifinfo
@section CPU Model Name
The macro CPU_MODEL_NAME is a string which designates
the name of this CPU model. For example, for the Intel i960CA,
this macro is set to the string "i960ca".
@ifinfo
@node CPU Model Dependent Features Floating Point Unit, Calling Conventions, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features
@end ifinfo
@section Floating Point Unit
The macro I960_HAS_FPU is set to 1 to indicate that

15
doc/supplements/i960/cputable.t
View File

@@ -6,20 +6,8 @@
@c $Id$
@c
@ifinfo
@node Processor Dependent Information Table, Processor Dependent Information Table Introduction, Board Support Packages Processor Initialization, Top
@end ifinfo
@chapter Processor Dependent Information Table
@ifinfo
@menu
* Processor Dependent Information Table Introduction::
* Processor Dependent Information Table CPU Dependent Information Table::
@end menu
@end ifinfo
@ifinfo
@node Processor Dependent Information Table Introduction, Processor Dependent Information Table CPU Dependent Information Table, Processor Dependent Information Table, Processor Dependent Information Table
@end ifinfo
@section Introduction
Any highly processor dependent information required
@@ -28,9 +16,6 @@ Dependent Information Table. This table is not required for all
processors supported by RTEMS. This chapter describes the
contents, if any, for a particular processor type.
@ifinfo
@node Processor Dependent Information Table CPU Dependent Information Table, Memory Requirements, Processor Dependent Information Table Introduction, Processor Dependent Information Table
@end ifinfo
@section CPU Dependent Information Table
The i960CA version of the RTEMS CPU Dependent

15
doc/supplements/i960/fatalerr.t
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@@ -6,20 +6,8 @@
@c $Id$
@c
@ifinfo
@node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Interrupt Stack, Top
@end ifinfo
@chapter Default Fatal Error Processing
@ifinfo
@menu
* Default Fatal Error Processing Introduction::
* Default Fatal Error Processing Default Fatal Error Handler Operations::
@end menu
@end ifinfo
@ifinfo
@node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing
@end ifinfo
@section Introduction
Upon detection of a fatal error by either the
@@ -32,9 +20,6 @@ default fatal error handler is then invoked. This chapter
describes the precise operations of the default fatal error
handler.
@ifinfo
@node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing
@end ifinfo
@section Default Fatal Error Handler Operations
The default fatal error handler which is invoked by

2
doc/supplements/i960/i960.texi
View File

@@ -72,7 +72,7 @@ END-INFO-DIR-ENTRY
@include cputable.texi
@include wksheets.texi
@include timing.texi
@include timedata.texi
@include timeCVME961.texi
@ifinfo
@node Top, Preface, (dir), (dir)
@top c_i960

35
doc/supplements/i960/intr_NOTIMES.t
View File

@@ -6,25 +6,8 @@
@c $Id$
@c
@ifinfo
@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
@end ifinfo
@chapter Interrupt Processing
@ifinfo
@menu
* Interrupt Processing Introduction::
* Interrupt Processing Vectoring of Interrupt Handler::
* Interrupt Processing Interrupt Record::
* Interrupt Processing Interrupt Levels::
* Interrupt Processing Disabling of Interrupts by RTEMS::
* Interrupt Processing Register Cache Flushing::
* Interrupt Processing Interrupt Stack::
@end menu
@end ifinfo
@ifinfo
@node Interrupt Processing Introduction, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing, Interrupt Processing
@end ifinfo
@section Introduction
Different types of processors respond to the
@@ -42,9 +25,6 @@ processor's unique architecture. Discussed in this chapter are
the the processor's response and control mechanisms as they
pertain to RTEMS.
@ifinfo
@node Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing Interrupt Record, Interrupt Processing Introduction, Interrupt Processing
@end ifinfo
@section Vectoring of Interrupt Handler
Upon receipt of an interrupt the i960CA
@@ -87,9 +67,6 @@ Interrupt Record is examined by RTEMS to determine when an outer
most interrupt is being exited. Therefore, the user application
code MUST NOT modify this bit.
@ifinfo
@node Interrupt Processing Interrupt Record, Interrupt Processing Interrupt Levels, Interrupt Processing Vectoring of Interrupt Handler, Interrupt Processing
@end ifinfo
@section Interrupt Record
The structure of the Interrupt Record for the i960CA
@@ -151,9 +128,6 @@ response to an interrupt is as follows:
@end html
@end ifset
@ifinfo
@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Record, Interrupt Processing
@end ifinfo
@section Interrupt Levels
Thirty-two levels (0-31) of interrupt priorities are
@@ -169,9 +143,6 @@ through 31 directly correspond to i960CA interrupt levels. All
other RTEMS interrupt levels are undefined and their behavior is
unpredictable.
@ifinfo
@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Register Cache Flushing, Interrupt Processing Interrupt Levels, Interrupt Processing
@end ifinfo
@section Disabling of Interrupts by RTEMS
During the execution of directive calls, critical
@@ -194,9 +165,6 @@ occur due to the inability of RTEMS to protect its critical
sections. However, ISRs that make no system calls may safely
execute as non-maskable interrupts.
@ifinfo
@node Interrupt Processing Register Cache Flushing, Interrupt Processing Interrupt Stack, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing
@end ifinfo
@section Register Cache Flushing
The i960CA version of the RTEMS interrupt manager is
@@ -214,9 +182,6 @@ nested interrupt or when a context switch is not necessary.
This optimization is essential to providing high-performance
interrupt management on the i960CA.
@ifinfo
@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Register Cache Flushing, Interrupt Processing
@end ifinfo
@section Interrupt Stack
On the i960CA, RTEMS allocates the interrupt stack

15
doc/supplements/i960/memmodel.t
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@@ -6,20 +6,8 @@
@c $Id$
@c
@ifinfo
@node Memory Model, Memory Model Introduction, Calling Conventions Leaf Procedures, Top
@end ifinfo
@chapter Memory Model
@ifinfo
@menu
* Memory Model Introduction::
* Memory Model Flat Memory Model::
@end menu
@end ifinfo
@ifinfo
@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
@end ifinfo
@section Introduction
A processor may support any combination of memory
@@ -31,9 +19,6 @@ memory of any kind. The appropriate memory model for RTEMS
provided by the targeted processor and related characteristics
of that model are described in this chapter.
@ifinfo
@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
@end ifinfo
@section Flat Memory Model
The i960CA supports a flat 32-bit address space with

45
doc/supplements/i960/timeCVME961.t
View File

@@ -11,40 +11,12 @@
\global\advance \smallskipamount by -4pt
@end tex
@ifinfo
@node CVME961 Timing Data, CVME961 Timing Data Introduction, Timing Specification Terminology, Top
@end ifinfo
@chapter Timing Data
@ifinfo
@menu
* CVME961 Timing Data Introduction::
* CVME961 Timing Data Hardware Platform::
* CVME961 Timing Data Interrupt Latency::
* CVME961 Timing Data Context Switch::
* CVME961 Timing Data Directive Times::
* CVME961 Timing Data Task Manager::
* CVME961 Timing Data Interrupt Manager::
* CVME961 Timing Data Clock Manager::
* CVME961 Timing Data Timer Manager::
* CVME961 Timing Data Semaphore Manager::
* CVME961 Timing Data Message Manager::
* CVME961 Timing Data Event Manager::
* CVME961 Timing Data Signal Manager::
* CVME961 Timing Data Partition Manager::
* CVME961 Timing Data Region Manager::
* CVME961 Timing Data Dual-Ported Memory Manager::
* CVME961 Timing Data I/O Manager::
* CVME961 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@chapter CVME961 Timing Data
NOTE: The CVME961 board used by the RTEMS Project to
obtain i960CA times is currently broken. The information in
this chapter was obtained using Release 3.2.1.
@ifinfo
@node CVME961 Timing Data Introduction, CVME961 Timing Data Hardware Platform, CVME961 Timing Data, CVME961 Timing Data
@end ifinfo
@section Introduction
The timing data for the i960CA version of RTEMS is
@@ -55,9 +27,6 @@ understanding of each directive time provided. Also, provided
is a description of the interrupt latency and the context
switch times as they pertain to the i960CA version of RTEMS.
@ifinfo
@node CVME961 Timing Data Hardware Platform, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Introduction, CVME961 Timing Data
@end ifinfo
@section Hardware Platform
All times reported except for the maximum period
@@ -78,9 +47,6 @@ executed with interrupts disabled, including the instructions to
disable and enable interrupts, was divided by 33 to simulate a
i960CA executing at 33 Mhz with zero wait states.
@ifinfo
@node CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Context Switch, CVME961 Timing Data Hardware Platform, CVME961 Timing Data
@end ifinfo
@section Interrupt Latency
The maximum period with interrupts disabled within
@@ -104,9 +70,6 @@ vector and entry overhead time was generated on the Cyclone
CVME961 benchmark platform using the sysctl instruction as the
interrupt source.
@ifinfo
@node CVME961 Timing Data Context Switch, CVME961 Timing Data Directive Times, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data
@end ifinfo
@section Context Switch
The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
@@ -123,9 +86,3 @@ and floating point tasks are not supported.
The following table summarizes the context switch
times for the CVME961 benchmark platform:
@include timetbl.texi
@tex
\global\advance \smallskipamount by 4pt
@end tex

131
doc/supplements/i960/timedata.t
View File

@@ -1,131 +0,0 @@
@c
@c COPYRIGHT (c) 1988-1998.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c $Id$
@c
@include ../../common/timemac.texi
@tex
\global\advance \smallskipamount by -4pt
@end tex
@ifinfo
@node CVME961 Timing Data, CVME961 Timing Data Introduction, Timing Specification Terminology, Top
@end ifinfo
@chapter Timing Data
@ifinfo
@menu
* CVME961 Timing Data Introduction::
* CVME961 Timing Data Hardware Platform::
* CVME961 Timing Data Interrupt Latency::
* CVME961 Timing Data Context Switch::
* CVME961 Timing Data Directive Times::
* CVME961 Timing Data Task Manager::
* CVME961 Timing Data Interrupt Manager::
* CVME961 Timing Data Clock Manager::
* CVME961 Timing Data Timer Manager::
* CVME961 Timing Data Semaphore Manager::
* CVME961 Timing Data Message Manager::
* CVME961 Timing Data Event Manager::
* CVME961 Timing Data Signal Manager::
* CVME961 Timing Data Partition Manager::
* CVME961 Timing Data Region Manager::
* CVME961 Timing Data Dual-Ported Memory Manager::
* CVME961 Timing Data I/O Manager::
* CVME961 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
NOTE: The CVME961 board used by the RTEMS Project to
obtain i960CA times is currently broken. The information in
this chapter was obtained using Release 3.2.1.
@ifinfo
@node CVME961 Timing Data Introduction, CVME961 Timing Data Hardware Platform, CVME961 Timing Data, CVME961 Timing Data
@end ifinfo
@section Introduction
The timing data for the i960CA version of RTEMS is
provided along with the target dependent aspects concerning the
gathering of the timing data. The hardware platform used to
gather the times is described to give the reader a better
understanding of each directive time provided. Also, provided
is a description of the interrupt latency and the context
switch times as they pertain to the i960CA version of RTEMS.
@ifinfo
@node CVME961 Timing Data Hardware Platform, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Introduction, CVME961 Timing Data
@end ifinfo
@section Hardware Platform
All times reported except for the maximum period
interrupts are disabled by RTEMS were measured using a Cyclone
Microsystems CVME961 board. The CVME961 is a 33 Mhz board with
dynamic RAM which has two wait state dynamic memory (four CPU
cycles) for read accesses and one wait state (two CPU cycles)
for write accesses. The Z8536 on a SQUALL SQSIO4 mezzanine
board was used to measure elapsed time with one-half microsecond
resolution. All sources of hardware interrupts are disabled,
although the interrupt level of the i960CA allows all interrupts.
The maximum interrupt disable period was measured by
summing the number of CPU cycles required by each assembly
language instruction executed while interrupts were disabled.
Zero wait state memory was assumed. The total CPU cycles
executed with interrupts disabled, including the instructions to
disable and enable interrupts, was divided by 33 to simulate a
i960CA executing at 33 Mhz with zero wait states.
@ifinfo
@node CVME961 Timing Data Interrupt Latency, CVME961 Timing Data Context Switch, CVME961 Timing Data Hardware Platform, CVME961 Timing Data
@end ifinfo
@section Interrupt Latency
The maximum period with interrupts disabled within
RTEMS is less than
RTEMS_MAXIMUM_DISABLE_PERIOD microseconds including the instructions
which disable and re-enable interrupts. The time required for
the i960CA to generate an interrupt using the sysctl
instruction, vectoring to an interrupt handler, and for the
RTEMS entry overhead before invoking the user's interrupt
handler are a total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield
a worst case interrupt latency of less than
RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. [NOTE: The maximum period with interrupts
disabled within RTEMS was last calculated for Release
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
It should be noted again that the maximum period with
interrupts disabled within RTEMS is hand-timed. The interrupt
vector and entry overhead time was generated on the Cyclone
CVME961 benchmark platform using the sysctl instruction as the
interrupt source.
@ifinfo
@node CVME961 Timing Data Context Switch, CVME961 Timing Data Directive Times, CVME961 Timing Data Interrupt Latency, CVME961 Timing Data
@end ifinfo
@section Context Switch
The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
microseconds on the Cyclone CVME961 benchmark platform. This
time represents the raw context switch time with no user
extensions configured. Additional execution time is required
when a TSWITCH user extension is configured. The use of the
TSWITCH extension is application dependent. Thus, its execution
time is not considered part of the base context switch time.
The CVME961 has no hardware floating point capability
and floating point tasks are not supported.
The following table summarizes the context switch
times for the CVME961 benchmark platform:
@include timetbl.texi
@tex
\global\advance \smallskipamount by 4pt
@end tex