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2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>

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* rtems/score/ppc.h: Remove rtems_multilib.
	Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>).
	* rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush.
	Remove _CPU_Data_Cache_Block_Invalidate.
This commit is contained in:
Joel Sherrill
2002-05-01 22:35:52 +00:00
parent 80fe968c12
commit 5a715de409
6 changed files with 38 additions and 84 deletions
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7
c/src/exec/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,10 @@
2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/score/ppc.h: Remove rtems_multilib.
Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>).
* rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush.
Remove _CPU_Data_Cache_Block_Invalidate.
2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* asm.h: Include cpuopts.h instead of targopts.h.

20
c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h
View File

@@ -765,26 +765,6 @@ void _CPU_Initialize_vectors(void);
); \
}
#define _CPU_Data_Cache_Block_Flush( _address ) \
do { register void *__address = (_address); \
register unsigned32 _zero = 0; \
asm volatile ( "dcbf %0,%1" : \
"=r" (_zero), "=r" (__address) : \
"0" (_zero), "1" (__address) \
); \
} while (0)
#define _CPU_Data_Cache_Block_Invalidate( _address ) \
do { register void *__address = (_address); \
register unsigned32 _zero = 0; \
asm volatile ( "dcbi %0,%1" : \
"=r" (_zero), "=r" (__address) : \
"0" (_zero), "1" (__address) \
); \
} while (0)
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter

34
c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
View File

@@ -98,33 +98,12 @@ extern "C" {
#define PPC_LOW_POWER_MODE_NONE 0
#define PPC_LOW_POWER_MODE_STANDARD 1
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_RFCI 1
#if defined(_SOFT_FLOAT)
#define PPC_HAS_FPU 0
#else
#define PPC_HAS_FPU 1
#endif
#define PPC_USE_MULTIPLE 1
#define PPC_I_CACHE 2048
#define PPC_D_CACHE 1024
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
#define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 0
#define PPC_INTERRUPT_MAX 16
#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
#define PPC_HAS_DOUBLE 0
#elif defined(ppc403) || defined(ppc405)
#if defined(ppc403) || defined(ppc405)
/*
* IBM 403
*
@@ -150,6 +129,17 @@ extern "C" {
#define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 1
#elif defined(mpc555)
#define CPU_MODEL_NAME "PowerPC 555"
/* Copied from mpc505 */
#define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16
/* Based on comments by Sergei Organov <osv@Javad.RU> */
#define PPC_I_CACHE 0
#define PPC_D_CACHE 0
#elif defined(mpc505) || defined(mpc509)
/*

7
cpukit/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,10 @@
2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/score/ppc.h: Remove rtems_multilib.
Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>).
* rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush.
Remove _CPU_Data_Cache_Block_Invalidate.
2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* asm.h: Include cpuopts.h instead of targopts.h.

20
cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h
View File

@@ -765,26 +765,6 @@ void _CPU_Initialize_vectors(void);
); \
}
#define _CPU_Data_Cache_Block_Flush( _address ) \
do { register void *__address = (_address); \
register unsigned32 _zero = 0; \
asm volatile ( "dcbf %0,%1" : \
"=r" (_zero), "=r" (__address) : \
"0" (_zero), "1" (__address) \
); \
} while (0)
#define _CPU_Data_Cache_Block_Invalidate( _address ) \
do { register void *__address = (_address); \
register unsigned32 _zero = 0; \
asm volatile ( "dcbi %0,%1" : \
"=r" (_zero), "=r" (__address) : \
"0" (_zero), "1" (__address) \
); \
} while (0)
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter

34
cpukit/score/cpu/powerpc/rtems/score/ppc.h
View File

@@ -98,33 +98,12 @@ extern "C" {
#define PPC_LOW_POWER_MODE_NONE 0
#define PPC_LOW_POWER_MODE_STANDARD 1
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_RFCI 1
#if defined(_SOFT_FLOAT)
#define PPC_HAS_FPU 0
#else
#define PPC_HAS_FPU 1
#endif
#define PPC_USE_MULTIPLE 1
#define PPC_I_CACHE 2048
#define PPC_D_CACHE 1024
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
#define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 0
#define PPC_INTERRUPT_MAX 16
#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
#define PPC_HAS_DOUBLE 0
#elif defined(ppc403) || defined(ppc405)
#if defined(ppc403) || defined(ppc405)
/*
* IBM 403
*
@@ -150,6 +129,17 @@ extern "C" {
#define PPC_HAS_EXCEPTION_PREFIX 0
#define PPC_HAS_EVPR 1
#elif defined(mpc555)
#define CPU_MODEL_NAME "PowerPC 555"
/* Copied from mpc505 */
#define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16
/* Based on comments by Sergei Organov <osv@Javad.RU> */
#define PPC_I_CACHE 0
#define PPC_D_CACHE 0
#elif defined(mpc505) || defined(mpc509)
/*