forked from Imagelibrary/rtems
2005-09-12 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
PR 822/bsps * console/console.c, startup/bspstart.c, startup/imbx8xx.c, startup/mmutlbtab.c, startup/start.S, vectors/vectors_init.c: Currently the MBX8xx BSP does not boot, because some logical errors are in the startup code. Additionally, the mpc8xx shared clock driver does not support the clocking scheme of some of the board variants, which are clocked from a 32768Hz (!) external crystal.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,13 @@
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2005-09-12 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
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PR 822/bsps
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* console/console.c, startup/bspstart.c, startup/imbx8xx.c,
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startup/mmutlbtab.c, startup/start.S, vectors/vectors_init.c:
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Currently the MBX8xx BSP does not boot, because some logical errors
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are in the startup code. Additionally, the mpc8xx shared clock driver
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does not support the clocking scheme of some of the board variants,
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which are clocked from a 32768Hz (!) external crystal.
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2003-12-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* startup/Makefile.am: start.S instead of start.s.
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@@ -542,6 +542,13 @@ serial_init()
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unsigned int dpaddr, memaddr;
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bd_t *bd;
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#if NVRAM_CONFIGURE == 1
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if ( ((nvram->console_mode & 0x06) != 0x04 ) ||
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((nvram->console_mode & 0x30) != 0x20 )) {
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/*
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* FIXME: refine this condition...
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*/
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#endif
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bd = eppcbugInfo;
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cp = cpmp;
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@@ -647,7 +654,26 @@ serial_init()
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/* Enable transmitter/receiver.
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*/
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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#if NVRAM_CONFIGURE == 1
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}
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else {
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const char bootmsg_text[]= "using EPPC bug for console I/O\n";
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_EPPCBug_pollWrite((nvram->console_printk_port & 0x70) >> 4,
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bootmsg_text,
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sizeof(bootmsg_text)-1);
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}
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#endif
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#if NVRAM_CONFIGURE == 1
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if ((nvram->console_mode & 0x30) == 0x20 ) {
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BSP_output_char = _BSP_output_char;
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}
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else {
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BSP_output_char = serial_putchar;
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}
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#else
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BSP_output_char = serial_putchar;
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#endif
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}
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void
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@@ -148,7 +148,7 @@ void bsp_start(void)
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myCpuRevision = get_ppc_cpu_revision();
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mmu_init();
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/*
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* Enable instruction and data caches. Do not force writethrough mode.
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*/
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@@ -201,7 +201,22 @@ void bsp_start(void)
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if( Cpu_table.interrupt_stack_size < 4 * 1024 )
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Cpu_table.interrupt_stack_size = 4 * 1024;
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Cpu_table.clicks_per_usec = 1; /* for 4MHz extclk */
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#if ( defined(mbx821_001b) ||\
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defined(mbx821_002b) ||\
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defined(mbx821_003b) ||\
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defined(mbx821_004b) ||\
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defined(mbx821_005b) ||\
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defined(mbx821_006b) ||\
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defined(mbx860_001b) ||\
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defined(mbx860_002b) ||\
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defined(mbx860_003b) ||\
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defined(mbx860_004b) ||\
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defined(mbx860_005b) ||\
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defined(mbx860_006b))
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Cpu_table.clicks_per_usec = 0; /* for 32768 Hz oscclk */
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#else
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Cpu_table.clicks_per_usec = 1; /* for 4MHz oscclk */
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#endif
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Cpu_table.serial_per_sec = 10000000;
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Cpu_table.serial_external_clock = 1;
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Cpu_table.serial_xon_xoff = 0;
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@@ -271,6 +271,7 @@ void _InitMBX8xx (void)
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m8xx.sccrk = M8xx_UNLOCK_KEY; /* unlock SCCR */
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m8xx.sccr = 0x02800000; /* for MBX860/MBX821 */
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#if 0 /* IMD hack: do not init PLL after EPPCbug load */
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/* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */
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/* - set the clock speed and set normal power mode */
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m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */
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@@ -300,6 +301,7 @@ void _InitMBX8xx (void)
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m8xx.plprcr = 0x4C400000;
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#else
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#error "MBX board not defined"
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#endif
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#endif
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/* Unlock the timebase and decrementer registers. */
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m8xx.tbk = M8xx_UNLOCK_KEY;
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@@ -316,6 +318,7 @@ void _InitMBX8xx (void)
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_mtspr( M8xx_TBU_WR, r1 );
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_mtspr( M8xx_TBL_WR, r1 );
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#if 0 /* IMD hack: do not init UPMs after EPPCbug load */
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/*
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* Memory Controller Initialization
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*/
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@@ -584,6 +587,7 @@ void _InitMBX8xx (void)
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#endif
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m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 |
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M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
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#endif /* IMD hack */
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/*
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* PCMCIA initialization
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*/
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@@ -31,19 +31,8 @@
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* location is equal to its real address.
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*/
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MMU_TLB_table_t MMU_TLB_table[] = {
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#if ( defined(mbx860_001b) )
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/*
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* DRAM: CS1, Start address 0x00000000, 2M,
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* ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
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* R/W,X for all, no ASID comparison, not cache-inhibited.
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* Last 512K block is cache-inhibited, but not guarded for use by EPPCBug.
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* EPN TWC RPN
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*/
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{ 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */
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{ 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */
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{ 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */
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{ 0x00180200, 0x05, 0x001809FF }, /* DRAM - PS=512K, cache-inhibited */
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#elif ( defined(mbx860_002b) || \
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#if ( defined(mbx860_001b) || \
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defined(mbx860_002b) || \
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defined(mbx860_003b) || \
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defined(mbx821_001b) || \
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defined(mbx821_002b) || \
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@@ -243,6 +243,46 @@ spin:
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*/
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#define LOADED_BY_EPPCBUG
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#define EARLY_CONSOLE
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/*
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* test function: blink orange led once
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*/
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#define LEDBLINK_DELAY (5*1000*1000)
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#define LEDPORT 0xFA100001
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#define LEDMASK 0xf0
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#define LEDON 0x00
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#define LEDOFF 0x08
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PUBLIC_VAR(ledblink)
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SYM(ledblink):
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lis r3,LEDBLINK_DELAY>>16
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ledblink1:
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subi r3,r3,1
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cmpi 0,1,r3,0
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bne ledblink1
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/*
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* turn orange led off
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*/
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lis r3,LEDPORT@ha
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lbz r0,LEDPORT@l(r3)
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andi. r0,r0,LEDMASK
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ori r0,r0,LEDOFF
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stb r0,LEDPORT@l(r3)
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lis r3,LEDBLINK_DELAY>>16
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ledblink2:
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subi r3,r3,1
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cmpi 0,1,r3,0
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bne ledblink2
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/*
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* turn orange led on
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*/
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lis r3,LEDPORT@ha
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lbz r0,LEDPORT@l(r3)
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andi. r0,r0,LEDMASK
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ori r0,r0,LEDON
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stb r0,LEDPORT@l(r3)
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blr
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/*
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* Initialization code
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*/
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@@ -115,6 +115,11 @@ void initialize_exceptions()
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if (!mpc8xx_vector_is_valid (i)) {
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continue;
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}
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#if 0 /* FIXME: refine this condition, leave Syscall for EPPCBug console */
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if (i == ASM_SYS_VECTOR) {
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continue;
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}
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#endif
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exception_table[i].exceptIndex = i;
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exception_table[i].hdl = exception_config.defaultRawEntry.hdl;
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exception_table[i].hdl.vector = i;
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