RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>

Browse Source 
PR 1573/cpukit
	* shared/irq/exception.S: Add a per cpu data structure which contains
	the information required by RTEMS for each CPU core. This
	encapsulates information such as thread executing, heir, idle and
	dispatch needed.
This commit is contained in:
Joel Sherrill
2010-06-29 00:38:20 +00:00
parent 15519cba23
commit 5a0b7914c8
2 changed files with 16 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
c/src/lib/libbsp/mips/ChangeLog
View File

@@ -1,3 +1,11 @@
2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
PR 1573/cpukit
* shared/irq/exception.S: Add a per cpu data structure which contains
the information required by RTEMS for each CPU core. This
encapsulates information such as thread executing, heir, idle and
dispatch needed.
2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com> 2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com>
* shared/liblnk/lnklib.S, shared/liblnk/pmon.S, shared/liblnk/regs.h, * shared/liblnk/lnklib.S, shared/liblnk/pmon.S, shared/liblnk/regs.h,

18
c/src/lib/libbsp/mips/shared/irq/exception.S
View File

@@ -35,6 +35,7 @@
#include <bspopts.h> #include <bspopts.h>
#include <rtems/asm.h> #include <rtems/asm.h>
#include <rtems/score/percpu.h>
#include <rtems/mips/iregdef.h> #include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h> #include <rtems/mips/idtcpu.h>
#if BSP_HAS_USC320 #if BSP_HAS_USC320
@@ -88,9 +89,7 @@
#endif #endif
EXTERN(_ISR_Nest_level, 4)
EXTERN(_Thread_Dispatch_disable_level,4) EXTERN(_Thread_Dispatch_disable_level,4)
EXTERN(_Context_Switch_necessary,1)
EXTERN(_ISR_Signals_to_thread_executing,1) EXTERN(_ISR_Signals_to_thread_executing,1)
.extern _Thread_Dispatch .extern _Thread_Dispatch
.extern _ISR_Vector_table .extern _ISR_Vector_table
@@ -236,10 +235,10 @@ _chk_int:
/* /*
* _ISR_Nest_level++; * _ISR_Nest_level++;
*/ */
lw t0,_ISR_Nest_level lw t0,ISR_NEST_LEVEL
NOP NOP
add t0,t0,1 add t0,t0,1
sw t0,_ISR_Nest_level sw t0,ISR_NEST_LEVEL
/* /*
* _Thread_Dispatch_disable_level++; * _Thread_Dispatch_disable_level++;
*/ */
@@ -299,10 +298,10 @@ _ISR_Handler_cleanup:
/* /*
* --_ISR_Nest_level; * --_ISR_Nest_level;
*/ */
lw t2,_ISR_Nest_level lw t2,ISR_NEST_LEVEL
NOP NOP
add t2,t2,-1 add t2,t2,-1
sw t2,_ISR_Nest_level sw t2,ISR_NEST_LEVEL
/* /*
* --_Thread_Dispatch_disable_level; * --_Thread_Dispatch_disable_level;
*/ */
@@ -324,13 +323,12 @@ _ISR_Handler_cleanup:
* restore stack * restore stack
* #endif * #endif
* *
* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) * if ( !_Context_Switch_necessary )
* goto the label "exit interrupt (simple case)" * goto the label "exit interrupt (simple case)"
*/ */
lb t0,_Context_Switch_necessary lb t0,DISPATCH_NEEDED
lb t1,_ISR_Signals_to_thread_executing
NOP NOP
or t0,t0,t1 or t0,t0,t0
beq t0,zero,_ISR_Handler_exit beq t0,zero,_ISR_Handler_exit
NOP NOP