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riscv: New CPU_Exception_frame

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Use the CPU_Interrupt_frame for the volatile context.  Add non-volatile
registers and extra state on top of it.

Update #3433.
This commit is contained in:
Sebastian Huber
2018-07-19 10:15:53 +02:00
parent d779a1e228
commit 5694b0cce4
4 changed files with 203 additions and 64 deletions
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38
cpukit/score/cpu/riscv/cpu.c
View File

@@ -130,6 +130,44 @@ RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa7, FA7 );
#endif /* __riscv_flen */ #endif /* __riscv_flen */
#define RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( field, off ) \
RTEMS_STATIC_ASSERT( \
offsetof( CPU_Exception_frame, field) == RISCV_EXCEPTION_FRAME_ ## off, \
riscv_context_offset_ ## field \
)
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( mcause, MCAUSE );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( sp, SP );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( gp, GP );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( tp, TP );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s2, S2 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s3, S3 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s4, S4 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s5, S5 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s6, S6 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s7, S7 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s8, S8 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s9, S9 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s10, S10 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s11, S11 );
#if __riscv_flen > 0
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs0, FS0 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs1, FS1 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs2, FS2 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs3, FS3 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs4, FS4 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs5, FS5 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs6, FS6 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs7, FS7 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs8, FS8 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs9, FS9 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs10, FS10 );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs11, FS11 );
#endif /* __riscv_flen */
RTEMS_STATIC_ASSERT( RTEMS_STATIC_ASSERT(
sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0, sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0,
riscv_interrupt_frame_size riscv_interrupt_frame_size

76
cpukit/score/cpu/riscv/include/rtems/score/cpu.h
View File

@@ -260,7 +260,81 @@ typedef enum {
} RISCV_Exception_code; } RISCV_Exception_code;
typedef struct { typedef struct {
unsigned long x[32];; uintptr_t mstatus;
uintptr_t mepc;
uintptr_t a2;
uintptr_t s0;
uintptr_t s1;
uintptr_t ra;
uintptr_t a3;
uintptr_t a4;
uintptr_t a5;
uintptr_t a6;
uintptr_t a7;
uintptr_t t0;
uintptr_t t1;
uintptr_t t2;
uintptr_t t3;
uintptr_t t4;
uintptr_t t5;
uintptr_t t6;
#if __riscv_flen > 0
uint32_t fcsr;
RISCV_Float ft0;
RISCV_Float ft1;
RISCV_Float ft2;
RISCV_Float ft3;
RISCV_Float ft4;
RISCV_Float ft5;
RISCV_Float ft6;
RISCV_Float ft7;
RISCV_Float ft8;
RISCV_Float ft9;
RISCV_Float ft10;
RISCV_Float ft11;
RISCV_Float fa0;
RISCV_Float fa1;
RISCV_Float fa2;
RISCV_Float fa3;
RISCV_Float fa4;
RISCV_Float fa5;
RISCV_Float fa6;
RISCV_Float fa7;
#endif
uintptr_t a0;
uintptr_t a1;
} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
typedef struct {
CPU_Interrupt_frame Interrupt_frame;
uintptr_t mcause;
uintptr_t sp;
uintptr_t gp;
uintptr_t tp;
uintptr_t s2;
uintptr_t s3;
uintptr_t s4;
uintptr_t s5;
uintptr_t s6;
uintptr_t s7;
uintptr_t s8;
uintptr_t s9;
uintptr_t s10;
uintptr_t s11;
#if __riscv_flen > 0
RISCV_Float fs0;
RISCV_Float fs1;
RISCV_Float fs2;
RISCV_Float fs3;
RISCV_Float fs4;
RISCV_Float fs5;
RISCV_Float fs6;
RISCV_Float fs7;
RISCV_Float fs8;
RISCV_Float fs9;
RISCV_Float fs10;
RISCV_Float fs11;
#endif
} CPU_Exception_frame; } CPU_Exception_frame;
/** /**

100
cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
View File

@@ -94,11 +94,11 @@
#define RISCV_CONTEXT_FCSR 68 #define RISCV_CONTEXT_FCSR 68
#define RISCV_CONTEXT_F( x ) (72 + 4 * (x)) #define RISCV_CONTEXT_F( x ) ( 72 + 4 * x )
#define RISCV_INTERRUPT_FRAME_FCSR 72 #define RISCV_INTERRUPT_FRAME_FCSR 72
#define RISCV_INTERRUPT_FRAME_F( x ) (76 + 4 * (x)) #define RISCV_INTERRUPT_FRAME_F( x ) ( 76 + 4 * x )
#define RISCV_INTERRUPT_FRAME_A0 156 #define RISCV_INTERRUPT_FRAME_A0 156
#define RISCV_INTERRUPT_FRAME_A1 160 #define RISCV_INTERRUPT_FRAME_A1 160
@@ -109,11 +109,11 @@
#define RISCV_CONTEXT_FCSR 68 #define RISCV_CONTEXT_FCSR 68
#define RISCV_CONTEXT_F( x ) (72 + 8 * (x)) #define RISCV_CONTEXT_F( x ) ( 72 + 8 * x )
#define RISCV_INTERRUPT_FRAME_FCSR 72 #define RISCV_INTERRUPT_FRAME_FCSR 72
#define RISCV_INTERRUPT_FRAME_F( x ) (80 + 8 * (x)) #define RISCV_INTERRUPT_FRAME_F( x ) ( 80 + 8 * x )
#define RISCV_INTERRUPT_FRAME_A0 240 #define RISCV_INTERRUPT_FRAME_A0 240
#define RISCV_INTERRUPT_FRAME_A1 244 #define RISCV_INTERRUPT_FRAME_A1 244
@@ -122,6 +122,8 @@
#endif /* __riscv_flen */ #endif /* __riscv_flen */
#define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 4 * x )
#elif __riscv_xlen == 64 #elif __riscv_xlen == 64
#define RISCV_CONTEXT_RA 8 #define RISCV_CONTEXT_RA 8
@@ -170,11 +172,11 @@
#define RISCV_CONTEXT_FCSR 128 #define RISCV_CONTEXT_FCSR 128
#define RISCV_CONTEXT_F( x ) (132 + 4 * (x)) #define RISCV_CONTEXT_F( x ) ( 132 + 4 * x )
#define RISCV_INTERRUPT_FRAME_FCSR 144 #define RISCV_INTERRUPT_FRAME_FCSR 144
#define RISCV_INTERRUPT_FRAME_F( x ) (148 + 4 * (x)) #define RISCV_INTERRUPT_FRAME_F( x ) ( 148 + 4 * x )
#define RISCV_INTERRUPT_FRAME_A0 232 #define RISCV_INTERRUPT_FRAME_A0 232
#define RISCV_INTERRUPT_FRAME_A1 240 #define RISCV_INTERRUPT_FRAME_A1 240
@@ -185,11 +187,11 @@
#define RISCV_CONTEXT_FCSR 128 #define RISCV_CONTEXT_FCSR 128
#define RISCV_CONTEXT_F( x ) (136 + 8 * (x)) #define RISCV_CONTEXT_F( x ) ( 136 + 8 * x )
#define RISCV_INTERRUPT_FRAME_FCSR 144 #define RISCV_INTERRUPT_FRAME_FCSR 144
#define RISCV_INTERRUPT_FRAME_F( x ) (152 + 8 * (x)) #define RISCV_INTERRUPT_FRAME_F( x ) ( 152 + 8 * x )
#define RISCV_INTERRUPT_FRAME_A0 312 #define RISCV_INTERRUPT_FRAME_A0 312
#define RISCV_INTERRUPT_FRAME_A1 320 #define RISCV_INTERRUPT_FRAME_A1 320
@@ -198,8 +200,25 @@
#endif /* __riscv_flen */ #endif /* __riscv_flen */
#define RISCV_EXCEPTION_FRAME_X( x ) ( CPU_INTERRUPT_FRAME_SIZE + 8 * x )
#endif /* __riscv_xlen */ #endif /* __riscv_xlen */
#define RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 )
#define RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 )
#define RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 )
#define RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 )
#define RISCV_EXCEPTION_FRAME_S2 RISCV_EXCEPTION_FRAME_X( 4 )
#define RISCV_EXCEPTION_FRAME_S3 RISCV_EXCEPTION_FRAME_X( 5 )
#define RISCV_EXCEPTION_FRAME_S4 RISCV_EXCEPTION_FRAME_X( 6 )
#define RISCV_EXCEPTION_FRAME_S5 RISCV_EXCEPTION_FRAME_X( 7 )
#define RISCV_EXCEPTION_FRAME_S6 RISCV_EXCEPTION_FRAME_X( 8 )
#define RISCV_EXCEPTION_FRAME_S7 RISCV_EXCEPTION_FRAME_X( 9 )
#define RISCV_EXCEPTION_FRAME_S8 RISCV_EXCEPTION_FRAME_X( 10 )
#define RISCV_EXCEPTION_FRAME_S9 RISCV_EXCEPTION_FRAME_X( 11 )
#define RISCV_EXCEPTION_FRAME_S10 RISCV_EXCEPTION_FRAME_X( 12 )
#define RISCV_EXCEPTION_FRAME_S11 RISCV_EXCEPTION_FRAME_X( 13 )
#if __riscv_flen > 0 #if __riscv_flen > 0
#define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 ) #define RISCV_CONTEXT_FS0 RISCV_CONTEXT_F( 0 )
@@ -236,6 +255,25 @@
#define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 ) #define RISCV_INTERRUPT_FRAME_FA6 RISCV_INTERRUPT_FRAME_F( 18 )
#define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 ) #define RISCV_INTERRUPT_FRAME_FA7 RISCV_INTERRUPT_FRAME_F( 19 )
#if __riscv_flen == 32
#define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 4 * x )
#elif __riscv_flen == 64
#define RISCV_EXCEPTION_FRAME_F( x ) ( RISCV_EXCEPTION_FRAME_X( 14 ) + 8 * x )
#endif
#define RISCV_EXCEPTION_FRAME_FS0 RISCV_EXCEPTION_FRAME_F( 0 )
#define RISCV_EXCEPTION_FRAME_FS1 RISCV_EXCEPTION_FRAME_F( 1 )
#define RISCV_EXCEPTION_FRAME_FS2 RISCV_EXCEPTION_FRAME_F( 2 )
#define RISCV_EXCEPTION_FRAME_FS3 RISCV_EXCEPTION_FRAME_F( 3 )
#define RISCV_EXCEPTION_FRAME_FS4 RISCV_EXCEPTION_FRAME_F( 4 )
#define RISCV_EXCEPTION_FRAME_FS5 RISCV_EXCEPTION_FRAME_F( 5 )
#define RISCV_EXCEPTION_FRAME_FS6 RISCV_EXCEPTION_FRAME_F( 6 )
#define RISCV_EXCEPTION_FRAME_FS7 RISCV_EXCEPTION_FRAME_F( 7 )
#define RISCV_EXCEPTION_FRAME_FS8 RISCV_EXCEPTION_FRAME_F( 8 )
#define RISCV_EXCEPTION_FRAME_FS9 RISCV_EXCEPTION_FRAME_F( 9 )
#define RISCV_EXCEPTION_FRAME_FS10 RISCV_EXCEPTION_FRAME_F( 10 )
#define RISCV_EXCEPTION_FRAME_FS11 RISCV_EXCEPTION_FRAME_F( 11 )
#endif /* __riscv_flen */ #endif /* __riscv_flen */
#ifndef ASM #ifndef ASM
@@ -244,52 +282,6 @@
extern "C" { extern "C" {
#endif #endif
typedef struct {
uintptr_t mstatus;
uintptr_t mepc;
uintptr_t a2;
uintptr_t s0;
uintptr_t s1;
uintptr_t ra;
uintptr_t a3;
uintptr_t a4;
uintptr_t a5;
uintptr_t a6;
uintptr_t a7;
uintptr_t t0;
uintptr_t t1;
uintptr_t t2;
uintptr_t t3;
uintptr_t t4;
uintptr_t t5;
uintptr_t t6;
#if __riscv_flen > 0
uint32_t fcsr;
RISCV_Float ft0;
RISCV_Float ft1;
RISCV_Float ft2;
RISCV_Float ft3;
RISCV_Float ft4;
RISCV_Float ft5;
RISCV_Float ft6;
RISCV_Float ft7;
RISCV_Float ft8;
RISCV_Float ft9;
RISCV_Float ft10;
RISCV_Float ft11;
RISCV_Float fa0;
RISCV_Float fa1;
RISCV_Float fa2;
RISCV_Float fa3;
RISCV_Float fa4;
RISCV_Float fa5;
RISCV_Float fa6;
RISCV_Float fa7;
#endif
uintptr_t a0;
uintptr_t a1;
} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
#ifdef __riscv_atomic #ifdef __riscv_atomic
typedef struct { typedef struct {
uint64_t clear_reservations; uint64_t clear_reservations;

53
cpukit/score/cpu/riscv/riscv-exception-frame-print.c
View File

@@ -1,4 +1,5 @@
/* /*
* Copyright (c) 2018 embedded brains GmbH
* Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk> * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -31,15 +32,49 @@
#include <rtems/bspIo.h> #include <rtems/bspIo.h>
#include <inttypes.h> #include <inttypes.h>
#if __riscv_xlen == 32
#define PRINT_REG "0x%08" PRIxPTR
#elif __riscv_xlen == 64
#define PRINT_REG "0x%016" PRIxPTR
#endif
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
{ {
int i; printk("mstatus 0x%08" PRIxPTR "\n", frame->Interrupt_frame.mstatus);
printk("mcause " PRINT_REG "\n", frame->mcause);
for ( i = 0; i < 32; ++i ) { printk("mepc " PRINT_REG "\n", frame->Interrupt_frame.mepc);
#if __riscv_xlen == 32 printk("ra " PRINT_REG "\n", frame->Interrupt_frame.ra);
printk( "x%02i = 0x%032" PRIx32 "\n", i, frame->x[i]); printk("sp " PRINT_REG "\n", frame->sp);
#else /* xlen == 64 */ printk("gp " PRINT_REG "\n", frame->gp);
printk( "x%02i = 0x%032" PRIx64 "\n", i, frame->x[i]); printk("tp " PRINT_REG "\n", frame->tp);
#endif printk("t0 " PRINT_REG "\n", frame->Interrupt_frame.t0);
} printk("t1 " PRINT_REG "\n", frame->Interrupt_frame.t1);
printk("t2 " PRINT_REG "\n", frame->Interrupt_frame.t2);
printk("s0 " PRINT_REG "\n", frame->Interrupt_frame.s0);
printk("s1 " PRINT_REG "\n", frame->Interrupt_frame.s1);
printk("a0 " PRINT_REG "\n", frame->Interrupt_frame.a0);
printk("a1 " PRINT_REG "\n", frame->Interrupt_frame.a1);
printk("a2 " PRINT_REG "\n", frame->Interrupt_frame.a2);
printk("a3 " PRINT_REG "\n", frame->Interrupt_frame.a3);
printk("a4 " PRINT_REG "\n", frame->Interrupt_frame.a4);
printk("a5 " PRINT_REG "\n", frame->Interrupt_frame.a5);
printk("a6 " PRINT_REG "\n", frame->Interrupt_frame.a6);
printk("a7 " PRINT_REG "\n", frame->Interrupt_frame.a7);
printk("s2 " PRINT_REG "\n", frame->s2);
printk("s3 " PRINT_REG "\n", frame->s3);
printk("s4 " PRINT_REG "\n", frame->s4);
printk("s5 " PRINT_REG "\n", frame->s5);
printk("s6 " PRINT_REG "\n", frame->s6);
printk("s7 " PRINT_REG "\n", frame->s7);
printk("s8 " PRINT_REG "\n", frame->s8);
printk("s9 " PRINT_REG "\n", frame->s9);
printk("s10 " PRINT_REG "\n", frame->s10);
printk("s11 " PRINT_REG "\n", frame->s11);
printk("t3 " PRINT_REG "\n", frame->Interrupt_frame.t3);
printk("t4 " PRINT_REG "\n", frame->Interrupt_frame.t4);
printk("t5 " PRINT_REG "\n", frame->Interrupt_frame.t5);
printk("t6 " PRINT_REG "\n", frame->Interrupt_frame.t6);
#if __riscv_flen > 0
printk("fcsr 0x%08" PRIx32 "\n", frame->Interrupt_frame.fcsr);
#endif /* __riscv_flen */
} }