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bsp/gen83xx: Fix CSB clock calculation for MPC8309

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This commit is contained in:
Sebastian Huber
2012-12-19 13:41:27 +01:00
parent ef5e4526dc
commit 566c05c896
1 changed files with 6 additions and 1 deletions
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5
c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
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@@ -361,7 +361,12 @@
* derived values for all boards * derived values for all boards
*/ */
/* value of input clock divider (derived from pll mode reg) */ /* value of input clock divider (derived from pll mode reg) */
#if MPC83XX_CHIP_TYPE != 8309
#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
#else
/* On the MPC8309 this bit is reserved */
#define BSP_SYSPLL_CKID 1
#endif
/* value of system pll (derived from pll mode reg) */ /* value of system pll (derived from pll mode reg) */
#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) #define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f)
/* value of system pll (derived from pll mode reg) */ /* value of system pll (derived from pll mode reg) */