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bsps/i386: Revert most SMP related changes

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The commit partially restores the _ISR_Handler code to the original
version in commit b8fc2de1ce.  A list of
reverted changes follows.

commit c236082873
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date:   Tue Jul 30 15:54:53 2013 +0200

    smp: Provide cache optimized Per_CPU_Control

    Delete _Per_CPU_Information_p.

This commit was completely reverted.

commit 39e51758c8
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date:   Fri Jun 14 14:00:38 2013 +0200

    smp: Add and use _CPU_SMP_Get_current_processor()

    Add and use _SMP_Get_current_processor() and
    rtems_smp_get_current_processor().

    Delete bsp_smp_interrupt_cpu().

    Change type of current processor index from int to uint32_t to match
    _SMP_Processor_count type.

This commit was completely reverted.

commit e94aa61b68
Author: Till Straumann <strauman@slac.stanford.edu>
Date:   Fri Aug 5 00:15:50 2011 +0000

    2011-08-04	Till Straumann <strauman@slac.stanford.edu>

    	* shared/irq/irq_asm.S: BUGFIX (introduced by SMP changes
    	which moved code around, apparently): *must* store i8259
    	mask to frame *before* switching to IRQ stack. The code
    	retrieves the mask after switching back to original stack.
    	Also, the IRQ stack has no reserved space for the mask;
    	storing it there could overwrite memory!

This commit was completely reverted.

commit 01f2692e33
Author: Jennifer Averett <Jennifer.Averett@OARcorp.com>
Date:   Mon Aug 1 13:41:50 2011 +0000

    2011-08-01	Jennifer Averett <Jennifer.Averett@OARcorp.com>

    	PR 1802
    	* shared/irq/irq_asm.S, shared/irq/irq_init.c, shared/smp/smp-imps.c,
    	shared/smp/smp-imps.h: Add SMP support for i386.
    	* shared/smp/getcpuid.c: New file.

The parts modifying the code of _ISR_Handler were reverted.

commit 66729db311
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date:   Wed Mar 16 20:05:17 2011 +0000

    2011-03-16	Jennifer Averett <jennifer.averett@OARcorp.com>

    	PR 1729/cpukit
    	* shared/irq/irq_asm.S: Add next step in SMP support. This adds an
    	allocated array of the Per_CPU structures to support multiple cpus vs
    	a single instance of the structure which is still used if SMP support
    	is disabled. Configuration support is also added to explicitly enable
    	or disable SMP. But SMP can only be enabled for the CPUs which will
    	support it initially -- SPARC and i386. With the stub BSP support, a
    	BSP can be run as a single core SMP system from an RTEMS data
    	structure standpoint.

This commit was completely reverted.
This commit is contained in:
Sebastian Huber
2013-08-02 09:05:29 +02:00
parent f8ad6c6f7f
commit 55b1aee441
1 changed files with 46 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

100
c/src/lib/libbsp/i386/shared/irq/irq_asm.S
View File

@@ -44,9 +44,17 @@ SYM (_ISR_Handler):
* Before this was point is reached the vectors unique
* entry point did the following:
*
* 1. saved scratch registers registers eax edx ecx
* 1. saved scratch registers registers eax edx ecx"
* 2. put the vector number in ecx.
*
* BEGINNING OF ESTABLISH SEGMENTS
*
* WARNING: If an interrupt can occur when the segments are
* not correct, then this is where we should establish
* the segments. In addition to establishing the
* segments, it may be necessary to establish a stack
* in the current data area on the outermost interrupt.
*
* NOTE: If the previous values of the segment registers are
* pushed, do not forget to adjust SAVED_REGS.
*
@@ -74,8 +82,6 @@ SYM (_ISR_Handler):
movl ebx, EBX_OFF(esp)
movl eax, ESP_OFF(esp)
movl ebp, EBP_OFF(esp)
movw SYM (i8259s_cache), ax /* save current i8259 interrupt mask */
movl eax, MSK_OFF(esp) /* save in stack frame */
#ifdef __SSE__
/* NOTE: SSE only is supported if the BSP enables fxsave/fxrstor
@@ -96,54 +102,15 @@ SYM (_ISR_Handler):
ldmxcsr ARG_OFF(esp) /* clean-slate MXCSR */
#endif
.check_stack_switch:
movl esp, ebp /* ebp = previous stack pointer */
#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP)
call SYM(_CPU_SMP_Get_current_processor)
sall $PER_CPU_CONTROL_SIZE_LOG2, eax
addl $SYM(_Per_CPU_Information), eax
movl eax, ebx
pushl ecx
call SYM(_ISR_SMP_Enter)
popl ecx
cmpl $0, eax
jne .i8259
movl PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
#else
movl $SYM(_Per_CPU_Information), ebx
/*
* Is this the outermost interrupt?
* Switch stacks if necessary
*/
cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx)
jne nested /* No, then continue */
movl PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
/*
* We want to insure that the old stack pointer is in ebp
* By saving it on every interrupt, all we have to do is
* movl ebp->esp near the end of every interrupt.
*/
nested:
incl PER_CPU_ISR_NEST_LEVEL(ebx) /* one nest level deeper */
incl SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
#endif
/*
* i8259 Management
*/
.i8259:
/* Do not disable any 8259 interrupts if this isn't from one */
cmp ecx, 16 /* is this a PIC IRQ? */
jge .end_of_i8259
jge .check_stack_switch
/*
* acknowledge the interrupt
*/
movw SYM (i8259s_cache), ax /* fetch current i8259 interrupt mask */
movw SYM (i8259s_cache), ax /* save current i8259 interrupt mask */
movl eax, MSK_OFF(esp) /* save in stack frame */
/*
* compute the new PIC mask:
@@ -167,7 +134,39 @@ nested:
outb $PIC_SLAVE_COMMAND_IO_PORT
.master:
outb $PIC_MASTER_COMMAND_IO_PORT
.end_of_i8259:
/*
* Now switch stacks if necessary
*/
PUBLIC (ISR_STOP)
ISR_STOP:
.check_stack_switch:
movl esp, ebp /* ebp = previous stack pointer */
movl $SYM(_Per_CPU_Information), ebx
/* is this the outermost interrupt? */
cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx)
jne nested /* No, then continue */
movl PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
/*
* We want to insure that the old stack pointer is in ebp
* By saving it on every interrupt, all we have to do is
* movl ebp->esp near the end of every interrupt.
*/
nested:
incl PER_CPU_ISR_NEST_LEVEL(ebx) /* one nest level deeper */
incl SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
/*
* GCC versions starting with 4.3 no longer place the cld
* instruction before string operations. We need to ensure
* it is set correctly for ISR handlers.
*/
cld
/*
* re-enable interrupts at processor level as the current
@@ -210,14 +209,8 @@ nested:
outb $PIC_MASTER_IMR_IO_PORT
movb ah, al
outb $PIC_SLAVE_IMR_IO_PORT
.dont_restore_i8259:
#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP)
call SYM(_ISR_SMP_Exit)
testl eax, eax
je .exit
#else
decl PER_CPU_ISR_NEST_LEVEL(ebx) /* one less ISR nest level */
/* If interrupts are nested, */
/* then dispatching is disabled */
@@ -231,7 +224,6 @@ nested:
/* Is task switch necessary? */
jne .schedule /* Yes, then call the scheduler */
jmp .exit /* No, exit */
#endif
.schedule:
/*