From 552e481699ff513fcf7e46298e9b08468c3abd51 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 5 Feb 2025 15:10:34 -0600 Subject: [PATCH] m68k/gen68340: Remove obsolete BSP Updates #5031 --- bsps/m68k/gen68340/README.md | 90 -- bsps/m68k/gen68340/btimer/btimer.c | 275 ------ bsps/m68k/gen68340/clock/ckinit.c | 116 --- bsps/m68k/gen68340/config/gen68340.cfg | 18 - bsps/m68k/gen68340/console/console.c | 709 -------------- bsps/m68k/gen68340/console/m340uart.c | 330 ------- bsps/m68k/gen68340/include/bsp.h | 104 -- bsps/m68k/gen68340/include/bsp/irq.h | 1 - bsps/m68k/gen68340/include/m340timer.h | 104 -- bsps/m68k/gen68340/include/m340uart.h | 183 ---- bsps/m68k/gen68340/include/m68340.h | 145 --- bsps/m68k/gen68340/include/m68340.inc | 148 --- bsps/m68k/gen68340/include/m68349.inc | 410 -------- bsps/m68k/gen68340/include/tm27.h | 1 - bsps/m68k/gen68340/start/dumpanic.c | 209 ---- bsps/m68k/gen68340/start/init68340.c | 38 - bsps/m68k/gen68340/start/linkcmds | 254 ----- bsps/m68k/gen68340/start/start.S | 896 ------------------ spec/build/bsps/m68k/gen68340/abi.yml | 18 - spec/build/bsps/m68k/gen68340/bspgen68340.yml | 61 -- spec/build/bsps/m68k/gen68340/start.yml | 14 - 21 files changed, 4124 deletions(-) delete mode 100644 bsps/m68k/gen68340/README.md delete mode 100644 bsps/m68k/gen68340/btimer/btimer.c delete mode 100644 bsps/m68k/gen68340/clock/ckinit.c delete mode 100644 bsps/m68k/gen68340/config/gen68340.cfg delete mode 100644 bsps/m68k/gen68340/console/console.c delete mode 100644 bsps/m68k/gen68340/console/m340uart.c delete mode 100644 bsps/m68k/gen68340/include/bsp.h delete mode 100644 bsps/m68k/gen68340/include/bsp/irq.h delete mode 100644 bsps/m68k/gen68340/include/m340timer.h delete mode 100644 bsps/m68k/gen68340/include/m340uart.h delete mode 100644 bsps/m68k/gen68340/include/m68340.h delete mode 100644 bsps/m68k/gen68340/include/m68340.inc delete mode 100644 bsps/m68k/gen68340/include/m68349.inc delete mode 100644 bsps/m68k/gen68340/include/tm27.h delete mode 100644 bsps/m68k/gen68340/start/dumpanic.c delete mode 100644 bsps/m68k/gen68340/start/init68340.c delete mode 100644 bsps/m68k/gen68340/start/linkcmds delete mode 100644 bsps/m68k/gen68340/start/start.S delete mode 100644 spec/build/bsps/m68k/gen68340/abi.yml delete mode 100644 spec/build/bsps/m68k/gen68340/bspgen68340.yml delete mode 100644 spec/build/bsps/m68k/gen68340/start.yml diff --git a/bsps/m68k/gen68340/README.md b/bsps/m68k/gen68340/README.md deleted file mode 100644 index 186f09eba4..0000000000 --- a/bsps/m68k/gen68340/README.md +++ /dev/null @@ -1,90 +0,0 @@ -gen68340 -======== - -This package requires a version of GCC that supports the `-mcpu32` option. - -Please send any comments, improvements, or bug reports to: -Geoffroy Montel -g_montel@yahoo.com - -This board support package works both MC68340 and MC68349 systems. - -Special console features: -- support of polled and interrupts mode (both MC68340 and MC68349) -- support of FIFO FULL mode (only for MC68340, the MC68349 doesn't have any timer, so - you may write your own timer driver if you have an external one) - -The type of the board is automatically recognised in the initialization sequence. - -WARNING: there's still no network driver! - I hope it will come in the next RTEMS version! - -``` -BSP NAME: gen68340 -BOARD: Generic 68360 as described in Motorola MC68340 User's Manual -BOARD: Home made MC68340 board -BOARD: Home made MC68349 board -BUS: none -CPU FAMILY: Motorola CPU32 -COPROCESSORS: none -MODE: not applicable - -DEBUG MONITOR: none (Hardware provides BDM) -DEBUG SETUP: EST Vision Ice - - -``` -PERIPHERALS ------------ -``` -TIMERS: two timers - RESOLUTION: one microsecond -SERIAL PORTS: 2 channel on the UART -REAL-TIME CLOCK: yes -DMA: yes -VIDEO: none -SCSI: none -NETWORKING: Ethernet on SCC1. -``` - - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: -IOSUPP DRIVER: -SHMSUPP: none -TIMER DRIVER: Timer 1 for timing test suites - Timer 2 for console's FIFO FULL mode -``` - - -STDIO ------ -``` -PORT: 1 -ELECTRICAL: -BAUD: 9600 -BITS PER CHARACTER: 8 -PARITY: None -STOP BITS: 1 -``` - - -Board description ------------------ -``` -clock rate: 25 MHz -bus width: 16-bit PROM, 32-bit DRAM -ROM: To 1 MByte, 60 nsec (0 wait states), chip select 0 -RAM: 1 to 16 MByte DRAM SIMM, 60 nsec (0 wait states), parity or nonparity -``` - -Host System ------------ -Cygwin 32 - -Verification (Standalone 68360) -------------------------------- -Single processor tests: Passed -Multi-processor tests: not applicable diff --git a/bsps/m68k/gen68340/btimer/btimer.c b/bsps/m68k/gen68340/btimer/btimer.c deleted file mode 100644 index 4fff208c55..0000000000 --- a/bsps/m68k/gen68340/btimer/btimer.c +++ /dev/null @@ -1,275 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * ATTENTION: As MC68349 has no built-in Timer, the following code doesn't work - * in a MC68349. You can't use FIFO full mode for the moment, but - * it should be easy to fix this by using an external timer. - * - * Use TIMER 1 for TIMEOUT when using FIFO FULL mode in UART driver - * Use TIMER 2 for timing test suites - * - * NOTE: It is important that the timer start/stop overhead be - * determined when porting or modifying this code. - */ - -/* - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include - -#define TIMER1_VECTOR 122 -#define TIMER1_IRQ_LEVEL 5 -#define TIMER1_INTERRUPT_ARBITRATION 5 - -#define TIMER2_VECTOR 123 -#define TIMER2_IRQ_LEVEL 4 -#define TIMER2_INTERRUPT_ARBITRATION 4 - -#define CLOCK_SPEED 25 /* in Mhz */ - -#define max(a,b) (((a)>(b)) ? (a) : (b)) - -void (*Restart_Fifo_Full_A_Timer)(void); -void (*Restart_Check_A_Timer)(void); -void (*Restart_Fifo_Full_B_Timer)(void); -void (*Restart_Check_B_Timer)(void); - -int preload = 0; - -/* - * __Restart_Fifo_Full_Timer - * - * When a character is received, sets the TIMER to raise an interrupt at - * TIMEOUT. It's necessary to prevent from not getting n-1 characters - * (with n the Uart Fifo size). - */ -static void __Restart_Fifo_Full_Timer (void) -{ - TSR1 |= m340_TO; - TCR1 &= ~m340_CPE; - WPREL11 = preload; - TCR1 |= m340_CPE; -} - -/* - * __Restart_Check_Timer - * - * When no character has been received recently, check now and then if whether - * a there's a character in the FIFO - */ -static void __Restart_Check_Timer (void) -{ - TSR1 |= m340_TO; - TCR1 &= ~m340_CPE; - WPREL11 = 0xFFFF; - TCR1 |= m340_CPE; -} - -/* - * __do_nothing - * - * We always restart the fifo full timer with a call to Restart_*_Timer - * if we do not use FIFO full, Restart_X_Timer are set to do __do_nothing - */ -static void __do_nothing (void) -{ -} - -#define Fifo_Full_on_A \ - (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL && \ - m340_uart_config[UART_CHANNEL_A].enable && \ - m340_uart_config[UART_CHANNEL_A].mode==UART_INTERRUPTS) -#define Fifo_Full_on_B \ - (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL && \ - m340_uart_config[UART_CHANNEL_B].enable && \ - m340_uart_config[UART_CHANNEL_B].mode==UART_INTERRUPTS) - -/* - * Fifo_Full_benchmark_timer_initialize - * - * initialize Timer 1 for FIFO full mode - */ -void Fifo_Full_benchmark_timer_initialize (void) -{ - float max_baud_rate; - int prescaler_output_tap = -1; - int nb_of_clock_ticks = 0; - rtems_isr_entry old_handler; - - /* - * USE TIMER 1 for UART FIFO FULL mode - */ - if ( Fifo_Full_on_A || Fifo_Full_on_B ) { - /* Disable the timer */ - TCR1 &= ~m340_SWR; - - /* Reset the interrupts */ - TSR1 &= ~(m340_TO | m340_TG | m340_TC); - - /* Init the stop bit for normal operation, ignore FREEZE, user privileges, - * set interrupt arbitration. - */ - TMCR1 = TIMER1_INTERRUPT_ARBITRATION; - - /* interrupt priority level and interrupt vector */ - TIR1 = TIMER1_VECTOR | (TIMER1_IRQ_LEVEL << 8); - - /* compute prescaler */ - if ( Fifo_Full_on_A && Fifo_Full_on_B) { - max_baud_rate = max( - m340_uart_config[UART_CHANNEL_A].rx_baudrate, - m340_uart_config[UART_CHANNEL_B].rx_baudrate - ); - } else if ( Fifo_Full_on_A ) { - max_baud_rate = m340_uart_config[UART_CHANNEL_A].rx_baudrate; - } else - max_baud_rate = m340_uart_config[UART_CHANNEL_B].rx_baudrate; - - /* find out config */ - nb_of_clock_ticks = (10/max_baud_rate)*(CLOCK_SPEED*1000000)*1.2; - if (nb_of_clock_ticks < 0xFFFF) { - preload = nb_of_clock_ticks; - prescaler_output_tap = -1; - } else if (nb_of_clock_ticks/2 < 0xFFFF) { - preload = nb_of_clock_ticks/2; - prescaler_output_tap = m340_Divide_by_2; - } else if (nb_of_clock_ticks/4 < 0xFFFF) { - preload = nb_of_clock_ticks/4; - prescaler_output_tap = m340_Divide_by_4; - } else if (nb_of_clock_ticks/8 < 0xFFFF) { - preload = nb_of_clock_ticks/8; - prescaler_output_tap = m340_Divide_by_16; - } else if (nb_of_clock_ticks/16 < 0xFFFF) { - preload = nb_of_clock_ticks/16; - prescaler_output_tap = m340_Divide_by_16; - } else if (nb_of_clock_ticks/32 < 0xFFFF) { - preload = nb_of_clock_ticks/32; - prescaler_output_tap = m340_Divide_by_32; - } else if (nb_of_clock_ticks/64 < 0xFFFF) { - preload = nb_of_clock_ticks/64; - prescaler_output_tap = m340_Divide_by_64; - } else if (nb_of_clock_ticks/128 < 0xFFFF) { - preload = nb_of_clock_ticks/128; - prescaler_output_tap = m340_Divide_by_128; - } else if (nb_of_clock_ticks/256 < 0xFFFF) { - preload = nb_of_clock_ticks/256; - prescaler_output_tap = m340_Divide_by_256; - } - - /* Input Capture/Output Compare (ICOC) */ - TCR1 = m340_SWR | m340_TO_Enabled | m340_ICOC; - if (prescaler_output_tap!=-1) TCR1 |= prescaler_output_tap | m340_PSE; - - /* install interrupt vector */ - rtems_interrupt_catch(InterruptHandler, TIMER1_VECTOR, &old_handler); - - } /* fifo full mode on a uart */ - - /* install routines */ - if ( Fifo_Full_on_A ) { - Restart_Check_A_Timer = __Restart_Check_Timer; - Restart_Fifo_Full_A_Timer = __Restart_Fifo_Full_Timer; - } else { - Restart_Check_A_Timer = __do_nothing; - Restart_Fifo_Full_A_Timer = __do_nothing; - } - - if ( Fifo_Full_on_B ) { - Restart_Check_B_Timer = __Restart_Check_Timer; - Restart_Fifo_Full_B_Timer = __Restart_Fifo_Full_Timer; - } else { - Restart_Check_B_Timer = __do_nothing; - Restart_Fifo_Full_B_Timer = __do_nothing; - } - - /* start checking timer */ - Restart_Check_A_Timer(); - Restart_Check_B_Timer(); -} - -/* - * benchmark_timer_initialize - * - * init Timer for timing test suites - */ -void benchmark_timer_initialize (void) -{ - /* Disable the timer */ - TCR2 &= ~m340_SWR; - - /* Reset the interrupts */ - TSR2 &= ~(m340_TO | m340_TG | m340_TC); - - /* Init the stop bit for normal operation, ignore FREEZE, user privileges, - set interrupt arbitration */ - TMCR1 = TIMER2_INTERRUPT_ARBITRATION; - - /* interrupt priority level and interrupt vector */ - TIR1 = TIMER2_VECTOR | (TIMER2_IRQ_LEVEL << 8); - - /* Init the stop bit for normal operation, ignore FREEZE, user privileges, - set interrupt arbitration */ - TMCR2 = TIMER2_INTERRUPT_ARBITRATION; - - /* Preload register 1 */ - WPREL21 = 0xFFFF; - - /* Input Capture/Output Compare (ICOC) */ - TCR2 = m340_SWR | m340_ICOC | m340_PSE | m340_Divide_by_16 | m340_CPE; -} - -/* - * benchmark_timer_read - * - * Return timer value in microsecond units - */ -uint32_t benchmark_timer_read (void) -{ - /* there's CLOCK_SPEED / 16 micro seconds between two timer - * register decrements. - */ - return (((0xFFFF - TCNTR2) * CLOCK_SPEED) / 16); -} - -/* - * benchmark_timer_disable_subtracting_average_overhead - */ -void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) -{ -} diff --git a/bsps/m68k/gen68340/clock/ckinit.c b/bsps/m68k/gen68340/clock/ckinit.c deleted file mode 100644 index 8ca30426b7..0000000000 --- a/bsps/m68k/gen68340/clock/ckinit.c +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This routine initializes the MC68340/349 Periodic Interval Timer - */ - -/* - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include /* for atexit() */ -#include -#include -#include - -#define CLOCK_VECTOR 120 /* clock isr routine vector in the vbr */ -#define CLOCK_IRQ_LEVEL 6 /* clock isr level */ - -/* - * Clock_driver_ticks is a monotonically increasing counter of the - * number of clock ticks since the driver was initialized. - */ -volatile uint32_t Clock_driver_ticks; - -/* - * Periodic interval timer interrupt handler - */ -static rtems_isr -Clock_isr (rtems_vector_number vector) -{ - /* - * Announce the clock tick - */ - Clock_driver_ticks++; - rtems_clock_tick(); -} - -static void -Clock_exit (void) -{ - /* - * Turn off periodic interval timer - */ - SIMPITR = 0; -} - -static void -Install_clock (rtems_isr_entry clock_isr) -{ - uint32_t pitr_tmp; - uint32_t usecs_per_tick; - - Clock_driver_ticks = 0; - - set_vector (clock_isr, CLOCK_VECTOR, 1); - - /* sets the Periodic Interrupt Control Register PICR */ - SIMPICR = ( CLOCK_IRQ_LEVEL << 8 ) | ( CLOCK_VECTOR ); - - /* sets the PITR count value */ - /* this assumes a 32.765 kHz crystal */ - - usecs_per_tick = rtems_configuration_get_microseconds_per_tick(); - /* find out whether prescaler should be enabled or not */ - if ( usecs_per_tick <= 31128 ) { - pitr_tmp = ( usecs_per_tick * 8192 ) / 1000000 ; - } else { - pitr_tmp = ( usecs_per_tick / 1000000 ) * 16; - /* enable it */ - pitr_tmp |= 0x100; - } - - SIMPITR = (unsigned char) pitr_tmp; - - atexit (Clock_exit); -} - -void _Clock_Initialize( void ) -{ - Install_clock (Clock_isr); -} diff --git a/bsps/m68k/gen68340/config/gen68340.cfg b/bsps/m68k/gen68340/config/gen68340.cfg deleted file mode 100644 index 54fa7bcc02..0000000000 --- a/bsps/m68k/gen68340/config/gen68340.cfg +++ /dev/null @@ -1,18 +0,0 @@ -# -# Config file for a "generic 68340" BSP - -RTEMS_CPU=m68k - -include $(RTEMS_ROOT)/make/custom/default.cfg - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -mcpu=cpu32 - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -fomit-frame-pointer - -# FIXME: Disabled because linkcmds lacks proper KEEP() directives. See #2573. -# The following two lines enable compiling and linking on per element. -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/m68k/gen68340/console/console.c b/bsps/m68k/gen68340/console/console.c deleted file mode 100644 index 0f5e26d9e8..0000000000 --- a/bsps/m68k/gen68340/console/console.c +++ /dev/null @@ -1,709 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * 68340/68349 console serial I/O. - */ - -/* - * Author: - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define CONSOLE_VECTOR 121 -#define CONSOLE_IRQ_LEVEL 3 -#define CONSOLE_INTERRUPT_ARBITRATION 2 - -static void *ttypA; /* to remember which tty has been opened on channel A - used when interrupts are enabled */ - -static void *ttypB; /* to remember which tty has been opened on channel B - used when interrupts are enabled */ - -unsigned char DUIER_mirror = 0 ; /* reflects the state of IER register, which is Write Only */ -unsigned char Error_Status_A = 0; /* error status on Channel A */ -unsigned char Error_Status_B = 0; /* error status on Channel A */ - -/* - * Device-specific routines - */ - -#define USE_INTERRUPTS_A (m340_uart_config[UART_CHANNEL_A].mode==UART_INTERRUPTS) -#define USE_INTERRUPTS_B (m340_uart_config[UART_CHANNEL_B].mode==UART_INTERRUPTS) -#define CHANNEL_ENABLED_A m340_uart_config[UART_CHANNEL_A].enable -#define CHANNEL_ENABLED_B m340_uart_config[UART_CHANNEL_B].enable - -#define set_DUIER(a) DUIER_mirror |= (a); DUIER = DUIER_mirror -#define unset_DUIER(a) DUIER_mirror &= ~(a); DUIER = DUIER_mirror - -#define Enable_Interrupts_Tx_A if (USE_INTERRUPTS_A) set_DUIER(m340_TxRDYA) -#define Disable_Interrupts_Tx_A if (USE_INTERRUPTS_A) unset_DUIER(m340_TxRDYA) - -#define Enable_Interrupts_Tx_B if (USE_INTERRUPTS_B) set_DUIER(m340_TxRDYB) -#define Disable_Interrupts_Tx_B if (USE_INTERRUPTS_B) unset_DUIER(m340_TxRDYB) - -/****************************************************** - Name: InterruptHandler - Input parameters: vector number - Output parameters: - - Description: UART ISR Routine, called by _RTEMS_ISR - *****************************************************/ -rtems_isr -InterruptHandler (rtems_vector_number v) -{ - char ch; - - /***************************************************************************** - ** CHANNEL A ** - *****************************************************************************/ - - /* check Received Break*/ - if (DUSRA & m340_RB) { - Error_Status_A |= m340_RB; - /* reset error status */ - DUCRA = m340_Reset_Error_Status; - } - - /* buffer received ? */ - if (DUSRA & m340_Rx_RDY) { - do { - /* error encountered? */ - if (DUSRA & (m340_OE | m340_PE | m340_FE | m340_RB)) { - Error_Status_A |= DUSRA; - /* reset error status */ - DUCRA = m340_Reset_Error_Status; - /* all the characters in the queue may not be good */ - while (DUSRA & m340_Rx_RDY) - /* push them in a trash */ - ch = DURBA; - } - else { - /* this is necessary, otherwise it blocks when FIFO is full */ - ch = DURBA; - rtems_termios_enqueue_raw_characters(ttypA,&ch,1); - } - } while (DUSRA & m340_Rx_RDY); - Restart_Fifo_Full_A_Timer(); /* only if necessary (pointer to a fake function if - not in FIFO full mode) */ - } - - else /* if no character has been received */ - Restart_Check_A_Timer(); /* same remark */ - - /* ready to accept a character ? */ - if (DUISR & DUIER_mirror & m340_TxRDYA) { - Disable_Interrupts_Tx_A; - /* one character has been transmitted */ - rtems_termios_dequeue_characters(ttypA,1); - } - - /***************************************************************************** - ** CHANNEL B ** - *****************************************************************************/ - - /* check Received Break*/ - if (DUSRB & m340_RB) { - Error_Status_B |= m340_RB; - /* reset error status */ - DUCRB = m340_Reset_Error_Status; - } - - /* buffer received ? */ - if (DUSRB & m340_Rx_RDY) { - do { - if (DUSRB & (m340_OE | m340_PE | m340_FE | m340_RB)) { - Error_Status_B |= DUSRB; - /* reset error status */ - DUCRB = m340_Reset_Error_Status; - /* all the characters in the queue may not be good */ - while (DUSRB & m340_Rx_RDY) - /* push them in a trash */ - ch = DURBB; - } - else { - ch = DURBB; - rtems_termios_enqueue_raw_characters(ttypB,&ch,1); - } - - } while (DUSRB & m340_Rx_RDY); - Restart_Fifo_Full_B_Timer(); - } - else /* if no character has been received */ - Restart_Check_B_Timer(); - - /* ready to accept a character ? */ - if (DUISR & DUIER_mirror & m340_TxRDYB) { - Disable_Interrupts_Tx_B; - /* one character has been transmitted */ - rtems_termios_dequeue_characters(ttypB,1); - } -} - -/****************************************************** - Name: InterruptWrite - Input parameters: minor = channel, pointer to buffer, - and length of buffer to transmit - Output parameters: - - Description: write the first character of buf only - may be called by either console_write - or rtems_termios_enqueue_raw_characters - *****************************************************/ -static ssize_t -InterruptWrite (int minor, const char *buf, size_t len) -{ - if (minor==UART_CHANNEL_A) { - if (len>0) { - DUTBA=*buf; - Enable_Interrupts_Tx_A; - } - } - else if (minor==UART_CHANNEL_B) { - if (len>0) { - DUTBB=*buf; - Enable_Interrupts_Tx_B; - } - } - return 0; -} - -/****************************************************** - Name: dbug_out_char - Input parameters: channel, character to emit - Output parameters: - - Description: wait for the UART to be ready to emit - a character and send it - *****************************************************/ -void dbug_out_char( int minor, int ch ) -{ - if (minor==UART_CHANNEL_A) { - while (!(DUSRA & m340_Tx_RDY)) continue; - DUTBA=ch; - } - else if (minor==UART_CHANNEL_B) { - while (!(DUSRB & m340_Tx_RDY)) continue; - DUTBB=ch; - } -} - -/****************************************************** - Name: dbug_in_char - Input parameters: - - Output parameters: received character - Description: return the character in the UART - *****************************************************/ -int dbug_in_char( int minor ) -{ - if (minor==UART_CHANNEL_A) { - return DURBA; - } - else if (minor==UART_CHANNEL_B) { - return DURBB; - } - return 0; -} - -/****************************************************** - Name: dbug_char_present - Input parameters: channel # - Output parameters: TRUE or FALSE - Description: return whether there's a character - in the receive buffer - *****************************************************/ -int dbug_char_present( int minor ) -{ - if (minor==UART_CHANNEL_A) { - return (DUSRA & m340_Rx_RDY); - } - else if (minor==UART_CHANNEL_B) { - return (DUSRB & m340_Rx_RDY); - } - return 0; -} - -/****************************************************** - Name: dbugInitialise - Input parameters: - - Output parameters: - - Description: Init the UART - *****************************************************/ -static void -dbugInitialise (void) -{ - t_baud_speed_table uart_config; /* configuration of UARTS */ - - /* - * Reset Receiver - */ - DUCRA = m340_Reset_Receiver; - DUCRB = m340_Reset_Receiver; - - /* - * Reset Transmitter - */ - DUCRA = m340_Reset_Transmitter; - DUCRB = m340_Reset_Transmitter; - - /* - * Enable serial module for normal operation, ignore FREEZE, select the crystal clock, - * supervisor/user serial registers unrestricted - * interrupt arbitration at priority CONSOLE_INTERRUPT_ARBITRATION - * WARNING : 8 bits access only on this UART! - */ - DUMCRH = 0x00; - DUMCRL = CONSOLE_INTERRUPT_ARBITRATION; - - /* - * Interrupt level register - */ - DUILR = CONSOLE_IRQ_LEVEL; - - /* sets the IVR */ - DUIVR = CONSOLE_VECTOR; - - /* search for a correct m340 uart configuration */ - uart_config = Find_Right_m340_UART_Config(m340_uart_config[UART_CHANNEL_A].rx_baudrate, - m340_uart_config[UART_CHANNEL_A].tx_baudrate, - CHANNEL_ENABLED_A, - m340_uart_config[UART_CHANNEL_B].rx_baudrate, - m340_uart_config[UART_CHANNEL_B].tx_baudrate, - CHANNEL_ENABLED_B); - - /***************************************************************************** - ** CHANNEL A ** - *****************************************************************************/ - if (CHANNEL_ENABLED_A) { - - if (USE_INTERRUPTS_A) { - rtems_isr_entry old_handler; - - (void) rtems_interrupt_catch (InterruptHandler, - CONSOLE_VECTOR, - &old_handler); - - /* uncomment this if you want to pass control to your own ISR handler - it may be usefull to do so to check for performances with an oscilloscope */ - /* - { - CPU_ISR_raw_handler ignored; - _CPU_ISR_install_raw_handler( CONSOLE_VECTOR, _Debug_ISR_Handler_Console, &ignored ); - } - */ - - /* - * Interrupt Enable Register - * Enable Interrupts on Channel A Receiver Ready - */ - set_DUIER(m340_RxRDYA); - } - else { - /* - * Disable Interrupts on channel A - */ - unset_DUIER(m340_RxRDYA&m340_TxRDYA); - } - - /* - * Change set of baud speeds - * disable input control - */ - /* no good uart configuration ? */ - if (uart_config.nb<1) rtems_fatal_error_occurred (-1); - - if (uart_config.baud_speed_table[UART_CHANNEL_A].set==1) - DUACR = m340_BRG_Set1; - else - DUACR = m340_BRG_Set2; - - /* - * make OPCR an auxiliary function serving the communication channels - */ - DUOPCR = m340_OPCR_Aux; - - /* poll the XTAL_RDY bit until it is cleared to ensure that an unstable crystal - input is not applied to the baud rate generator */ - while (DUISR & m340_XTAL_RDY) continue; - - /* - * Serial Channel Baud Speed - */ - DUCSRA = (uart_config.baud_speed_table[UART_CHANNEL_A].rcs << 4) - | (uart_config.baud_speed_table[UART_CHANNEL_A].tcs); - - /* - * Serial Channel Configuration - */ - DUMR1A = m340_uart_config[UART_CHANNEL_A].parity_mode - | m340_uart_config[UART_CHANNEL_A].bits_per_char - | m340_RxRTS; - - if (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL) DUMR1A |= m340_R_F | m340_ERR; - - /* - * Serial Channel Configuration 2 - */ - DUMR2A |= m340_normal; - - /* - * Enable Channel A: transmitter and receiver - */ - DUCRA = m340_Transmitter_Enable | m340_Receiver_Enable; - } /* channel A enabled */ - - /***************************************************************************** - ** CHANNEL B ** - *****************************************************************************/ - if (CHANNEL_ENABLED_B) { - - /* we mustn't set the console vector twice! */ - if ((USE_INTERRUPTS_B && !(CHANNEL_ENABLED_A)) - || (USE_INTERRUPTS_B && CHANNEL_ENABLED_A && !USE_INTERRUPTS_A)) { - rtems_isr_entry old_handler; - - (void) rtems_interrupt_catch (InterruptHandler, - CONSOLE_VECTOR, - &old_handler); - - /* uncomment this if you want to pass control to your own ISR handler - it may be usefull to do so to check for performances with an oscilloscope */ - /* - { - CPU_ISR_raw_handler ignored; - _CPU_ISR_install_raw_handler( CONSOLE_VECTOR, _Debug_ISR_Handler_Console, &ignored ); - } - */ - - /* - * Interrupt Enable Register - * Enable Interrupts on Channel A Receiver Ready - */ - set_DUIER(m340_RxRDYB); - } - else { - /* - * Disable Interrupts on channel B - */ - unset_DUIER(m340_RxRDYB&m340_TxRDYB); - } - - /* - * Change set of baud speeds - * disable input control - */ - - /* no good uart configuration ? */ - if (uart_config.nb<2) rtems_fatal_error_occurred (-1); - - /* don't set DUACR twice! */ - if (!CHANNEL_ENABLED_A) { - if (uart_config.baud_speed_table[UART_CHANNEL_B].set==1) - DUACR = m340_BRG_Set1; - else - DUACR = m340_BRG_Set2; - } - - /* - * make OPCR an auxiliary function serving the communication channels - */ - if (!CHANNEL_ENABLED_A) DUOPCR = m340_OPCR_Aux; - - /* poll the XTAL_RDY bit until it is cleared to ensure that an unstable crystal - input is not applied to the baud rate generator */ - while (DUISR & m340_XTAL_RDY) continue; - - /* - * Serial Channel Baud Speed - */ - DUCSRB = (uart_config.baud_speed_table[UART_CHANNEL_B].rcs << 4) - | (uart_config.baud_speed_table[UART_CHANNEL_B].tcs); - - /* - * Serial Channel Configuration - */ - DUMR1B = m340_uart_config[UART_CHANNEL_B].parity_mode - | m340_uart_config[UART_CHANNEL_B].bits_per_char - | m340_RxRTS; - - if (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL) DUMR1B |= m340_R_F | m340_ERR; - - /* - * Serial Channel Configuration 2 - */ - DUMR2B |= m340_normal; - - /* - * Enable Channel A: transmitter and receiver - */ - DUCRB = m340_Transmitter_Enable | m340_Receiver_Enable; - } /* channel B enabled */ -} - -/****************************************************** - Name: SetAttributes - Input parameters: termios structure, channel - Output parameters: - - Description: return whether there's a character - in the receive buffer - TO DO: add the channel # to check for!! - *****************************************************/ -static int -SetAttributes (int minor, const struct termios *t) -{ - rtems_interrupt_level level; - float ispeed, ospeed; - - /* convert it */ - ispeed = rtems_termios_baud_to_number(t->c_ispeed); - ospeed = rtems_termios_baud_to_number(t->c_ospeed); - - if (ispeed || ospeed) { - /* update config table */ - m340_uart_config[UART_CHANNEL_A].rx_baudrate = ((minor==UART_CHANNEL_A)&&(ispeed!=0)) ? ispeed : m340_uart_config[UART_CHANNEL_A].rx_baudrate; - m340_uart_config[UART_CHANNEL_A].tx_baudrate = ((minor==UART_CHANNEL_A)&&(ospeed!=0)) ? ospeed : m340_uart_config[UART_CHANNEL_A].tx_baudrate; - m340_uart_config[UART_CHANNEL_B].rx_baudrate = ((minor==UART_CHANNEL_B)&&(ispeed!=0)) ? ispeed : m340_uart_config[UART_CHANNEL_B].rx_baudrate; - m340_uart_config[UART_CHANNEL_B].tx_baudrate = ((minor==UART_CHANNEL_B)&&(ospeed!=0)) ? ospeed : m340_uart_config[UART_CHANNEL_B].tx_baudrate; - } - - /* change parity */ - if (t->c_cflag & PARENB) { - if (t->c_cflag & PARODD) m340_uart_config[minor].parity_mode = m340_Odd_Parity; - else m340_uart_config[minor].parity_mode = m340_Even_Parity; - } - - /* change bits per character */ - if (t->c_cflag & CSIZE) { - switch (t->c_cflag & CSIZE) { - default: break; - case CS5: m340_uart_config[minor].bits_per_char = m340_5bpc; break; - case CS6: m340_uart_config[minor].bits_per_char = m340_6bpc; break; - case CS7: m340_uart_config[minor].bits_per_char = m340_7bpc; break; - case CS8: m340_uart_config[minor].bits_per_char = m340_8bpc; break; - } - } - - /* if serial module configuration has been changed */ - if (t->c_cflag & (CSIZE | PARENB)) { - rtems_interrupt_disable(level); - /* reinit the UART */ - dbugInitialise(); - rtems_interrupt_enable (level); - } - - return 0; -} - -/****************************************************** - Name: console_initialize - Input parameters: MAJOR # of console_driver, - minor is always 0, - args are always NULL - Output parameters: - - Description: Reserve resources consumed by this driver - TODO: We should pass m340_uart_config table in arg - *****************************************************/ -rtems_device_driver console_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - rtems_status_code status; - int i; - - /* - * Set up TERMIOS - */ - rtems_termios_initialize (); - - /* - * Do device-specific initialization - */ - Init_UART_Table(); - dbugInitialise (); - Fifo_Full_benchmark_timer_initialize(); - - /* - * Register the devices - */ - for (i=0; iiop->data1; - } - else { - sc |= rtems_termios_open (major, minor, arg, &pollCallbacks); - } - } - - else if (minor==UART_CHANNEL_B) { - if (USE_INTERRUPTS_B) { - rtems_libio_open_close_args_t *args = arg; - - sc |= rtems_termios_open (major, minor, arg, &intrCallbacks); - ttypB = args->iop->data1; - } - else { - sc |= rtems_termios_open (major, minor, arg, &pollCallbacks); - } - } - - else return RTEMS_INVALID_NUMBER; - - return sc; -} - -/****************************************************** - Name: console_close - Input parameters: channel #, termios args - Output parameters: - - Description: close the device - *****************************************************/ -rtems_device_driver console_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_termios_close (arg); -} - -/****************************************************** - Name: console_read - Input parameters: channel #, termios args - Output parameters: - - Description: read the device - *****************************************************/ -rtems_device_driver console_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_termios_read (arg); -} - -/****************************************************** - Name: console_write - Input parameters: channel #, termios args - Output parameters: - - Description: write to the device - *****************************************************/ -rtems_device_driver console_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_termios_write (arg); -} - -/****************************************************** - Name: console_control - Input parameters: channel #, termios args - Output parameters: - - Description: Handle ioctl request - *****************************************************/ -rtems_device_driver console_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_libio_ioctl_args_t *args = arg; - - if (args->command == TIOCSETA) - SetAttributes (minor, (struct termios *)args->buffer); - - return rtems_termios_ioctl (arg); -} diff --git a/bsps/m68k/gen68340/console/m340uart.c b/bsps/m68k/gen68340/console/m340uart.c deleted file mode 100644 index d8207ea757..0000000000 --- a/bsps/m68k/gen68340/console/m340uart.c +++ /dev/null @@ -1,330 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * M68340/349 UART management tools - */ - -/* - * Author: - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* this table shows compatible speed configurations for the MC68340: - the first row shows baud rates for baud speed set 1 - the second row shows baud rates for baud speed set 2 - look at Motorola's MC68340 Integrated Processor User's Manual - page 7-30 for more infos */ - -float m340_Baud_Rates_Table[16][2] = { - { 50, 75 }, - { 110, 110 }, - { 134.5, 134.5 }, - { 200, 150 }, - { 300, 300 }, - { 600, 600 }, - { 1200, 1200 }, - { 1050, 2000 }, - { 2400, 2400 }, - { 4800, 4800 }, - { 7200, 1800 }, - { 9600, 9600 }, - { 38400, 19200 }, - { 76800, 38400 }, - { SCLK/16, SCLK/16}, - { SCLK, SCLK }, -}; - -/* config on both 340 channels */ -uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS]; - -/* - * Init UART table - */ - -#define NOT_IMPLEMENTED_YET 0 - -/****************************************************** - Name: Init_UART_Table - Input parameters: - - Output parameters: - - Description: Init the m340_uart_config - THIS SHOULD NOT BE HERE! - Its aim was to let the user configure - UARTs for each application. - As we can't pass args to the console - driver initialisation routine at the - moment, this was not done. - ATTENTION: TERMIOS init presupposes that the channel - baud rates is 9600/9600. - -> risks when using IOCTL - *****************************************************/ -void Init_UART_Table(void) -{ - m340_uart_config[UART_CHANNEL_A].enable = TRUE; - strcpy(m340_uart_config[UART_CHANNEL_A].name, UART_CONSOLE_NAME); - m340_uart_config[UART_CHANNEL_A].parity_mode = m340_No_Parity; - m340_uart_config[UART_CHANNEL_A].bits_per_char = m340_8bpc; - m340_uart_config[UART_CHANNEL_A].rx_baudrate = 9600; - m340_uart_config[UART_CHANNEL_A].tx_baudrate = 9600; - m340_uart_config[UART_CHANNEL_A].rx_mode = UART_CRR; - m340_uart_config[UART_CHANNEL_A].mode = UART_POLLING; - - m340_uart_config[UART_CHANNEL_A].termios.enable = TRUE; - m340_uart_config[UART_CHANNEL_A].termios.rx_buffer_size = NOT_IMPLEMENTED_YET; - m340_uart_config[UART_CHANNEL_A].termios.tx_buffer_size = NOT_IMPLEMENTED_YET; - - m340_uart_config[UART_CHANNEL_B].enable = FALSE; - strcpy(m340_uart_config[UART_CHANNEL_B].name, UART_RAW_IO_NAME); - m340_uart_config[UART_CHANNEL_B].parity_mode = m340_No_Parity; - m340_uart_config[UART_CHANNEL_B].bits_per_char = m340_8bpc; - m340_uart_config[UART_CHANNEL_B].rx_baudrate = 38400; - m340_uart_config[UART_CHANNEL_B].tx_baudrate = 38400; - m340_uart_config[UART_CHANNEL_B].rx_mode = UART_CRR; - m340_uart_config[UART_CHANNEL_B].mode = UART_INTERRUPTS; - - m340_uart_config[UART_CHANNEL_B].termios.enable = TRUE; - m340_uart_config[UART_CHANNEL_B].termios.rx_buffer_size = NOT_IMPLEMENTED_YET; - m340_uart_config[UART_CHANNEL_B].termios.tx_buffer_size = NOT_IMPLEMENTED_YET; -} - -/****************************************************** - Name: Find_Right_m340_UART_Channel_Config - Input parameters: Send/Receive baud rates for a - given channel - Output parameters: UART compatible configs for this - channel - Description: returns which uart configurations fit - Receiver Baud Rate and Transmitter Baud - Rate for a given channel - For instance, according to the - m340_Baud_Rates_Table: - - Output Speed = 50, Input Speed = 75 - is not a correct config, because - 50 bauds implies set 1 and 75 bauds - implies set 2 - - Output Speed = 9600, Input Speed = 9600 - two correct configs for this: - RCS=11, TCS=11, Set=1 or 2 - *****************************************************/ -static t_baud_speed_table -Find_Right_m340_UART_Channel_Config( - float ReceiverBaudRate, - float TransmitterBaudRate -) -{ - t_baud_speed_table return_value; - int i,j; - - struct { - int cs; - int set; - } Receiver[2], Transmitter[2]; - - int Receiver_nb_of_config = 0; - int Transmitter_nb_of_config = 0; - - /* Receiver and Transmitter baud rates must be compatible, ie in the - * same set. - */ - - /* search for configurations for ReceiverBaudRate - * there can't be more than two (only two sets). - */ - for (i=0;i<16;i++) { - for (j=0;j<2;j++) { - if (m340_Baud_Rates_Table[i][j]==ReceiverBaudRate) { - Receiver[Receiver_nb_of_config].cs=i; - Receiver[Receiver_nb_of_config].set=j; - Receiver_nb_of_config++; - } - } - } - - /* search for configurations for TransmitterBaudRate - * there can't be more than two (only two sets) - */ - for (i=0;i<16;i++) { - for (j=0;j<2;j++) { - if (m340_Baud_Rates_Table[i][j]==TransmitterBaudRate) { - Transmitter[Transmitter_nb_of_config].cs=i; - Transmitter[Transmitter_nb_of_config].set=j; - Transmitter_nb_of_config++; - } - } - } - - /* now check if there's a compatible config */ - return_value.nb=0; - - for (i=0; i -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -/* Structures */ - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Methods used across files inside the BSP - */ -int dbug_in_char( int minor ); -void dbug_out_char( int minor, int ch ); -int dbug_char_present( int minor ); -void _dbug_dumpanic(void); - -/* - * Only called from .S but prototyped here to capture the dependecy. - */ -void _Init68340 (void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/** @} */ - -#endif diff --git a/bsps/m68k/gen68340/include/bsp/irq.h b/bsps/m68k/gen68340/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/m68k/gen68340/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/m68k/gen68340/include/m340timer.h b/bsps/m68k/gen68340/include/m340timer.h deleted file mode 100644 index 2c3d00e818..0000000000 --- a/bsps/m68k/gen68340/include/m340timer.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup m68k_gen68340 - * - * @brief Time driver definitions. - */ - -/* - * Header file for timer driver - * defines for accessing M68340 timer registers - * - * Author: - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __m340timer_H__ -#define __m340timer_H__ - -extern void Fifo_Full_benchmark_timer_initialize (void); - -extern void (*Restart_Fifo_Full_A_Timer)(void); -extern void (*Restart_Check_A_Timer)(void); -extern void (*Restart_Fifo_Full_B_Timer)(void); -extern void (*Restart_Check_B_Timer)(void); - -/* CR */ -#define m340_SWR (1<<15) -#define m340_Polling_Mode (0<<12) -#define m340_TC_Enabled (1<<12) -#define m340_TG_Enabled (2<<12) -#define m340_TG_TC_Enabled (3<<12) -#define m340_TO_Enabled (4<<12) -#define m340_TO_TC_Enabled (5<<12) -#define m340_TG_TG_Enabled (6<<12) -#define m340_TO_TG_TG_Enabled (7<<12) -#define m340_TGE (1<<11) -#define m340_PSE (1<<10) -#define m340_CPE (1<<9) -#define m340_CLK (1<<8) -#define m340_Divide_by_2 (1<<5) -#define m340_Divide_by_4 (2<<5) -#define m340_Divide_by_8 (3<<5) -#define m340_Divide_by_16 (4<<5) -#define m340_Divide_by_32 (5<<5) -#define m340_Divide_by_64 (6<<5) -#define m340_Divide_by_128 (7<<5) -#define m340_Divide_by_256 (0<<5) -#define m340_ICOC (0<<2) -#define m340_SWG (1<<2) -#define m340_VDCSWG (2<<2) -#define m340_VWSSPG (3<<2) -#define m340_PWM (4<<2) -#define m340_PM (5<<2) -#define m340_EC (6<<2) -#define m340_TB (7<<2) -#define m340_Disabled 0 -#define m340_Toggle_Mode 1 -#define m340_Zero_Mode 2 -#define m340_One_Mode 3 - -/* SR */ -#define m340_IRQ (1<<15) -#define m340_TO (1<<14) -#define m340_TG (1<<13) -#define m340_TC (1<<12) -#define m340_TGL (1<<11) -#define m340_ON (1<<10) -#define m340_OUT (1<<9) -#define m340_COM (1<<8) - -#endif diff --git a/bsps/m68k/gen68340/include/m340uart.h b/bsps/m68k/gen68340/include/m340uart.h deleted file mode 100644 index c7991089ab..0000000000 --- a/bsps/m68k/gen68340/include/m340uart.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup m68k_gen68340 - * - * @brief UART console driver definitions. - */ - -/* - * Header file for console driver - * defines for accessing M68340/68349 UART registers - * - * Author: - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __m340uart_H__ -#define __m340uart_H__ - -#include - -/* UART initialisation */ -#define UART_CHANNEL_A 0 -#define UART_CHANNEL_B 1 -#define UART_NUMBER_OF_CHANNELS 2 -#define UART_CONSOLE_NAME "/dev/console" -#define UART_RAW_IO_NAME "/dev/tty1" -#define UART_FIFO_FULL 0 -#define UART_CRR 1 -#define UART_INTERRUPTS 0 -#define UART_POLLING 1 -#define UART_TERMIOS_CONSOLE 0 -#define UART_TERMIOS_RAW 1 -#define UART_TERMIOS_MIN_DEFAULT 1 -#define UART_TERMIOS_TIME_DEFAULT 0 - -void Init_UART_Table(void); - -typedef struct { - uint8_t enable; - uint16_t rx_buffer_size; /* NOT IMPLEMENTED */ - uint16_t tx_buffer_size; /* NOT IMPLEMENTED */ - } uart_termios_config; - -typedef struct { /* for one channel */ - uint8_t enable; /* use this channel */ - char name[64]; /* use UART_CONSOLE_NAME for console purpose */ - uint8_t parity_mode; /* parity mode, see MR1 section for defines */ - uint8_t bits_per_char; /* bits per character, see MR1 section for defines */ - float rx_baudrate; /* Rx baudrate */ - float tx_baudrate; /* Tx baudrate */ - uint8_t rx_mode; /* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */ - uint8_t mode; /* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */ - uart_termios_config termios; - } uart_channel_config; - -extern uart_channel_config m340_uart_config[UART_NUMBER_OF_CHANNELS]; - -typedef struct { - int set; /* number of the m340 baud speed set */ - int rcs; /* RCS for the needed baud set */ - int tcs; /* TCS for the needed baud set */ - } t_baud_speed; - -typedef struct { - t_baud_speed baud_speed_table[2]; - short nb; - } t_baud_speed_table; - -extern t_baud_speed_table -Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, uint8_t enableA, - float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, uint8_t enableB); - -extern rtems_isr InterruptHandler (rtems_vector_number v); - -extern int dbugRead (int minor); -extern ssize_t dbugWrite (int minor, const char *buf, size_t len); - -extern float m340_Baud_Rates_Table[16][2]; - -/* SR */ -#define m340_Rx_RDY 1 -#define m340_FFULL (1<<1) -#define m340_Tx_RDY (1<<2) -#define m340_TxEMP (1<<3) -#define m340_OE (1<<4) -#define m340_PE (1<<5) -#define m340_FE (1<<6) -#define m340_RB (1<<7) - -/* IER */ -#define m340_TxRDYA 1 -#define m340_RxRDYA (1<<1) -#define m340_TxRxRDYA 0x3 -#define m340_TxRDYB (1<<4) -#define m340_RxRDYB (1<<5) -#define m340_TxRxRDYB 0x30 - -/* CR */ -#define m340_Reset_Error_Status 0x40 -#define m340_Reset_Receiver 0x20 -#define m340_Reset_Transmitter 0x30 -#define m340_Transmitter_Enable (1<<2) -#define m340_Receiver_Enable 1 -#define m340_Transmitter_Disable (2<<2) -#define m340_Receiver_Disable 2 - -/* ACR */ -#define m340_BRG_Set1 0 -#define m340_BRG_Set2 (1<<7) - -/* OPCR */ -#define m340_OPCR_Gal 0x0 -#define m340_OPCR_Aux 0xFF - -/* ISR */ -#define m340_COS (1<<7) -#define m340_DBB (1<<6) -#define m340_XTAL_RDY (1<<3) -#define m340_DBA (1<<2) - -/* MR1 */ -#define m340_RxRTS (1<<7) -#define m340_R_F (1<<6) /* character or block mode */ -#define m340_ERR (1<<5) -#define m340_RxRTX (1<<7) -#define m340_Even_Parity 0 -#define m340_Odd_Parity (1<<2) -#define m340_Low_Parity (2<<2) -#define m340_High_Parity (3<<2) -#define m340_No_Parity (4<<2) -#define m340_Data_Character (6<<2) -#define m340_Address_Character (7<<2) -#define m340_5bpc 0x0 -#define m340_6bpc 0x1 -#define m340_7bpc 0x2 -#define m340_8bpc 0x3 - -/* MR2 */ -#define m340_normal (0<<6) -#define m340_automatic_echo (1<<6) -#define m340_local_loopback (2<<6) -#define m340_remote_loopback (3<<6) -#define m340_TxRTS (1<<5) -#define m340_TxCTS (1<<4) - -/* Baud rates for Transmitter/Receiver */ -#define SCLK 1 /* put your own SCLK value here */ - -#endif diff --git a/bsps/m68k/gen68340/include/m68340.h b/bsps/m68k/gen68340/include/m68340.h deleted file mode 100644 index 37440f3098..0000000000 --- a/bsps/m68k/gen68340/include/m68340.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - * @file - * - * @ingroup m68k_gen68340 - * - * @brief MC68430 definitions. - */ - -/********************************************************************** - * MC68340 C Header File * - * * - * Developed by : Motorola * - * High Performance Embedded Systems Division * - * Austin, TX * - * Rectified by : Geoffroy Montel - * g_montel@yahoo.com * - * * - **********************************************************************/ - -typedef volatile unsigned char * portb; /* 8-bit port */ -typedef volatile unsigned short * portw; /* 16-bit port */ -typedef volatile unsigned int * portl; /* 32-bit port */ - -#define MBASE 0xEFFFF000 /* Module Base Address */ - /* not EFFFF000 due to a 68349 - hardware incompatibility */ - -#define MBAR (*(portb) 0x0003FF00) /* Module Base Addr Reg */ -#define MBAR1 (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */ -#define MBAR2 (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */ - -/* System Integration Module */ - -#define SIMMCR (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg */ -#define SIMSYNCR (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */ -#define SIMAVR (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg */ -#define SIMRSR (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg */ -#define SIMPORTA (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg */ -#define SIMDDRA (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg */ -#define SIMPPRA1 (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */ -#define SIMPPRA2 (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */ -#define SIMPORTB (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg */ -#define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg */ -#define SIMDDRB (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg */ -#define SIMPPARB (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg */ -#define SIMSWIV (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector */ -#define SIMSYPCR (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */ -#define SIMPICR (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */ -#define SIMPITR (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg */ -#define SIMSWSR (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */ - -#define SIMCS0AM (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk */ -#define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */ -#define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */ -#define SIMCS0BA (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr */ -#define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */ -#define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */ -#define SIMCS1AM (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */ -#define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */ -#define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */ -#define SIMCS1BA (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr */ -#define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */ -#define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */ -#define SIMCS2AM (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk */ -#define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */ -#define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */ -#define SIMCS2BA (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr */ -#define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */ -#define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */ -#define SIMCS3AM (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk */ -#define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */ -#define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */ -#define SIMCS3BA (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr */ -#define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */ -#define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */ - -/* Dynamic Memory Access (DMA) Module */ - -#define DMAMCR1 (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1 */ -#define DMAINTR1 (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1 */ -#define DMACCR1 (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1 */ -#define DMACSR1 (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */ -#define DMAFCR1 (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1 */ -#define DMASAR1 (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1 */ -#define DMADAR1 (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1 */ -#define DMABTC1 (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */ - -#define DMAMCR2 (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2 */ -#define DMAINTR2 (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2 */ -#define DMACCR2 (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2 */ -#define DMACSR2 (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */ -#define DMAFCR2 (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1 */ -#define DMASAR2 (*(portl) (MBASE+0x07AC)) /* DMA Source Addr Reg 2 */ -#define DMADAR2 (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2 */ -#define DMABTC2 (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */ - -/* Dual Serial Module */ - -#define DUMCRH (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg */ -#define DUMCRL (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg */ -#define DUILR (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level */ -#define DUIVR (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector */ -#define DUMR1A (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A */ -#define DUSRA (*(portb) (MBASE+0x0711)) /* DUART Status Reg A */ -#define DUCSRA (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A */ -#define DUCRA (*(portb) (MBASE+0x0712)) /* DUART Command Reg A */ -#define DURBA (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A */ -#define DUTBA (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */ -#define DUIPCR (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */ -#define DUACR (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */ -#define DUISR (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */ -#define DUIER (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg */ - -#define DUMR1B (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B */ -#define DUSRB (*(portb) (MBASE+0x0719)) /* DUART Status Reg B */ -#define DUCSRB (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B */ -#define DUCRB (*(portb) (MBASE+0x071A)) /* DUART Command Reg B */ -#define DURBB (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B */ -#define DUTBB (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */ -#define DUIP (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg */ -#define DUOPCR (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg */ -#define DUOPBS (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set */ -#define DUOPBR (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst */ -#define DUMR2A (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A */ -#define DUMR2B (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B */ - -/* Dual Timer Module */ - -#define TMCR1 (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */ -#define TIR1 (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1 */ -#define TCR1 (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1 */ -#define TSR1 (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1 */ -#define TCNTR1 (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1 */ -#define WPREL11 (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1 */ -#define WPREL21 (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1 */ -#define TCOM1 (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1 */ - -#define TMCR2 (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */ -#define TIR2 (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2 */ -#define TCR2 (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2 */ -#define TSR2 (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2 */ -#define TCNTR2 (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2 */ -#define WPREL12 (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2 */ -#define WPREL22 (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2 */ -#define TCOM2 (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2 */ diff --git a/bsps/m68k/gen68340/include/m68340.inc b/bsps/m68k/gen68340/include/m68340.inc deleted file mode 100644 index 5c1ba36799..0000000000 --- a/bsps/m68k/gen68340/include/m68340.inc +++ /dev/null @@ -1,148 +0,0 @@ -/*---------------------------------------------------------------------------- -* file name: M68340.INC JC RAHUEL CNET/DSM/TAM/CAT -* -* MC68340 BCC Board Support Package -* -* date: 1/12/1993 -* -* Copyright 1989, Ready Systems FRANCE -* -* Supports: VRTX32 and RTscope -* -* Related Board: MOTOROLA BCC M68340 -* -* Description: EQUATES FOR 68340 DEVICES -* -* Changes: -* - Geoffroy Montel (g_montel@yahoo.com) : -* changed EQU syntax for GNU as -* -*----------------------------------------------------------------------------*/ - -/************************************************ - * ATTENTION: must match defs. in C header file * - ************************************************/ - -/* -- SIM equates -- system integration module */ -.equ BASE_REG, 0x3FF00 -.equ BASE_SIM, 0xEFFFF000 -.equ SIM_MCR, 0x000 /* module configuration register */ -.equ SIM_SYNCR, 0x004 /* clock synthesizer control register */ -.equ SIM_AVR, 0x006 /* autovector register */ -.equ SIM_RSR, 0x007 /* reset status register */ - -/* -- Port A -- */ -.equ SIM_PORTA, 0x011 /* port A data */ -.equ SIM_DDRA, 0x013 /* port A direction data */ -.equ SIM_PPRA1, 0x015 /* Port A pin assignement 1 */ -.equ SIM_PPRA2, 0x017 /* Port A pin assignement 2 */ - -/* -- Port B -- */ -.equ SIM_PORTB, 0x019 /* port B data */ -.equ SIM_PORTB1, 0x01B /* port B data auxiliary */ -.equ SIM_DDRB, 0x01D /* port B direction data */ -.equ SIM_PPRB, 0x01F /* Port B pin assignement */ -.equ SIM_SWIV, 0x020 /* SW interrupt vector */ -.equ SIM_SYPCR, 0x021 /* System protection control register */ -.equ SIM_PICR, 0x022 /* Periodic interrupt control register */ -.equ SIM_PITR, 0x024 /* Periodic interrupt timing register */ -.equ SIM_SWSR, 0x027 /* Sofware service */ - -/* -- Chip select -- */ -.equ SIM_MASKH0, 0x040 /* mask register CS0 */ -.equ SIM_MASKL0, 0x042 /* mask register CS0 */ -.equ SIM_ADDRH0, 0x044 /* base address CS0 */ -.equ SIM_ADDRL0, 0x046 /* base address CS0 */ -.equ SIM_MASKH1, 0x048 /* mask register CS1 */ -.equ SIM_MASKL1, 0x04A /* mask register CS1 */ -.equ SIM_ADDRH1, 0x04C /* base address CS1 */ -.equ SIM_ADDRL1, 0x04E /* base address CS1 */ -.equ SIM_MASKH2, 0x050 /* mask register CS2 */ -.equ SIM_MASKL2, 0x052 /* mask register CS2 */ -.equ SIM_ADDRH2, 0x054 /* base address CS2 */ -.equ SIM_ADDRL2, 0x056 /* base address CS2 */ -.equ SIM_MASKH3, 0x058 /* mask register CS3 */ -.equ SIM_MASKL3, 0x05A /* mask register CS3 */ -.equ SIM_ADDRH3, 0x05C /* base address CS3 */ -.equ SIM_ADDRL3, 0x05E /* base address CS3 */ - -/* -- TIMERS equates -- */ - -/* __ TIMER 0 */ -.equ TIM_MCR0, 0x600 /* Module configuration register */ -.equ TIM_IR0, 0x604 /* interrupt register */ -.equ TIM_CR0, 0x606 /* controle register */ -.equ TIM_SR0, 0x608 /* Status/prescaler register */ -.equ TIM_CNTR0, 0x60A /* counter register */ -.equ TIM_PREL10, 0x60C /* Preload register 1 */ -.equ TIM_PREL20, 0x60E /* Preload register 2 */ -.equ TIM_COM0, 0x610 /* Compare register */ - -/* __ TIMER 1 */ - -.equ TIM_MCR1, 0x640 /* Module configuration register */ -.equ TIM_IR1, 0x644 /* interrupt register */ -.equ TIM_CR1, 0x646 /* controle register */ -.equ TIM_SR1, 0x648 /* Status/prescaler register */ -.equ TIM_CNTR1, 0x64A /* counter register */ -.equ TIM_PREL11, 0x64C /* Preload register 1 */ -.equ TIM_PREL21, 0x64E /* Preload register 2 */ -.equ TIM_COM1, 0x650 /* Compare register */ - -/* -- U.A.R.T. equates -- */ - -.equ UA_MCRH, 0x700 /* module configuration register */ -.equ UA_MCRL, 0x701 /* module configuration register */ -.equ UA_ILR, 0x704 /* Interrupt level */ -.equ UA_IVR, 0x705 /* Interrupt vector */ -.equ UA_MR1A, 0x710 /* Mode register 1 A */ -.equ UA_MR2A, 0x720 /* Mode register 2 A*/ -.equ UA_CSRA, 0x711 /* Clock_select register A */ -.equ UA_SRA, 0x711 /* status register A */ -.equ UA_CRA, 0x712 /* command register A */ -.equ UA_RBA, 0x713 /* receive buffer A */ -.equ UA_TBA, 0x713 /* transmit buffer A */ -.equ UA_IPCR, 0x714 /* input port change register */ -.equ UA_ACR, 0x714 /* auxiliary control register */ -.equ UA_ISR, 0x715 /* interrupt status register */ -.equ UA_IER, 0x715 /* interrupt enable register */ -.equ UA_MR1B, 0x718 /* Mode register 1 B */ -.equ UA_MR2B, 0x721 /* Mode register 2 B */ -.equ UA_CSRB, 0x719 /* Clock_select register B */ -.equ UA_SRB, 0x719 /* status register B */ -.equ UA_CRB, 0x71A /* command register A */ -.equ UA_RBB, 0x71B /* receive buffer A */ -.equ UA_TBB, 0x71B /* transmit buffer A */ -.equ UA_IP, 0x71D /* Input port register */ -.equ UA_OPCR, 0x71D /* output port control register */ -.equ UA_OPS, 0x71E /* output port bit set */ -.equ UA_OPR, 0x71F /* output port bit reset */ -.equ TX_A_EN, 0x01 /* Tx A irq enable */ -.equ TX_B_EN, 0x10 /* Tx B irq enable */ -.equ TX_A_DIS, 0xFE /* Tx A irq enable */ -.equ TX_B_DIS, 0xEF /* Tx B irq enable */ -.equ TX_AB_DIS, 0x22 - -/* -- DMA equates -- */ -.equ DMA_MCR0, 0x780 /* module configuration register */ -.equ DMA_IR0, 0x784 /* Interrupt register */ -.equ DMA_CCR0, 0x788 /* Channel control register */ -.equ DMA_CSR0, 0x78A /* Channel status register */ -.equ DMA_FCR0, 0x78B /* Function code register */ -.equ DMA_SARH0, 0x78C /* Source adresse register */ -.equ DMA_SARL0, 0x78E /* Source adresse register */ -.equ DMA_DARH0, 0x790 /* destination adresse register */ -.equ DMA_DARL0, 0x792 /* destination adresse register */ -.equ DMA_BTCH0, 0x794 /* byte transfer register */ -.equ DMA_BTCL0, 0x796 /* byte transfer register */ -.equ DMA_MCR1, 0x7A0 /* module configuration register */ -.equ DMA_IR1, 0x7A4 /* Interrupt register */ -.equ DMA_CCR1, 0x7A8 /* Channel control register */ -.equ DMA_CSR1, 0x7AA /* Channel status register */ -.equ DMA_FCR1, 0x7AB /* Function code register */ -.equ DMA_SARH1, 0x7AC /* Source adresse register */ -.equ DMA_SARL1, 0x7AE /* Source adresse register */ -.equ DMA_DARH1, 0x7B0 /* destination adresse register */ -.equ DMA_DARL1, 0x7B2 /* destination adresse register */ -.equ DMA_BTCH1, 0x7B4 /* byte transfer register */ -.equ DMA_BTCL1, 0x7B6 /* byte transfer register */ diff --git a/bsps/m68k/gen68340/include/m68349.inc b/bsps/m68k/gen68340/include/m68349.inc deleted file mode 100644 index 4e3ce53d29..0000000000 --- a/bsps/m68k/gen68340/include/m68349.inc +++ /dev/null @@ -1,410 +0,0 @@ -/*---------------------------------------------------------------------------- - * file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT - * - * MC68349 BCC Board Support Package - * - * date: 31/07/97 - * - * Description: EQUATES FOR 68349 DEVICES - * - * Modifications: - * - adapted for GNU CC by G.Montel 26/05/98 - *----------------------------------------------------------------------------*/ - -| -- SIM equates -- - -.equ BASE_REG, 0x3FF00 -.equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK - -.equ SIM_MCR, 0x000 | module configuration register -.equ SIM_IDR, 0x002 | processor identification register -.equ SIM_SYNCR, 0x004 | clock synthesizer control register -.equ SIM_AVR, 0x006 | autovector register -.equ SIM_RSR, 0x007 | reset status register - -| -- Port A -.equ SIM_PORTA, 0x011 | port A data -.equ SIM_DDRA, 0x013 | port A direction data -.equ SIM_PPRA1, 0x015 | Port A pin assignement 1 -.equ SIM_PPRA2, 0x017 | Port A pin assignement 2 - -| -- Port B -.equ SIM_PORTB, 0x019 | port B data -.equ SIM_PORTB1, 0x01B | port B data auxiliary -.equ SIM_DDRB, 0x01D | port B direction data -.equ SIM_PPRB, 0x01F | Port B pin assignement - -.equ SIM_SWIV, 0x020 | SW interrupt vector -.equ SIM_SYPCR, 0x021 | System protection control register -.equ SIM_PICR, 0x022 | Periodic interrupt control register -.equ SIM_PITR, 0x024 | Periodic interrupt timing register -.equ SIM_SWSR, 0x027 | Sofware service - -| -- Chip select -.equ SIM_MASKH0, 0x040 | mask register CS0 -.equ SIM_MASKL0, 0x042 | mask register CS0 -.equ SIM_ADDRH0, 0x044 | base address CS0 -.equ SIM_ADDRL0, 0x046 | base address CS0 - -.equ SIM_MASKH1, 0x048 | mask register CS1 -.equ SIM_MASKL1, 0x04A | mask register CS1 -.equ SIM_ADDRH1, 0x04C | base address CS1 -.equ SIM_ADDRL1, 0x04E | base address CS1 - -.equ SIM_MASKH2, 0x050 | mask register CS2 -.equ SIM_MASKL2, 0x052 | mask register CS2 -.equ SIM_ADDRH2, 0x054 | base address CS2 -.equ SIM_ADDRL2, 0x056 | base address CS2 - -.equ SIM_MASKH3, 0x058 | mask register CS3 -.equ SIM_MASKL3, 0x05A | mask register CS3 -.equ SIM_ADDRH3, 0x05C | base address CS3 -.equ SIM_ADDRL3, 0x05E | base address CS3 - -| -- TIMERS equates -- - -| __ TIMER 0 - -.equ TIM_MCR0, 0x600 | Module configuration register -.equ TIM_IR0, 0x604 | interrupt register -.equ TIM_CR0, 0x606 | controle register -.equ TIM_SR0, 0x608 | Status/prescaler register -.equ TIM_CNTR0, 0x60A | counter register -.equ TIM_PREL10, 0x60C | Preload register 1 -.equ TIM_PREL20, 0x60E | Preload register 2 -.equ TIM_COM0, 0x610 | Compare register - -| __ TIMER 1 - -.equ TIM_MCR1, 0x640 | Module configuration register -.equ TIM_IR1, 0x644 | interrupt register -.equ TIM_CR1, 0x646 | controle register -.equ TIM_SR1, 0x648 | Status/prescaler register -.equ TIM_CNTR1, 0x64A | counter register -.equ TIM_PREL11, 0x64C | Preload register 1 -.equ TIM_PREL21, 0x64E | Preload register 2 -.equ TIM_COM1, 0x650 | Compare register - -| -- U.A.R.T. equates -- - -.equ UA_MCRH, 0x700 | module configuration register -.equ UA_MCRL, 0x701 | module configuration register -.equ UA_ILR, 0x704 | Interrupt level -.equ UA_IVR, 0x705 | Interrupt vector - -.equ UA_MR1A, 0x710 | Mode register 1 A -.equ UA_MR2A, 0x720 | Mode register 2 A -.equ UA_CSRA, 0x711 | Clock_select regiter A -.equ UA_SRA, 0x711 | status register A -.equ UA_CRA, 0x712 | command register A -.equ UA_RBA, 0x713 | receive buffer A -.equ UA_TBA, 0x713 | transmit buffer A - -.equ UA_IPCR, 0x714 | input port change register -.equ UA_ACR, 0x714 | auxiliary control register -.equ UA_ISR, 0x715 | interrupt status register -.equ UA_IER, 0x715 | interrupt enable register - -.equ UA_MR1B, 0x718 | Mode register 1 B -.equ UA_MR2B, 0x721 | Mode register 2 B -.equ UA_CSRB, 0x719 | Clock_select regiter B -.equ UA_SRB, 0x719 | status register B -.equ UA_CRB, 0x71A | command register A -.equ UA_RBB, 0x71B | receive buffer A -.equ UA_TBB, 0x71B | transmit buffer A - -.equ UA_IP, 0x71D | Input port register -.equ UA_OPCR, 0x71D | output port control register -.equ UA_OPS, 0x71E | output port bit set -.equ UA_OPR, 0x71F | output port bit reset -.equ TX_A_EN, 0x01 | Tx A irq enable -.equ TX_B_EN, 0x10 | Tx B irq enable -.equ TX_A_DIS, 0xFE | Tx A irq enable -.equ TX_B_DIS, 0xEF | Tx B irq enable -.equ TX_AB_DIS, 0x22 - - -| -- DMA equates -.equ DMA_MCR0, 0x780 | module configuration register -.equ DMA_IR0, 0x784 | Interrupt register -.equ DMA_CCR0, 0x788 | Channel control register -.equ DMA_CSR0, 0x78A | Channel status register -.equ DMA_FCR0, 0x78B | Function code register -.equ DMA_SARH0, 0x78C | Source adresse register -.equ DMA_SARL0, 0x78E | Source adresse register -.equ DMA_DARH0, 0x790 | destination adresse register -.equ DMA_DARL0, 0x792 | destination adresse register -.equ DMA_BTCH0, 0x794 | byte transfer register -.equ DMA_BTCL0, 0x796 | byte transfer register - -.equ DMA_MCR1, 0x7A0 | module configuration register -.equ DMA_IR1, 0x7A4 | Interrupt register -.equ DMA_CCR1, 0x7A8 | Channel control register -.equ DMA_CSR1, 0x7AA | Channel status register -.equ DMA_FCR1, 0x7AB | Function code register -.equ DMA_SARH1, 0x7AC | Source adresse register -.equ DMA_SARL1, 0x7AE | Source adresse register -.equ DMA_DARH1, 0x7B0 | destination adresse register -.equ DMA_DARL1, 0x7B2 | destination adresse register -.equ DMA_BTCH1, 0x7B4 | byte transfer register -.equ DMA_BTCL1, 0x7B6 | byte transfer register - -| -- cache equates -.equ CACHE_MCR, 0xFC0 | cache config reg. (long) - -| -- quad data memory module (QDMM) equates -.equ QDMM_MCR, 0xC00 | QDMM config reg (long) -.equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long) -.equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long) -.equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long) -.equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long) - - - -|----------------------------------------------------- -| AST68349 internal registers -|----------------------------------------------------- -.equ EPLD_SPACE, 3 | "reserved user" space -.equ CPU_SPACE, 7 | "CPU" space - -|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| -| GLUE EPLD -|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| - -.equ GLUE_EPLD, 0xB0000000 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| configuration of /CS0 : -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |ena|val|wid| ws|b31|b30|b29|b28| -| +---+---+---+---+---+---+---+---+ -| -| b[31..28] : base address for decoding /CS[3..0] -| the decoding is as follow : -| -| +----------+------------+------+ -| | a[31..28] | a[27..26] | /CS | -| +-----------+-----------+------+ -| | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes -| | b[31..28] | 01 | /CS1 | -| | b[31..28] | 10 | /CS2 | -| | b[31..28] | 11 | /CS3 | -| +-----------------------+------+ -| -| after /RESET, /CS0 is validated for every cycle, until programmed -| -| ws : number of wait-states : 0 => 0 ws -| 1 => external /dsackx -| wid : width of chip-select : 0 => 16 bits -| 1 => 32 bits -| ena : enable chip-select : 0 => disabled -| 1 => enabled -| -| val : automatic validation. set after reset -| cleared when /CS0 is configured -| -.equ REG_CS0, 0 - - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| configuration of /CS1 to /CS3: -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |ena| x |wid| ws| x | x | x | x | -| +---+---+---+---+---+---+---+---+ -| -| ws : number of wait-states : 0 => 0 ws -| 1 => external /dsackx -| wid : width of chip-select : 0 => 16 bits -| 1 => 32 bits -| ena : enable chip-select : 0 => disabled -| 1 => enabled -.equ REG_CS1, 1 -.equ REG_CS2, 2 -.equ REG_CS3, 3 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| I2C register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+----+ -| | x | x | x | x | x | x |clk|data| -| +---+---+---+---+---+---+---+----+ -| bidirecionnal pin, open drain output. -| set bit to 1 to read external state of pin -| -.equ REG_I2C, 4 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| PDCS register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |s12|s11|s14|pd5|pd4|pd3|pd2|pd1| -| +---+---+---+---+---+---+---+---+ -| pd[5..1] : value read on the DRAM module -| S12, S11 and S14 : "user reserved" configuration switch -| -.equ REG_PDCS, 5 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| timer1 register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |ena| x | x | x | x | x | d1| d0| -| +---+---+---+---+---+---+---+---+ -| -| the timer clock is the 1000Hz clock of the ASTECC platform -| the timer is reloaded on each write to the register, or if the input -| TIN1 is set to 0. -| on overflow, the open drain output TOUT1 is set to 0 -| the timer must be disabled to return TOUT1 to the inactive state -| -.equ REG_TIMER1, 6 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| timer2 register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |ena| x | x | x | x | x | d1| d0| -| +---+---+---+---+---+---+---+---+ -| the timer clock is the 1000Hz clock of the ASTECC platform -| the timer is reloaded on each write to the register, or if the input -| TIN2 is set to 0. -| on overflow, the open drain output TOUT2 is set to 0 -| the timer must be disabled to return TOUT2 to the inactive state -| -.equ REG_TIMER2, 7 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| baudrate generator register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| | x | x | x | x | x | d2| d1| d0| -| +---+---+---+---+---+---+---+---+ -| -| d[2..0] : divider of a 3.6864 Mhz clock -| -| d[2..0] : 0 1 2 3 4 5 6 7 -| divides by : 2 4 6 8 10 12 14 16 -| SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304 -| baudrate : 115200 57600 38400 28800 x 19200 x 14400 -| -.equ REG_BAUDRATE, 8 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| IO register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| | x | x | x |io4|io3|io2|io1|io0| -| +---+---+---+---+---+---+---+---+ -| -| io[4..0] : data written to port -| -| maximum current load is about 5 mA per pin -| -.equ REG_IO, 9 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| IO port -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| | x | x | x |io4|io3|io2|io1|io0| -| +---+---+---+---+---+---+---+---+ -| -| io[4..0] : data read from port -| -.equ REG_IO_PORT, 10 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| IO direction register -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| | x | x | x | x | x |dr2|dr1|dr0| -| +---+---+---+---+---+---+---+---+ -| -| dr0 : 0 => io port 0 is configured as input (default after /RESET) -| 1 => io port 0 is configured as output -| -| dr1 : 0 => io port 1 is configured as input (default after /RESET) -| 1 => io port 1 is configured as output -| -| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET) -| 1 => io ports 2 to 4 are configured as output -| -.equ REG_DIR_IO, 11 - - - - -|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| -| DRAM EPLD -|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| - -.equ DRAM_EPLD, 0xA0000000 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| number of wait-state for DRAM -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| | x | x | x | x | x | x |ws1|ws0| -| +---+---+---+---+---+---+---+---+ -| -| ws[1..0] : 0 1 2 3 -| wait states : 0 1 2 3 -| -.equ REG_WS, 0 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| configuration of refresh for DRAM -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |ena| x | x | x | x | x |rf1|rf0| -| +---+---+---+---+---+---+---+---+ -| -| rf[1..0] : 0 1 2 3 -| refresh : 5µs 10µs 15µs 20µs -| -| ena == 0 : refresh disabled -| ena == 1 : refresh enabled -| -.equ REG_REFRESH, 1 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| configuration of DRAM module size -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| | x | x | x | x | x |sz2|sz1|sz0| -| +---+---+---+---+---+---+---+---+ -| -| sz[2..0] : 0 1 2 3 4 5 6 7 -| size (Mbytes): 4 8 16 32 64 128 0 0 -| -.equ REG_CONFIG, 2 - -|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| bus width of /CS0 during reset bw[1..0] : 0 1 2 3 -| bus width : 32 16 8 ext. /dsackx -| -| state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) -| : sel == 1 => EPLD chip_selects (/CS[3..0]) -| -| 7 6 5 4 3 2 1 0 -| +---+---+---+---+---+---+---+---+ -| |bw1|bw0| x | x | x | x | x |sel| -| +---+---+---+---+---+---+---+---+ -| -.equ REG_BUSWIDTH, 3 - diff --git a/bsps/m68k/gen68340/include/tm27.h b/bsps/m68k/gen68340/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/m68k/gen68340/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/m68k/gen68340/start/dumpanic.c b/bsps/m68k/gen68340/start/dumpanic.c deleted file mode 100644 index 2569550dd5..0000000000 --- a/bsps/m68k/gen68340/start/dumpanic.c +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * M68340/349 registers and stack dump if an exception is raised - */ - -/* - * Author: - * Pascal Cadic - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -const char *exceptionName[] = { - "INITIAL STACK POINTER", - "INITIAL PROGRAM COUNTER", - "BUS ERROR", - "ADDRESS ERROR", - "ILLEGAL INSTRUCTION", - "DIVISION BY ZERO", - "CHK, CHK2", - "TRAPcc, TRAPv", - "PRIVILEGE VIOLATION", - "TRACE", - "LINE A EMULATOR", - "LINE F EMULATOR", - "HARDWARE BREAK", - "COPROCESSOR PROTOCOL VIOLATION", - "FORMAT ERROR", - "UNINITIALIZED INTERRUPT", - "RESERVED 16", - "RESERVED 17", - "RESERVED 18", - "RESERVED 19", - "RESERVED 20", - "RESERVED 21", - "RESERVED 22", - "RESERVED 23", - "SPURIOUS INTERRUPT", - "LEVEL 1 AUTOVECTOR", - "LEVEL 2 AUTOVECTOR", - "LEVEL 3 AUTOVECTOR", - "LEVEL 4 AUTOVECTOR", - "LEVEL 5 AUTOVECTOR", - "LEVEL 6 AUTOVECTOR", - "LEVEL 7 AUTOVECTOR", - "TRAP 1", - "TRAP 2", - "TRAP 3", - "TRAP 4", - "TRAP 5", - "TRAP 6", - "TRAP 7", - "TRAP 8", - "TRAP 9", - "TRAP 10", - "TRAP 11", - "TRAP 12", - "TRAP 13", - "TRAP 14", - "TRAP 15", - "VECTOR 48", - "VECTOR 49", - "VECTOR 50", - "VECTOR 51", - "VECTOR 52", - "VECTOR 53", - "VECTOR 54", - "VECTOR 55", - "VECTOR 56", - "VECTOR 57", - "VECTOR 58", - "VECTOR 59", - "VECTOR 60", - "VECTOR 61", - "VECTOR 62", - "VECTOR 63", - }; - -typedef struct { - unsigned long pc; - unsigned short sr; - unsigned short format_id; - unsigned long d0, d1, d2, d3, d4, d5, d6, d7; - unsigned long a0, a1, a2, a3, a4, a5, a6, a7; - unsigned long sfc, dfc, vbr; -} boot_panic_registers_t; - -boot_panic_registers_t _boot_panic_registers; - -/****************************************************** - Name: _dbug_dump - Input parameters: sr, pc, stack pointer, - size to display - Output parameters: - - Description: display the supervisor stack - *****************************************************/ -static void _dbug_dump( - unsigned short sr, - void* pc, - unsigned short *stack, - int size -) -{ - int i; - - printk("%x : %x \t%x",0,sr,(unsigned short)(((unsigned)pc)>>16)); - for (i=2; i>2; - frametype = (_boot_panic_registers.format_id&0xF000)>>12; - - printk("\n---------------------------------------------\n"); - if (vector<64) - printk("%s",exceptionName[vector]); - else { - printk("RESERVED USER"); - } - printk(" exception (vector %x, type %x)\n",vector,frametype); - printk("---------------------------------------------\n"); - printk("PC : %p ",pc); - printk("A7 : 0x%lx ",_boot_panic_registers.a7); - printk("SR : 0x%x\n",status); - if (frametype==0x0c) { - printk("\nfaulted address = %p\n",faultedAddr); - } - printk("---------------------------------------------\n"); - printk(" panic regs\n"); - printk("---------------------------------------------\n"); - printk("D[0..3] : %lx \t%lx \t%lx \t%lx\n", - _boot_panic_registers.d0,_boot_panic_registers.d1, - _boot_panic_registers.d2,_boot_panic_registers.d3); - printk("D[4..7] : %lx \t%lx \t%lx \t%lx\n", - _boot_panic_registers.d4,_boot_panic_registers.d5, - _boot_panic_registers.d6,_boot_panic_registers.d7); - printk("A[0..3] : %lx \t%lx \t%lx \t%lx\n", - _boot_panic_registers.a0,_boot_panic_registers.a1, - _boot_panic_registers.a2,_boot_panic_registers.a3); - printk("A[4..7] : %lx \t%lx \t%lx \t%lx\n", - _boot_panic_registers.a4,_boot_panic_registers.a5, - _boot_panic_registers.a6,_boot_panic_registers.a7); - - printk(" SFC : %lx",_boot_panic_registers.sfc); - printk(" DFC : %lx\n",_boot_panic_registers.dfc); - printk(" VBR : %lx\n",_boot_panic_registers.vbr); - printk("---------------------------------------------\n"); - printk(" panic stack\n"); - printk("---------------------------------------------\n"); - _dbug_dump(status, pc, (unsigned short*)stack,64*2); - - printk("---------------------------------------------\n"); - printk("press escape to reboot\n"); - } while ((c=getchark())!=ESCAPE); -} diff --git a/bsps/m68k/gen68340/start/init68340.c b/bsps/m68k/gen68340/start/init68340.c deleted file mode 100644 index ee30f415e9..0000000000 --- a/bsps/m68k/gen68340/start/init68340.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * MC68340/349 support routines - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - */ - -#include -#include - -extern void _CopyDataClearBSSAndStart (void); - -/* - * Initialize MC68340 - */ -void _Init68340 (void) -{ - rtems_isr_entry *vbr; - int i; - - /* - * Copy the exception vector table to system RAM - */ - m68k_get_vbr (vbr); - for (i = 0; i < 256; ++i) - M68Kvec[i] = vbr[i]; - m68k_set_vbr (M68Kvec); - - /* - * Copy data, clear BSS, switch stacks and call main() - */ - _CopyDataClearBSSAndStart (); -} diff --git a/bsps/m68k/gen68340/start/linkcmds b/bsps/m68k/gen68340/start/linkcmds deleted file mode 100644 index 801d08f82e..0000000000 --- a/bsps/m68k/gen68340/start/linkcmds +++ /dev/null @@ -1,254 +0,0 @@ -/* - * This file contains GNU linker directives for a generic MC68340/349 board. - * Variations in hardware type and dynamic memory size can be made - * by overriding some values with linker command-line arguments. - * - * ATTENTION: RAM and ROM placement must accord those in start340.S!! - * (next time I'll use some shared variables :) ) - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - */ - -/* - * Declare some sizes. - */ -RamBase = DEFINED(RamBase) ? RamBase : 0x10000000; -RamSize = DEFINED(RamSize) ? RamSize : 4M; -RamEnd = RamBase + RamSize; -HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0; - -/* - * Declare on-board memory. - * It would be nice if the ram length could be given as - * LENGTH=RamSize, but gld doesn't allow non-constant - * values in the LENGTH expression. - */ -MEMORY { - ram : ORIGIN = 0x10000000, LENGTH = 4M - rom : ORIGIN = 0x01000000, LENGTH = 4M -/* dpram : ORIGIN = 0xFE000000, LENGTH = 8k */ -} - -ENTRY(start) -STARTUP(start.o) - -/* - * Declare low-order three octets of Ethernet address. - */ -ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12; - -/* - * Load objects - */ -SECTIONS { - - /* - * Boot PROM - */ - rom : { - _RomBase = .; - __RomBase = .; - } >rom - - /* - * Dynamic RAM - */ - ram : { - . = .; - } >ram - - /* - * Text, data and bss segments - */ - .text : { - *(.text*) - - /* - * C++ constructors/destructors - */ - *(.gnu.linkonce.t.*) - - /* - * Initialization and finalization code. - * - * Various files can provide initialization and finalization - * functions. crtbegin.o and crtend.o are two instances. The - * body of these functions are in .init and .fini sections. We - * accumulate the bodies here, and prepend function prologues - * from crti.o and function epilogues from crtn.o. crti.o must - * be linked first; crtn.o must be linked last. Because these - * are wildcards, it doesn't matter if the user does not - * actually link against crti.o and crtn.o; the linker won't - * look for a file to match a wildcard. The wildcard also - * means that it doesn't matter which directory crti.o and - * crtn.o are in. - */ - PROVIDE (_init = .); - *crti.o(.init) - *(.init) - *crtn.o(.init) - PROVIDE (_fini = .); - *crti.o(.fini) - *(.fini) - *crtn.o(.fini) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - __start_set_sysctl_set = .; - *(set_sysctl_*); - __stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - /* - * C++ constructors/destructors - * - * gcc uses crtbegin.o to find the start of the constructors - * and destructors so we make sure it is first. Because this - * is a wildcard, it doesn't matter if the user does not - * actually link against crtbegin.o; the linker won't look for - * a file to match a wildcard. The wildcard also means that - * it doesn't matter which directory crtbegin.o is in. The - * constructor and destructor list are terminated in - * crtend.o. The same comments apply to it. - */ - . = ALIGN (16); - *crtbegin.o(.ctors) - *(.ctors) - *crtend.o(.ctors) - *crtbegin.o(.dtors) - *(.dtors) - *crtend.o(.dtors) - - /* - * Exception frame info - */ - . = ALIGN (16); - *(.eh_frame) - - /* - * Read-only data - */ - . = ALIGN (16); - _rodata_start = . ; - *(.rodata*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - - . = ALIGN (16); - PROVIDE (_etext = .); - } >ram - - .tdata : { - _TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - _TLS_Data_end = .; - } >ram - - .tbss : { - _TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - _TLS_BSS_end = .; - } >ram - - _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; - _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; - _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; - _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; - _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; - _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .data : { - PROVIDE (_copy_start = .); - *(.data*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gnu.linkonce.d*) - *(.gcc_except_table*) - *(.jcr) - . = ALIGN (16); - PROVIDE (_edata = .); - PROVIDE (_copy_end = .); - } >ram - .bss : { - M68Kvec = .; - . += (256 * 4); - _clear_start = .; - *(.dynbss) - *(.bss* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (16); - PROVIDE (end = .); - _clear_end = .; - } >ram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } >ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - WorkAreaBase = .; - } >ram - - /* - * On-chip memory/peripherals - * - */ - dpram : { - m340 = .; - _m340 = .; - . += (8 * 1024); - } >ram - - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} diff --git a/bsps/m68k/gen68340/start/start.S b/bsps/m68k/gen68340/start/start.S deleted file mode 100644 index 94d9ee0a36..0000000000 --- a/bsps/m68k/gen68340/start/start.S +++ /dev/null @@ -1,896 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - */ - -#include -#include - -#include /* to indicate dependencies */ - -/* old addresses for AST68340 only, undefine for AST68349 */ -#define _OLD_ASTECC 1 - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - 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.long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - move.w (a7),_boot_panic_registers+4 | SR - move.l 2(a7),_boot_panic_registers | PC - move.w 6(a7),_boot_panic_registers+6 | format & vector - movem.l d0-d7/a0-a7, _boot_panic_registers+8 - movec sfc, d0 - movem.l d0, _boot_panic_registers+72 - movec dfc, d0 - movem.l d0, _boot_panic_registers+76 - movec vbr, d0 - movem.l d0, _boot_panic_registers+80 - jmp SYM(_dbug_dumpanic) - bra.s _crt0_cold_start - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -BEGIN_DATA - -/* equates */ - -.equ _CPU340, 0x0 -.equ _CPU349, 0x31 - -#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ -.equ _EPLD_CS_BASE, 0x1 -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x10000000 /* SRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ - -#else /* new addresses for AST68349 and 68340 */ - -.equ _EPLD_CS_BASE, 0x5 -.equ _PROM_Start, 0x50000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x80000000 /* DRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ -#endif - -.equ _SPEED349, 0xD680 /* 24 Mhz */ -.equ _SPEED340, 0xD700 /* 25 Mhz */ -/* .equ _SPEED340, 0xCE00 16 Mhz */ - -#define crt0_boot_type d0 /* cold/warm start (must be D0) */ -#define crt0_temp d1 -#define crt0_cpu_type d2 -#define crt0_csswitch d3 -#define crt0_buswidth d4 -#define crt0_pdcs d5 -#define crt0_spare6 d6 -#define crt0_spare7 d7 -#define crt0_sim_base a0 -#define crt0_glue a1 -#define crt0_dram a2 -#define crt0_ptr3 a3 -#define crt0_ptr4 a4 -#define crt0_ptr5 a5 -#define crt0_ptr6 a6 - -/* -- PDCS buffer equates -- */ -.equ pdcs_mask, 0x1F /* DRAM configuration */ -.equ pdcs_sw12, 7 /* switch 12 */ -.equ pdcs_sw11, 6 /* switch 11 */ -.equ pdcs_sw14, 5 /* switch 14 */ - -.equ bit_cache, pdcs_sw12 /* enable cache if on */ -.equ bit_meminit, pdcs_sw11 /* init memory if on */ - -/* -- Initialization stack and vars -- */ - -/* When using DWARF, everything must be a multiple of 16-bits. */ -#if 1 -_AsteccBusWidth: ds.w 0x0101 -_AsteccCsSwitch: ds.w 0x0101 -#else -_AsteccBusWidth: ds.b 1 -_AsteccCsSwitch: ds.b 1 -#endif -_AsteccCpuName: ds.l 1 - -.align 4 - -_crt0_init_stack: - ds.l 500 -_crt0_init_stktop: - -/* -- Initialization code -- */ -BEGIN_CODE - -.align 4 - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - -/* When using DWARF, everything must be a multiple of 16-bits. */ - .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards " - .text - dc.w 0 -.align 4 - -.globl start -start: - -_crt0_cold_start: - moveq.l #0,crt0_boot_type | signal cold reset - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,crt0_boot_type | signal warm reset - -_crt0_common_start: - move.w #0x2700,sr | disable interrupts and switch to interrupt mode - movea.l #_crt0_init_stktop,sp | set up initialization stack - - move.l #Entry,crt0_temp | VBR initialization - movec.l crt0_temp,vbr | - moveq.l #0x07,crt0_temp - movec.l crt0_temp,dfc | prepare access in CPU space - move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES - moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) - - movea.l #BASE_SIM,crt0_sim_base - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(crt0_sim_base) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(crt0_sim_base) - - /* -- enable /IRQ3, 5, 6, 7 -- */ - move.b #0xE8,SIM_PPRB(crt0_sim_base) - - /* -- enable autovector on /IRQ7 -- */ - move.b #0x80,SIM_AVR(crt0_sim_base) - - /* -- test CPU type -- */ - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne cpu_is_68340 - -/*-------------------------------------------------------------------------------------------*/ -cpu_is_68349: - - /* -- set cpu clock -- */ - move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock - -sync_wait349: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait349 - - /* to allow access to the EPLD internal registers, it is necessary - to disable the global chip-select /CS0 (which decodes every external - cycles). To do that, we initialize the 68349 internal RAM, - copy a part of the initialization code in it, and jump there. - from that moment, /CS0 is not used, therefore it can be initialized - with its default value. Its width may be incorrect, but it will be - adjusted later. The goal is to avoid any conflict with - the accesses to the EPLD registers. - When this is done, we read the RESET parameters (boot prom width - and chip-select switch) and proceed with the initialization - when all is done, we jump back to the boot prom now - decoded with a properly configured /CS0 */ - - /*-------------------------------------*/ - /* -- configure internal SRAM banks -- */ - - move.l #0x00000000,QDMM_MCR(crt0_sim_base) - move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) - move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) - move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) - move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) - - /*--------------------------------------------------------*/ - /* -- copy to address of the 68349 initialization code -- */ - - lea.l _copy_start_code(%pc),crt0_ptr3 - lea.l _copy_end_code(%pc),crt0_ptr4 - move.l crt0_ptr4,crt0_temp - sub.l crt0_ptr3,crt0_temp - add.l #3,crt0_temp | adjust to next long word - lsr.l #2,crt0_temp - - move.l #_FastRam_Start,crt0_ptr4 -_copy_loop: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - subq.l #1,crt0_temp - bne.s _copy_loop - bra.l _FastRam_Start | jump to code in internal RAM - - /*------------------------------------*/ - /* -- start of initialization code -- */ - -_copy_start_code: - bra.l _begin_68349_init - - /*----------------------------------------------------------*/ - /* Astecc 68349 board : chip-select initialization values */ - -_table_csepld: -/* When using DWARF, everything must be a multiple of 16-bits. */ -#if 1 - dc.w (((_EPLD_CS_BASE&0x0F)+0x80) << 8) | 0x80 | 16 bits, 0ws - dc.w 0x9090 | 16 bits, ext /dsack - -#else - dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws - dc.b 0x80 | 16 bits, 0 ws - dc.b 0x90 | 16 bits, ext /dsack - dc.b 0x90 | 16 bits, ext /dsack -#endif - -_table_cs349: - dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) - dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 - dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) - dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 - dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) - dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 - dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) - dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 - - /*-------------------------------------------------*/ -_begin_68349_init: - - /*-------------------------------------------------*/ - /* 68349 chip select initialization - - at this stage, the width of /CS0 may be incorrect - it will be corrected later - */ - -_cs68349_init: - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - - moveq.l #0x07,crt0_temp -_cs349_init2: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - dbra crt0_temp,_cs349_init2 - - /*-----------------------------------------------*/ - /* -- prepare access to the internal registers --*/ - moveq.l #EPLD_SPACE,crt0_temp - movec.l crt0_temp,dfc - movec.l crt0_temp,sfc - move.l #GLUE_EPLD,crt0_glue - move.l #DRAM_EPLD,crt0_dram - - /*-------------------------------------------*/ - /* EPLD generated /CS[3..0] must be disabled */ - -_csepld_clear: - move.l crt0_glue,crt0_ptr4 - move.w #3,crt0_spare6 - clr.b crt0_temp - -_csepld_clear1: - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld_clear1 - - /*---------------------------------------------------------*/ - /* -- get width of boot PROM, and active chip-select set --*/ - moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch - move.b crt0_csswitch,crt0_buswidth - - /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) - : sel == 1 => EPLD chip_selects (/CS[3..0]) */ - and.b #1,crt0_csswitch - - /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 - bus width : 32 16 8 ext./dsackx */ - rol.b #2,crt0_buswidth - and.b #3,crt0_buswidth - - /*----------------------------------------------------*/ - /* -- configure chip select 0 with boot prom width -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - move.l (crt0_ptr3)+,crt0_temp - and.b #0xFC,crt0_temp | clear PS0 & PS1 - or.b crt0_buswidth,crt0_temp | set boot PROM bus width - move.l crt0_temp,(crt0_ptr4)+ - - /*------------------------*/ - /* -- read PDCS buffer -- */ - moves.b REG_PDCS(crt0_glue),crt0_pdcs -/* move.b #0x3F,crt0_pdcs pour test */ - - /*---------------------------------------*/ - /* -- EPLD chip-select initialization -- */ - /*---------------------------------------*/ - btst.b #0,crt0_csswitch - beq _cs_init_end - - /*--------------------------------------------*/ - /* 68349 generated /CS[3..0] must be disabled */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - moveq.l #0x03,crt0_temp -_cs349_clear: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - move.l (crt0_ptr3)+,crt0_spare6 - and.b #0xFE,crt0_spare6 | disable chip-select - move.l crt0_spare6,(crt0_ptr4)+ - dbra crt0_temp,_cs349_clear - - /*---------------------------------------------*/ - /* EPLD generated /CS[3..0] must be configured */ -_csepld_init: - move.l crt0_glue,crt0_ptr4 - lea.l _table_csepld(%pc),crt0_ptr3 - - move.b (crt0_ptr3)+,crt0_temp - or.b #0x20,crt0_temp | default width is 32 bits - tst.b crt0_buswidth | is boot PROM bus width 32 bits ? - beq _csepld1 | if not - and.b #0xDF,crt0_temp | set width to 16 bits -_csepld1: - moves.b crt0_temp,(crt0_ptr4)+ - - moveq.l #0x02,crt0_spare6 -_csepld2: - move.b (crt0_ptr3)+,crt0_temp - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld2 - -_cs_init_end: - - /*--------------------------------------*/ - /* -- DRAM controller initialization -- */ -_dram_init: - move.w #15,crt0_temp - move.l #_ExtRam_Start,crt0_ptr3 - -_dram_init1: - clr.l (crt0_ptr3)+ | must access DRAM - dbra crt0_temp,_dram_init1 | prior to init refresh - -_dram_init2: - move.b #3,crt0_temp - moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states - - move.b #0x81,crt0_temp - moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs - - move.b #0,crt0_temp - moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes - - /*-----------------------*/ - /* -- configure cache -- */ -_init_cache: - move.l #0x000001E0,CACHE_MCR(crt0_sim_base) - btst.b #bit_cache,crt0_pdcs - bne _init_cache_end - or.l #0x00000001,CACHE_MCR(crt0_sim_base) - -_init_cache_end: - - /*-----------------------------*/ - /* -- timers initialization -- */ - - clr.b crt0_temp - moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 - moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 - - /*--------------------------*/ - /* -- I2C initialization -- */ - move.b #3,crt0_temp - moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports - - /*-----------------------------------------*/ - /* -- baudrate generator initialization -- */ - move.b #2,crt0_temp - moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 - - /*-------------------------------*/ - /* -- IO port initialization -- */ - clr.b crt0_temp - moves.b crt0_temp,REG_IO(crt0_glue) | set port as input - - /* -- */ - - move.l #68349,crt0_cpu_type - - /* -- jump back to PROM -- */ - - jmp.l (_fill_test) | must be absolute long - -_copy_end_code: - -/*------------------------------------------------- - initialization code for the 68340 board - -------------------------------------------------*/ - - /* Astecc 68340 board : chip-select initialization values */ -_table_cs340: - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -cpu_is_68340: - - /* -- set cpu clock -- */ - move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock -sync_wait340: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait340 - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs340(%pc),crt0_ptr3 - moveq.l #0x07,crt0_temp -_b_cs340: - move.l (crt0_ptr3)+,crt0_ptr5 - move.l crt0_ptr5,(crt0_ptr4)+ | pour test - dbra crt0_temp,_b_cs340 - - move.l #68340,crt0_cpu_type - move.b #0,crt0_csswitch | CPU - move.b #1,crt0_buswidth | 16 bits - - /*------------------------------------------------- - fill RAM if COLDSTART - -------------------------------------------------*/ -_fill_test: - - tst.l crt0_boot_type - bne _dont_fill - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill - btst.b #bit_meminit,crt0_pdcs - bne _dont_fill - - /* fill main memory */ -_fill: - move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars - move.l #_ExtRam_Start,crt0_temp - sub.l #_crt0_init_stack,crt0_temp - add.l #_ExtRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_fill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _fill_loop - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill_bccram - - /* fill QDMM memory */ - movea.l #_FastRam_Start,crt0_ptr3 | get start - move.l #_FastRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word - -_QDMMfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _QDMMfill_loop - bra _dont_fill - - /* fill BCC memory */ -_fill_bccram: - movea.l #_BCCram_Start,crt0_ptr3 | get start - move.l #_BCCram_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_BCCfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _BCCfill_loop - - /*-------------------------------------------------*/ -_dont_fill: - move.b crt0_csswitch,_AsteccCsSwitch - move.b crt0_buswidth,_AsteccBusWidth - move.l crt0_cpu_type,_AsteccCpuName - - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea SYM(_copy_start),a0 | Get start of DATA in RAM - lea SYM(_etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea SYM(_copy_end),a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea _clear_start,a0 | Get start of BSS - lea _clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #_ISR_Stack_area_end,a7 | set master stack pointer - movel d0,a7@- | command line - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - bra.l SYM(_mainDone) | Stuck forever - - .align 2 -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END diff --git a/spec/build/bsps/m68k/gen68340/abi.yml b/spec/build/bsps/m68k/gen68340/abi.yml deleted file mode 100644 index 84831e93b0..0000000000 --- a/spec/build/bsps/m68k/gen68340/abi.yml +++ /dev/null @@ -1,18 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -mcpu=cpu32 -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/m68k/gen68340/bspgen68340.yml b/spec/build/bsps/m68k/gen68340/bspgen68340.yml deleted file mode 100644 index 9a5f58ca55..0000000000 --- a/spec/build/bsps/m68k/gen68340/bspgen68340.yml +++ /dev/null @@ -1,61 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: m68k -bsp: gen68340 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: gen68340 -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/m68k/gen68340/include/bsp.h - - bsps/m68k/gen68340/include/m340timer.h - - bsps/m68k/gen68340/include/m340uart.h - - bsps/m68k/gen68340/include/m68340.h - - bsps/m68k/gen68340/include/m68340.inc - - bsps/m68k/gen68340/include/m68349.inc -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/m68k/gen68340/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/m68k/gen68340/start/linkcmds -links: -- role: build-dependency - uid: abi -- role: build-dependency - uid: start -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/m68k/gen68340/btimer/btimer.c -- bsps/m68k/gen68340/clock/ckinit.c -- bsps/m68k/gen68340/console/console.c -- bsps/m68k/gen68340/console/m340uart.c -- bsps/m68k/gen68340/start/dumpanic.c -- bsps/m68k/gen68340/start/init68340.c -- bsps/m68k/shared/cache/cache.c -- bsps/m68k/shared/m68kidle.c -- bsps/m68k/shared/memProbe.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/printk-dummy.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/bspstart-empty.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/shared/start/setvec.c -type: build diff --git a/spec/build/bsps/m68k/gen68340/start.yml b/spec/build/bsps/m68k/gen68340/start.yml deleted file mode 100644 index b906b74bb2..0000000000 --- a/spec/build/bsps/m68k/gen68340/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/m68k/gen68340/start/start.S -target: start.o -type: build