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2000-10-18 Joel Sherrill <joel@OARcorp.com>

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* cpu_asm.S, rtems/score/cpu.h: Modified to better support
	multilibing.  These changes result in the code being able to
	compile with the default gcc settings.  It is not functional
	in this configuration but does compile.
This commit is contained in:
Joel Sherrill
2000-10-18 12:58:29 +00:00
parent 38e5a9f021
commit 54ba5aaad6
6 changed files with 58 additions and 34 deletions
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7
c/src/exec/score/cpu/h8300/ChangeLog
View File

@@ -1,3 +1,10 @@
2000-10-18 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S, rtems/score/cpu.h: Modified to better support
multilibing. These changes result in the code being able to
compile with the default gcc settings. It is not functional
in this configuration but does compile.
2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Include compile.am.

12
c/src/exec/score/cpu/h8300/cpu_asm.S
View File

@@ -48,6 +48,7 @@
__CPU_Context_switch:
/* Save Context */
#if defined(__H8300H__) || defined(__H8300S__)
stc.w ccr,@(0:16,er0)
mov.l er7,@(2:16,er0)
mov.l er6,@(6:16,er0)
@@ -66,6 +67,7 @@ restore:
mov.l @(6:16,er1),er6
mov.l @(2:16,er1),er7
ldc.w @(0:16,er1),ccr
#endif
rts
@@ -75,8 +77,10 @@ restore:
__CPU_Context_restore:
Mov.l er0,er1
#if defined(__H8300H__) || defined(__H8300S__)
mov.l er0,er1
jmp @restore:24
#endif
@@ -96,6 +100,7 @@ __CPU_Context_restore:
__ISR_Handler:
#if defined(__H8300H__) || defined(__H8300S__)
mov.l er1,@-er7
mov.l er2,@-er7
mov.l er3,@-er7
@@ -176,6 +181,7 @@ exit:
mov @er7+,er2
mov @er7+,er1
mov @er7+,er0
#endif
rte
/*
@@ -191,7 +197,8 @@ exit:
_ISR_Dispatch:
Jsr @__Thread_Dispatch
#if defined(__H8300H__) || defined(__H8300S__)
jsr @__Thread_Dispatch
mov @er7+,er6
mov @er7+,er5
mov @er7+,er4
@@ -199,6 +206,7 @@ _ISR_Dispatch:
mov @er7+,er2
mov @er7+,er1
mov @er7+,er0
#endif
rte

27
c/src/exec/score/cpu/h8300/rtems/score/cpu.h
View File

@@ -649,7 +649,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/* end of ISR handler macros */
#else
#else /* modern gcc version */
/*
* Disable all interrupts for an RTEMS critical section. The previous
@@ -660,10 +660,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX
*/
#if defined(__H8300__)
#define _CPU_ISR_Disable( _isr_cookie )
asm volatile( "orc #0x80,ccr " );
#else
#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
unsigned char __ccr; \
@@ -671,6 +668,8 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
: "=m" (__ccr) : "0" (__ccr) ); \
(_isr_cookie) = __ccr; \
} while (0)
#else
#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
#endif
@@ -684,15 +683,14 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX
*/
#if defined(__H8300__)
#define _CPU_ISR_Enable( _isr_cookie ) \
asm(" andc #0x7f,ccr \n")
#else
#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Enable( _isr_cookie )
#endif
/*
@@ -706,15 +704,14 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX
*/
#if defined(__H8300__)
#define _CPU_ISR_Enable( _isr_cookie ) \
asm( "andc #0x7f,ccr \n orc #0x80,ccr\n" )
#else
#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Flash( _isr_cookie )
#endif
#endif /* end of old gcc */
@@ -1151,8 +1148,8 @@ void _CPU_Context_restore_fp(
* XXX
*/
static inline unsigned int CPU_swap_u32(
unsigned int value
static inline unsigned32 CPU_swap_u32(
unsigned32 value
)
{
unsigned32 byte1, byte2, byte3, byte4, swapped;

7
cpukit/score/cpu/h8300/ChangeLog
View File

@@ -1,3 +1,10 @@
2000-10-18 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S, rtems/score/cpu.h: Modified to better support
multilibing. These changes result in the code being able to
compile with the default gcc settings. It is not functional
in this configuration but does compile.
2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Include compile.am.

12
cpukit/score/cpu/h8300/cpu_asm.S
View File

@@ -48,6 +48,7 @@
__CPU_Context_switch:
/* Save Context */
#if defined(__H8300H__) || defined(__H8300S__)
stc.w ccr,@(0:16,er0)
mov.l er7,@(2:16,er0)
mov.l er6,@(6:16,er0)
@@ -66,6 +67,7 @@ restore:
mov.l @(6:16,er1),er6
mov.l @(2:16,er1),er7
ldc.w @(0:16,er1),ccr
#endif
rts
@@ -75,8 +77,10 @@ restore:
__CPU_Context_restore:
Mov.l er0,er1
#if defined(__H8300H__) || defined(__H8300S__)
mov.l er0,er1
jmp @restore:24
#endif
@@ -96,6 +100,7 @@ __CPU_Context_restore:
__ISR_Handler:
#if defined(__H8300H__) || defined(__H8300S__)
mov.l er1,@-er7
mov.l er2,@-er7
mov.l er3,@-er7
@@ -176,6 +181,7 @@ exit:
mov @er7+,er2
mov @er7+,er1
mov @er7+,er0
#endif
rte
/*
@@ -191,7 +197,8 @@ exit:
_ISR_Dispatch:
Jsr @__Thread_Dispatch
#if defined(__H8300H__) || defined(__H8300S__)
jsr @__Thread_Dispatch
mov @er7+,er6
mov @er7+,er5
mov @er7+,er4
@@ -199,6 +206,7 @@ _ISR_Dispatch:
mov @er7+,er2
mov @er7+,er1
mov @er7+,er0
#endif
rte

27
cpukit/score/cpu/h8300/rtems/score/cpu.h
View File

@@ -649,7 +649,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/* end of ISR handler macros */
#else
#else /* modern gcc version */
/*
* Disable all interrupts for an RTEMS critical section. The previous
@@ -660,10 +660,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX
*/
#if defined(__H8300__)
#define _CPU_ISR_Disable( _isr_cookie )
asm volatile( "orc #0x80,ccr " );
#else
#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
unsigned char __ccr; \
@@ -671,6 +668,8 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
: "=m" (__ccr) : "0" (__ccr) ); \
(_isr_cookie) = __ccr; \
} while (0)
#else
#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
#endif
@@ -684,15 +683,14 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX
*/
#if defined(__H8300__)
#define _CPU_ISR_Enable( _isr_cookie ) \
asm(" andc #0x7f,ccr \n")
#else
#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Enable( _isr_cookie )
#endif
/*
@@ -706,15 +704,14 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX
*/
#if defined(__H8300__)
#define _CPU_ISR_Enable( _isr_cookie ) \
asm( "andc #0x7f,ccr \n orc #0x80,ccr\n" )
#else
#if defined(__H8300H__) || defined(__H8300S__)
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Flash( _isr_cookie )
#endif
#endif /* end of old gcc */
@@ -1151,8 +1148,8 @@ void _CPU_Context_restore_fp(
* XXX
*/
static inline unsigned int CPU_swap_u32(
unsigned int value
static inline unsigned32 CPU_swap_u32(
unsigned32 value
)
{
unsigned32 byte1, byte2, byte3, byte4, swapped;