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Patch from Jay Kulpinski <jskulpin@eng01.gdds.com> that addresses

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a floating point support problem discovered with the mvme2307 BSP.
A floating point not available exception would occur when trying
to switch to a new thread with the floating point attribute.
Floating point instructions were disabled, but floating point
loads and stores were needed to save and/or restore the context.
This commit is contained in:
Joel Sherrill
2000-04-03 13:57:34 +00:00
parent d2d4372da0
commit 52448f35e9
2 changed files with 13 additions and 1 deletions
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7
c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
View File

@@ -85,8 +85,15 @@ SYM (shared_raw_irq_code_entry):
stw r2, SRR1_FRAME_OFFSET(r1) stw r2, SRR1_FRAME_OFFSET(r1)
/* /*
* Enable data and instruction address translation, exception recovery * Enable data and instruction address translation, exception recovery
*
* also, on CPUs with FP, enable FP so that FP context can be
* saved and restored (using FP instructions)
*/ */
#if (PPC_HAS_FPU == 0)
ori r3, r3, MSR_RI | MSR_IR | MSR_DR ori r3, r3, MSR_RI | MSR_IR | MSR_DR
#else
ori r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
#endif
mtmsr r3 mtmsr r3
SYNC SYNC
/* /*

7
c/src/lib/libbsp/powerpc/shared/start/start.S
View File

@@ -106,8 +106,13 @@ enter_C_code:
.type MMUon,@function .type MMUon,@function
MMUon: MMUon:
mfmsr r0 mfmsr r0
ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 #if (PPC_HAS_FPU == 0)
ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
xori r0, r0, MSR_EE | MSR_IP | MSR_FP xori r0, r0, MSR_EE | MSR_IP | MSR_FP
#else
ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
#endif
mflr r11 mflr r11
mtsrr0 r11 mtsrr0 r11
mtsrr1 r0 mtsrr1 r0