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bsps/powerpc: Support a cache alignment of 64

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Give the BSP the ability to define PPC_CACHE_ALIGNMENT.
This commit is contained in:
Sebastian Huber
2014-12-19 12:12:08 +01:00
parent f6660bfba4
commit 5175ac6a87
1 changed files with 8 additions and 1 deletions
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9
c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
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@@ -61,6 +61,12 @@ extern "C" {
#include <rtems/score/powerpc.h>
/*
* Unfortunately it is very inefficient to use run-time detection for the cache
* line size, so give the BSP the opportunity to define it here.
*/
#include <bspopts.h>
/*
* This file contains the information required to build
* RTEMS for a particular member of the PowerPC family. It does
@@ -271,7 +277,6 @@ extern "C" {
#define PPC_USE_MULTIPLE 1
#elif defined(__ppc_generic)
#define PPC_CACHE_ALIGNMENT 32
#else
@@ -302,6 +307,8 @@ extern "C" {
#define PPC_CACHE_ALIGN_POWER 4
#elif (PPC_CACHE_ALIGNMENT == 32)
#define PPC_CACHE_ALIGN_POWER 5
#elif (PPC_CACHE_ALIGNMENT == 64)
#define PPC_CACHE_ALIGN_POWER 6
#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT)
#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER
#else