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arm: ARMv7-M statically initialized vector table

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Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.

Change licence to BSD-2-Clause in some files.
This commit is contained in:
Sebastian Huber
2020-03-20 09:12:26 +01:00
parent 7e33a80da5
commit 51307919b4
5 changed files with 94 additions and 53 deletions
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39
bsps/arm/shared/clock/clock-armv7m.c
View File

@@ -1,15 +1,29 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2011, 2018 Sebastian Huber. All rights reserved.
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
* Copyright (C) 2011, 2018 Sebastian Huber
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp/clock-armv7m.h>
@@ -29,7 +43,7 @@ static uint32_t _ARMV7M_TC_get_timecount(struct timecounter *base)
return _ARMV7M_Clock_counter((ARMV7M_Timecounter *) base);
}
static void _ARMV7M_Clock_handler(void)
void _ARMV7M_Clock_handler(void)
{
_ARMV7M_Interrupt_service_enter();
Clock_isr(NULL);
@@ -38,10 +52,9 @@ static void _ARMV7M_Clock_handler(void)
static void _ARMV7M_Clock_handler_install(void)
{
_ARMV7M_Set_exception_priority_and_handler(
_ARMV7M_Set_exception_priority(
ARMV7M_VECTOR_SYSTICK,
BSP_ARMV7M_SYSTICK_PRIORITY,
_ARMV7M_Clock_handler
BSP_ARMV7M_SYSTICK_PRIORITY
);
}

52
bsps/arm/shared/irq/irq-armv7m.c
View File

@@ -1,26 +1,40 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2011-2012 Sebastian Huber. All rights reserved.
* Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
* Copyright (C) 2011, 2012 Sebastian Huber
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <string.h>
#include <bsp/irq-generic.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/linker-symbols.h>
#include <bsp/armv7m-irq.h>
#include <rtems/score/armv7m.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/linker-symbols.h>
#include <bsp/armv7m-irq.h>
#include <string.h>
#ifdef ARM_MULTILIB_ARCH_V7M
@@ -38,9 +52,10 @@ void bsp_interrupt_vector_disable(rtems_vector_number vector)
rtems_status_code bsp_interrupt_facility_initialize(void)
{
int i;
ARMV7M_Exception_handler *vector_table =
(ARMV7M_Exception_handler *) bsp_vector_table_begin;
ARMV7M_Exception_handler *vector_table;
int i;
vector_table = (ARMV7M_Exception_handler *) bsp_vector_table_begin;
if (bsp_vector_table_begin != bsp_start_vector_table_begin) {
memcpy(
@@ -53,7 +68,6 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR | ARMV7M_SCB_ICSR_PENDSTCLR;
for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
vector_table [ARMV7M_VECTOR_IRQ(i)] = _ARMV7M_NVIC_Interrupt_dispatch;
_ARMV7M_NVIC_Clear_enable(i);
_ARMV7M_NVIC_Clear_pending(i);
_ARMV7M_NVIC_Set_priority(i, BSP_ARMV7M_IRQ_PRIORITY_DEFAULT);

10
bsps/arm/shared/start/start.S
View File

@@ -5,7 +5,7 @@
*/
/*
* Copyright (c) 2008, 2019 embedded brains GmbH. All rights reserved.
* Copyright (c) 2008, 2020 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -456,13 +456,13 @@ bsp_start_vector_table_begin:
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* SVC */
.word _ARMV7M_Supervisor_call /* SVC */
.word _ARMV7M_Exception_default /* Debug Monitor */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* PendSV */
.word _ARMV7M_Exception_default /* SysTick */
.word _ARMV7M_Pendable_service_call /* PendSV */
.word _ARMV7M_Clock_handler /* SysTick */
.rept BSP_INTERRUPT_VECTOR_MAX + 1
.word _ARMV7M_Exception_default /* IRQ */
.word _ARMV7M_NVIC_Interrupt_dispatch /* IRQ */
.endr
bsp_start_vector_table_end: