RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

SH port submitted from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.

Browse Source
This commit is contained in:
Joel Sherrill
1998-03-20 17:16:31 +00:00
parent a7a08713fb
commit 50cf94da7e
32 changed files with 5497 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
c/src/exec/score/cpu/sh/Makefile.in Normal file
View File

@@ -0,0 +1,88 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH=@srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES=cpu cpu_asm cpu_isps rtems
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES= \
$(srcdir)/cpu.h \
$(srcdir)/shtypes.h \
$(srcdir)/sh.h \
$(srcdir)/sh_io.h \
$(srcdir)/cpu_isps.h \
$(srcdir)/iosh7030.h
# H_FILES that get installed externally
# sh.h is handled separately
EXTERNAL_H_FILES = \
$(srcdir)/asm.h
# Assembly source names, if any, go here -- minus the .s
# Normally cpu_asm and rtems are assembly files
S_PIECES=
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
$(ARCH)/rtems-cpu.rel: $(OBJS)
$(make-rel)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: $(PROJECT_INCLUDE)/rtems/score/targopts.h \
${PROJECT_RELEASE}/lib/bsp_specs
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
# we will share the basic cpu file
$(INSTALL) -m 444 ${EXTERNAL_H_FILES} $(PROJECT_INCLUDE)
$(PROJECT_INCLUDE)/rtems/score/targopts.h: $(ARCH)/targopts.h-tmp
$(INSTALL) -m 444 $(ARCH)/targopts.h-tmp $@
# $(ARCH)/targopts.h-tmp rule is in leaf.cfg
${PROJECT_RELEASE}/lib/bsp_specs: $(ARCH)/bsp_specs.tmp
$(INSTALL) -m 444 $(ARCH)/bsp_specs.tmp $@
# $(ARCH)/bsp_specs.tmp rule is in leaf.cfg

137
c/src/exec/score/cpu/sh/asm.h Normal file
View File

@@ -0,0 +1,137 @@
/* asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_SH_ASM_h
#define __CPU_SH_ASM_h
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#ifndef ASM
#define ASM
#endif
#include <rtems/score/targopts.h>
#include <rtems/score/sh.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
#define r0 REG (r0)
#define r1 REG (r1)
#define r2 REG (r2)
#define r3 REG (r3)
#define r4 REG (r4)
#define r5 REG (r5)
#define r6 REG (r6)
#define r7 REG (r7)
#define r8 REG (r8)
#define r9 REG (r9)
#define r10 REG (r10)
#define r11 REG (r11)
#define r12 REG (r12)
#define r13 REG (r13)
#define r14 REG (r14)
#define r15 REG (r15)
#define vbr REG (vbr)
#define gbr REG (gbr)
#define pr REG (pr)
#define mach REG (mach)
#define macl REG (macl)
#define sr REG (sr)
#define pc REG (pc)
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .global SYM (sym)
#define EXTERN(sym) .global SYM (sym)
#endif

232
c/src/exec/score/cpu/sh/cpu.c Normal file
View File

@@ -0,0 +1,232 @@
/*
* This file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/cpu.h>
#include <rtems/score/sh.h>
/* referenced in start.s */
extern proc_ptr vectab[] ;
proc_ptr vectab[256] ;
extern proc_ptr _Hardware_isr_Table[];
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS:
* cpu_table - CPU table to initialize
* thread_dispatch - address of disptaching routine
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch) /* ignored on this CPU */
)
{
register unsigned32 level = 0;
/*
* The thread_dispatch argument is the address of the entry point
* for the routine called at the end of an ISR once it has been
* decided a context switch is necessary. On some compilation
* systems it is difficult to call a high-level language routine
* from assembly. This allows us to trick these systems.
*
* If you encounter this problem save the entry point in a CPU
* dependent variable.
*/
_CPU_Thread_dispatch_pointer = thread_dispatch;
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
_CPU_Table = *cpu_table;
/* enable interrupts */
_CPU_ISR_Set_level( level);
}
/*PAGE
*
* _CPU_ISR_Get_level
*/
unsigned32 _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
*/
register unsigned32 _mask ;
sh_get_interrupt_level( _mask );
return ( _mask);
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/*
* This is where we install the interrupt handler into the "raw" interrupt
* table used by the CPU to dispatch interrupt handlers.
*/
volatile proc_ptr *vbr ;
#if SH_PARANOID_ISR
unsigned32 level ;
sh_disable_interrupts( level );
#endif
/* get vbr */
asm ( "stc vbr,%0" : "=r" (vbr) );
*old_handler = vbr[vector] ;
vbr[vector] = new_handler ;
#if SH_PARANOID_ISR
sh_enable_interrupts( level );
#endif
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
proc_ptr ignored ;
if(( vector <= 113) && ( vector >= 11))
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* If the interrupt vector table is a table of pointer to isr entry
* points, then we need to install the appropriate RTEMS interrupt
* handler for this vector number.
*/
_CPU_ISR_install_raw_handler(vector,
_Hardware_isr_Table[vector],
&ignored );
/*
* We put the actual user ISR address in '_ISR_Vector_table'.
* This will be used by __ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
}
/*PAGE
*
* _CPU_Thread_Idle_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*/
#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
void _CPU_Thread_Idle_body( void )
{
for( ; ; )
{
asm volatile("nop");
}
/* insert your "halt" instruction here */ ;
}
#endif
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
unsigned8 _bit_set_table[16] =
{ 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
#endif
void _CPU_Context_Initialize(
Context_Control *_the_context,
void *_stack_base,
unsigned32 _size,
unsigned32 _isr,
void (*_entry_point)(void),
int _is_fp )
{
_the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
_the_context->sr = (_isr << 4) & 0x00f0 ;
_the_context->pr = (unsigned32*) _entry_point ;
}

849
c/src/exec/score/cpu/sh/cpu.h Normal file
View File

@@ -0,0 +1,849 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _SH_CPU_h
#define _SH_CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/sh.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/shtypes.h>
#endif
/* conditional compilation parameters */
/*
* Should the calls to _Thread_Enable_dispatch be inlined?
*
* If TRUE, then they are inlined.
* If FALSE, then a subroutine call is made.
*
* Basically this is an example of the classic trade-off of size
* versus speed. Inlining the call (TRUE) typically increases the
* size of RTEMS while speeding up the enabling of dispatching.
* [NOTE: In general, the _Thread_Dispatch_disable_level will
* only be 0 or 1 unless you are in an interrupt handler and that
* interrupt handler invokes the executive.] When not inlined
* something calls _Thread_Enable_dispatch which in turns calls
* _Thread_Dispatch. If the enable dispatch is inlined, then
* one subroutine call is avoided entirely.]
*/
#define CPU_INLINE_ENABLE_DISPATCH FALSE
/*
* Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
* If TRUE, then the loops are unrolled.
* If FALSE, then the loops are not unrolled.
*
* The primary factor in making this decision is the cost of disabling
* and enabling interrupts (_ISR_Flash) versus the cost of rest of the
* body of the loop. On some CPUs, the flash is more expensive than
* one iteration of the loop body. In this case, it might be desirable
* to unroll the loop. It is important to note that on some CPUs, this
* code is the longest interrupt disable period in RTEMS. So it is
* necessary to strike a balance when setting this parameter.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
* If FALSE, nothing is done.
*
* If the CPU supports a dedicated interrupt stack in hardware,
* then it is generally the responsibility of the BSP to allocate it
* and set it up.
*
* If the CPU does not support a dedicated interrupt stack, then
* the porter has two options: (1) execute interrupts on the
* stack of the interrupted task, and (2) have RTEMS manage a dedicated
* interrupt stack.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/*
* We define the interrupt stack in the linker script
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
* We currently support sh1 only, which has no FPU, other SHes have an FPU
*
* The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
* It indicates whether or not this CPU model has FP support. For
* example, it would be possible to have an i386_nofp CPU model
* which set this to false to indicate that you have an i386 without
* an i387 and wish to leave floating point support out of RTEMS.
*/
#define CPU_HARDWARE_FP FALSE
/*
* Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
* So far, the only CPU in which this option has been used is the
* HP PA-RISC. The HP C compiler and gcc both implicitly use the
* floating point registers to perform integer multiplies. If
* a function which you would not think utilize the FP unit DOES,
* then one can not easily predict which tasks will use the FP hardware.
* In this case, this option should be TRUE.
*
* If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/*
* Should the IDLE task have a floating point context?
*
* If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
* and it has a floating point context which is switched in and out.
* If FALSE, then the IDLE task does not have a floating point context.
*
* Setting this to TRUE negatively impacts the time required to preempt
* the IDLE task from an interrupt because the floating point context
* must be saved as part of the preemption.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
* If TRUE, then the floating point context will not be stored until
* necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
* If FALSE, then the floating point context is saved when a floating
* point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
*
* If the floating point context does NOT have to be saved as part of
* interrupt dispatching, then it should be safe to set this to TRUE.
*
* Setting this flag to TRUE results in using a different algorithm
* for deciding when to save and restore the floating point context.
* The deferred FP switch algorithm minimizes the number of times
* the FP context is saved and restored. The FP context is not saved
* until a context switch is made to another, different FP task.
* Thus in a system with only one FP task, the FP context will never
* be saved or restored.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Thread_Idle_body
* must be provided and is the default IDLE thread body instead of
* _CPU_Thread_Idle_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*
* This is intended to allow for supporting processors which have
* a low power or idle mode. When the IDLE thread is executed, then
* the CPU can be powered down.
*
* The order of precedence for selecting the IDLE thread body is:
*
* 1. BSP provided
* 2. CPU dependent (if provided)
* 3. generic (if no BSP and no CPU dependent)
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
* If TRUE, then the grows upward.
* If FALSE, then the grows toward smaller addresses.
*/
#define CPU_STACK_GROWS_UP FALSE
/*
* The following is the variable attribute used to force alignment
* of critical RTEMS structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The placement of this macro in the declaration of the variables
* is based on the syntactically requirements of the GNU C
* "__attribute__" extension. For example with GNU C, use
* the following to force a structures to a 32 byte boundary.
*
* __attribute__ ((aligned (32)))
*
* NOTE: Currently only the Priority Bit Map table uses this feature.
* To benefit from using this, the data must be heavily
* used so it will stay in the cache and used frequently enough
* in the executive to justify turning this on.
*/
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x0000000f
/*
* Processor defined structures
*
* Examples structures include the descriptor tables from the i386
* and the processor control structure on the i960ca.
*/
/* may need to put some structures here. */
/*
* Contexts
*
* Generally there are 2 types of context to save.
* 1. Interrupt registers to save
* 2. Task level registers to save
*
* This means we have the following 3 context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
* 3. special interrupt level context :: Context_Control_interrupt
*
* On some processors, it is cost-effective to save only the callee
* preserved registers during a task context switch. This means
* that the ISR code needs to save those registers which do not
* persist across function calls. It is not mandatory to make this
* distinctions between the caller/callee saves registers for the
* purpose of minimizing context saved during task switch and on interrupts.
* If the cost of saving extra registers is minimal, simplicity is the
* choice. Save the same context on interrupt entry as for tasks in
* this case.
*
* Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
* care should be used in designing the context area.
*
* On some CPUs with hardware floating point support, the Context_Control_fp
* structure will not be used or it simply consist of an array of a
* fixed number of bytes. This is done when the floating point context
* is dumped by a "FP save context" type instruction and the format
* is not really defined by the CPU. In this case, there is no need
* to figure out the exact format -- only the size. Of course, although
* this is enough information for RTEMS, it is probably not enough for
* a debugger such as gdb. But that is another problem.
*/
typedef struct {
unsigned32 *r15; /* stack pointer */
unsigned32 macl;
unsigned32 mach;
unsigned32 *pr;
unsigned32 *r14; /* frame pointer/call saved */
unsigned32 r13; /* call saved */
unsigned32 r12; /* call saved */
unsigned32 r11; /* call saved */
unsigned32 r10; /* call saved */
unsigned32 r9; /* call saved */
unsigned32 r8; /* call saved */
unsigned32 *r7; /* arg in */
unsigned32 *r6; /* arg in */
#if 0
unsigned32 *r5; /* arg in */
unsigned32 *r4; /* arg in */
#endif
unsigned32 *r3; /* scratch */
unsigned32 *r2; /* scratch */
unsigned32 *r1; /* scratch */
unsigned32 *r0; /* arg return */
unsigned32 gbr;
unsigned32 sr;
} Context_Control;
typedef struct {
} Context_Control_fp;
typedef struct {
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the SH processor specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
} rtems_cpu_table;
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
* _CPU_Initialize and copied into the task's FP context area during
* _CPU_Context_Initialize.
*/
/*
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
*/
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/*
* With some compilation systems, it is difficult if not impossible to
* call a high-level language routine from assembly language. This
* is especially true of commercial Ada compilers and name mangling
* C++ ones. This variable can be optionally defined by the CPU porter
* and contains the address of the routine _Thread_Dispatch. This
* can make it easier to invoke that routine at the end of the interrupt
* sequence (if a dispatch is necessary).
*/
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
/* XXX: if needed, put more variables here */
/*
* The size of the floating point context area. On some CPUs this
* will not be a "sizeof" because the format of the floating point
* area is not defined -- only the size is. This is usually on
* CPUs with a "floating point save context" instruction.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* Amount of extra stack (above minimum stack size) required by
* MPCI receive server thread. Remember that in a multiprocessor
* system this thread must exist and be able to process all directives.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
* by RTEMS.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Should be large enough to run all RTEMS tests. This insures
* that a "reasonable" small application should not have any problems.
*
* We have been able to run the sptests with this value, but have not
* been able to run the tmtest suite.
*/
#define CPU_STACK_MINIMUM_SIZE 4096
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*/
#define CPU_ALIGNMENT 4
/*
* This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
* common for the heap to follow the same alignment requirement as
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
* CPU_ALIGNMENT. It is common for the partition to follow the same
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
/* ISR handler macros */
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
*/
#define _CPU_ISR_Disable( _level) \
sh_disable_interrupts( _level )
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* _level is not modified.
*/
#define _CPU_ISR_Enable( _level) \
sh_enable_interrupts( _level)
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define _CPU_ISR_Flash( _level) \
sh_flash_interrupts( _level)
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a generic fashion are undefined. Someday,
* it would be nice if these were "mapped" by the application
* via a callout. For example, m68k has 8 levels 0 - 7, levels
* 8 - 255 would be available for bsp/application specific meaning.
* This could be used to manage a programmable interrupt controller
* via the rtems_task_mode directive.
*/
#define _CPU_ISR_Set_level( _newlevel) \
sh_set_interrupt_level(_newlevel)
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
/*
* Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
* - setting a starting address
* - preparing the stack
* - preparing the stack and frame pointers
* - setting the proper interrupt level in the context
* - initializing the floating point context
*
* This routine generally does not set any unnecessary register
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
* NOTE: This is_fp parameter is TRUE if the thread is to be a floating
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
*/
/*
* FIXME: defined as a function for debugging - should be a macro
*/
SCORE_EXTERN void _CPU_Context_Initialize(
Context_Control *_the_context,
void *_stack_base,
unsigned32 _size,
unsigned32 _isr,
void (*_entry_point)(void),
int _is_fp );
/*
* This routine is responsible for somehow restarting the currently
* executing task. If you are lucky, then all that is necessary
* is restoring the context. Otherwise, there will need to be
* a special assembly routine which does something special in this
* case. Context_Restore should work most of the time. It will
* not work if restarting self conflicts with the stack frame
* assumptions of restoring a context.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
/*
* The purpose of this macro is to allow the initial pointer into
* a floating point context area (used to save the floating point
* context) to be at an arbitrary place in the floating point
* context area.
*
* This is necessary because some FP units are designed to have
* their context saved as a stack which grows into lower addresses.
* Other FP units can be saved by simply moving registers into offsets
* from the base of the context area. Finally some FP units provide
* a "dump context" instruction which could fill in from high to low
* or low to high based on the whim of the CPU designers.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
/*
* This routine initializes the FP context area passed to it to.
* There are a few standard ways in which to initialize the
* floating point context. The code included for this macro assumes
* that this is a CPU in which a "initial" FP context was saved into
* _CPU_Null_fp_context and it simply copies it to the destination
* context passed to it.
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
* SH has no FPU !!!!!!!!!!!!
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ }
/* end of Context handler macros */
/* Fatal Error manager macros */
/*
* FIXME: Trap32 ???
*
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* invokes a Trap32 Instruction which returns to the breakpoint
* routine of cmon.
*/
#ifdef BSP_FATAL_HALT
/* we manage the fatal error in the board support package */
void bsp_fatal_halt( unsigned32 _error);
#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
#else
#define _CPU_Fatal_halt( _error)\
{ \
asm volatile("mov.l %0,r0"::"m" (_error)); \
asm volatile("trapa #34"); \
}
#endif
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
/*
* This routine sets _output to the bit number of the first bit
* set in _value. _value is of CPU dependent type Priority_Bit_map_control.
* This type may be either 16 or 32 bits wide although only the 16
* least significant bits will be used.
*
* There are a number of variables in using a "find first bit" type
* instruction.
*
* (1) What happens when run on a value of zero?
* (2) Bits may be numbered from MSB to LSB or vice-versa.
* (3) The numbering may be zero or one based.
* (4) The "find first bit" instruction may search from MSB or LSB.
*
* RTEMS guarantees that (1) will never happen so it is not a concern.
* (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
* _CPU_Priority_bits_index(). These three form a set of routines
* which must logically operate together. Bits in the _value are
* set and cleared based on masks built by _CPU_Priority_mask().
* The basic major and minor values calculated by _Priority_Major()
* and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
* to properly range between the values returned by the "find first bit"
* instruction. This makes it possible for _Priority_Get_highest() to
* calculate the major and directly index into the minor table.
* This mapping is necessary to ensure that 0 (a high priority major/minor)
* is the first bit found.
*
* This entire "find first bit" and mapping process depends heavily
* on the manner in which a priority is broken into a major and minor
* components with the major being the 4 MSB of a priority and minor
* the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
* priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
* to the lowest priority.
*
* If your CPU does not have a "find first bit" instruction, then
* there are ways to make do without it. Here are a handful of ways
* to implement this in software:
*
* - a series of 16 bit test instructions
* - a "binary search using if's"
* - _number = 0
* if _value > 0x00ff
* _value >>=8
* _number = 8;
*
* if _value > 0x0000f
* _value >=8
* _number += 4
*
* _number += bit_set_table[ _value ]
*
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
extern unsigned8 _bit_set_table[];
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
_output = 0;\
if(_value > 0x00ff) \
{ _value >>= 8; _output = 8; } \
if(_value > 0x000f) \
{ _output += 4; _value >>= 4; } \
_output += _bit_set_table[ _value]; }
#endif
/* end of Bitfield handler macros */
/*
* This routine builds the mask which corresponds to the bit fields
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#endif
/*
* This routine translates the bit numbers returned by
* _CPU_Bitfield_Find_first_bit() into something suitable for use as
* a major or minor component of a priority. See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
#endif
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*
* NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
* is TRUE.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Thread_Idle_body
*
* This routine is the CPU dependent IDLE thread body.
*
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
* is TRUE.
*/
void _CPU_Thread_Idle_body( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
#ifdef __cplusplus
}
#endif
#endif

311
c/src/exec/score/cpu/sh/cpu_asm.c Normal file
View File

@@ -0,0 +1,311 @@
/*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language
*
* NOTE: This port uses a C file with inline assembler instructions
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" cpu_asm file. An
* implementation in assembly should include "cpu_asm.h"
*/
#include <rtems/system.h>
#include <rtems/score/cpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/thread.h>
#include <rtems/score/cpu_isps.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/sh.h>
#include <rtems/score/iosh7030.h>
/* from cpu_isps.c */
extern proc_ptr _Hardware_isr_Table[];
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("r15");
/*
* sh_set_irq_priority
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
unsigned32 shiftcount;
unsigned32 prioreg;
unsigned16 temp16;
unsigned32 level;
/*
* first check for valid interrupt
*/
if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
return -1;
/*
* check for valid irq priority
*/
if( prio > 15 )
return -1;
/*
* look up appropriate interrupt priority register
*/
if( irq > 71)
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
case 1: { prioreg = INTC_IPRD; break;}
case 2: { prioreg = INTC_IPRE; break;}
default: return -1;
}
}
else
{
shiftcount = 12 - 4 * ( irq % 4);
if( irq > 67)
prioreg = INTC_IPRB;
else
prioreg = INTC_IPRA;
}
/*
* Set the interrupt priority register
*/
_CPU_ISR_Disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_CPU_ISR_Enable( level );
return 0;
}
/*
* _CPU_Context_save_fp_context
*
* This routine is responsible for saving the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
)
{
}
/*
* _CPU_Context_restore_fp_context
*
* This routine is responsible for restoring the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
)
{
}
/* _CPU_Context_switch
*
* This routine performs a normal non-FP context switch.
*/
/* within __CPU_Context_switch:
* _CPU_Context_switch
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: It should be safe not to store r4, r5
*
* NOTE: It is doubtful if r0 is really needed to be stored
*
* NOTE: gbr is added, but should not be necessary, as it is
* only used globally in this port.
*/
/*
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* the offset each time Context_Control is changed
*/
void __CPU_Context_switch(
Context_Control *run, /* r4 */
Context_Control *heir /* r5 */
)
{
asm volatile("
.global __CPU_Context_switch
__CPU_Context_switch:
add %0,r4
stc.l sr,@-r4
stc.l gbr,@-r4
mov.l r0,@-r4
mov.l r1,@-r4
mov.l r2,@-r4
mov.l r3,@-r4
mov.l r6,@-r4
mov.l r7,@-r4
mov.l r8,@-r4
mov.l r9,@-r4
mov.l r10,@-r4
mov.l r11,@-r4
mov.l r12,@-r4
mov.l r13,@-r4
mov.l r14,@-r4
sts.l pr,@-r4
sts.l mach,@-r4
sts.l macl,@-r4
mov.l r15,@-r4
mov r5, r4"
:: "I" (sizeof(Context_Control))
);
asm volatile("
.global __CPU_Context_restore
__CPU_Context_restore:
mov.l @r4+,r15
lds.l @r4+,macl
lds.l @r4+,mach
lds.l @r4+,pr
mov.l @r4+,r14
mov.l @r4+,r13
mov.l @r4+,r12
mov.l @r4+,r11
mov.l @r4+,r10
mov.l @r4+,r9
mov.l @r4+,r8
mov.l @r4+,r7
mov.l @r4+,r6
mov.l @r4+,r3
mov.l @r4+,r2
mov.l @r4+,r1
mov.l @r4+,r0
ldc.l @r4+,gbr
ldc.l @r4+,sr
rts
nop" );
}
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( unsigned32 vector)
{
register unsigned32 level;
_CPU_ISR_Disable( level );
_Thread_Dispatch_disable_level++;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0 )
{
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high;
}
#endif
_ISR_Nest_level++;
_CPU_ISR_Enable( level );
/* call isp */
if( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_CPU_ISR_Disable( level );
_ISR_Nest_level--;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
#endif
_Thread_Dispatch_disable_level--;
_CPU_ISR_Enable( level );
if ( _Thread_Dispatch_disable_level == 0 )
{
if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
{
_ISR_Signals_to_thread_executing = FALSE;
_Thread_Dispatch();
}
}
}

252
c/src/exec/score/cpu/sh/cpu_isps.c Normal file
View File

@@ -0,0 +1,252 @@
/*
* This file contains the isp frames for the user interrupts.
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/shtypes.h>
#include <rtems/score/cpu_isps.h>
/*
* This is a exception vector table
*
* It has the same structure like the actual vector table (vectab)
*/
proc_ptr _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
/* irq 64 ... */
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
_wdt_isp,
/* 113 */ _dref_isp
};
#define Str(a)#a
/*
* Some versions of gcc and all version of egcs at least until egcs-1.0.2
* are not able to handle #praga interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
#define isp( name, number, func)\
asm (".global _"Str(name)"\n\t" \
"_"Str(name)": \n\t" \
" mov.l r0,@-r15 \n\t" \
" mov.l r1,@-r15 \n\t" \
" mov.l r2,@-r15 \n\t" \
" mov.l r3,@-r15 \n\t" \
" mov.l r4,@-r15 \n\t" \
" mov.l r5,@-r15 \n\t" \
" mov.l r6,@-r15 \n\t" \
" mov.l r7,@-r15 \n\t" \
" mov.l r14,@-r15 \n\t" \
" sts.l pr,@-r15 \n\t" \
" sts.l mach,@-r15 \n\t" \
" sts.l macl,@-r15 \n\t" \
" mov r15,r14 \n\t" \
" mov.l "Str(name)"_k, r1\n\t" \
" jsr @r1 \n\t" \
" mov #"Str(number)", r4\n\t" \
" mov r14,r15 \n\t" \
" lds.l @r15+,macl \n\t" \
" lds.l @r15+,mach \n\t" \
" lds.l @r15+,pr \n\t" \
" mov.l @r15+,r14 \n\t" \
" mov.l @r15+,r7 \n\t" \
" mov.l @r15+,r6 \n\t" \
" mov.l @r15+,r5 \n\t" \
" mov.l @r15+,r4 \n\t" \
" mov.l @r15+,r3 \n\t" \
" mov.l @r15+,r2 \n\t" \
" mov.l @r15+,r1 \n\t" \
" mov.l @r15+,r0 \n\t" \
" rte \n\t" \
" nop \n\t" \
" .align 2 \n\t" \
#name"_k: \n\t" \
".long "Str(func));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
asm(" .section .text
.global __dummy_isp
__dummy_isp:
mov.l r14,@-r15
mov r15, r14
trapa #34
mov.l @r15+,r14
rte
nop");
/*****************************
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Interrupt timer unit
*****************************/
/*****************************
* Timer 0
*****************************/
isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler);
/*****************************
* Timer 1
*****************************/
isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler);
/*****************************
* Timer 2
*****************************/
isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler);
/*****************************
* Timer 3
*****************************/
isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler);
/*****************************
* Timer 4
*****************************/
isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
*****************************/
/*****************************
* Serial interface 0
*****************************/
isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
/*****************************
* Serial interface 1
*****************************/
isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
*****************************/
isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
/******************************
* Analog digital converter
* ADC
******************************/
isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);

165
c/src/exec/score/cpu/sh/cpu_isps.h Normal file
View File

@@ -0,0 +1,165 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/shtypes.h>
extern void __ISR_Handler( unsigned32 vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 74
#define DMA2_ISP_V 76
#define DMA3_ISP_V 78
#define IMIA0_ISP_V 80
#define IMIB0_ISP_V 81
#define OVI0_ISP_V 82
#define IMIA1_ISP_V 84
#define IMIB1_ISP_V 85
#define OVI1_ISP_V 86
#define IMIA2_ISP_V 88
#define IMIB2_ISP_V 89
#define OVI2_ISP_V 90
#define IMIA3_ISP_V 92
#define IMIB3_ISP_V 93
#define OVI3_ISP_V 94
#define IMIA4_ISP_V 96
#define IMIB4_ISP_V 97
#define OVI4_ISP_V 98
#define ERI0_ISP_V 100
#define RXI0_ISP_V 101
#define TXI0_ISP_V 102
#define TEI0_ISP_V 103
#define ERI1_ISP_V 104
#define RXI1_ISP_V 105
#define TXI1_ISP_V 106
#define TEI1_ISP_V 107
#define PRT_ISP_V 108
#define ADU_ISP_V 109
#define WDT_ISP_V 112
#define DREF_ISP_V 113
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _imia0_isp( void );
extern void _imib0_isp( void );
extern void _ovi0_isp( void );
/* Timer 1 */
extern void _imia1_isp( void );
extern void _imib1_isp( void );
extern void _ovi1_isp( void );
/* Timer 2 */
extern void _imia2_isp( void );
extern void _imib2_isp( void );
extern void _ovi2_isp( void );
/* Timer 3 */
extern void _imia3_isp( void );
extern void _imib3_isp( void );
extern void _ovi3_isp( void );
/* Timer 4 */
extern void _imia4_isp( void );
extern void _imib4_isp( void );
extern void _ovi4_isp( void );
/* seriell interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* Parity Control Unit of the Bus State Controllers */
extern void _prt_isp( void );
/* ADC */
extern void _adu_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _dref_isp( void );
#ifdef __cplusplus
}
#endif
#endif

223
c/src/exec/score/cpu/sh/iosh7030.h Normal file
View File

@@ -0,0 +1,223 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __IOSH7030_H
#define __IOSH7030_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
*/
#define SCI0_SMR 0x05fffec0 /* char */
#define SCI0_BRR 0x05fffec1 /* char */
#define SCI0_SCR 0x05fffec2 /* char */
#define SCI0_TDR 0x05fffec3 /* char */
#define SCI0_SSR 0x05fffec4 /* char */
#define SCI0_RDR 0x05fffec5 /* char */
#define SCI1_SMR 0x05fffec8 /* char */
#define SCI1_BRR 0x05fffec9 /* char */
#define SCI1_SCR 0x05fffeca /* char */
#define SCI1_TDR 0x05fffecb /* char */
#define SCI1_SSR 0x05fffecc /* char */
#define SCI1_RDR 0x05fffecd /* char */
#define ADDRAH 0x05fffee0 /* char */
#define ADDRAL 0x05fffee1 /* char */
#define ADDRBH 0x05fffee2 /* char */
#define ADDRBL 0x05fffee3 /* char */
#define ADDRCH 0x05fffee4 /* char */
#define ADDRCL 0x05fffee5 /* char */
#define ADDRDH 0x05fffee6 /* char */
#define ADDRDL 0x05fffee7 /* char */
#define AD_DRA 0x05fffee0 /* short */
#define AD_DRB 0x05fffee2 /* short */
#define AD_DRC 0x05fffee4 /* short */
#define AD_DRD 0x05fffee6 /* short */
#define ADCSR 0x05fffee8 /* char */
#define ADCR 0x05fffee9 /* char */
/*ITU SHARED*/
#define ITU_TSTR 0x05ffff00 /* char */
#define ITU_TSNC 0x05ffff01 /* char */
#define ITU_TMDR 0x05ffff02 /* char */
#define ITU_TFCR 0x05ffff03 /* char */
/*ITU CHANNEL 0*/
#define ITU_TCR0 0x05ffff04 /* char */
#define ITU_TIOR0 0x05ffff05 /* char */
#define ITU_TIER0 0x05ffff06 /* char */
#define ITU_TSR0 0x05ffff07 /* char */
#define ITU_TCNT0 0x05ffff08 /* short */
#define ITU_GRA0 0x05ffff0a /* short */
#define ITU_GRB0 0x05ffff0c /* short */
/*ITU CHANNEL 1*/
#define ITU_TCR1 0x05ffff0E /* char */
#define ITU_TIOR1 0x05ffff0F /* char */
#define ITU_TIER1 0x05ffff10 /* char */
#define ITU_TSR1 0x05ffff11 /* char */
#define ITU_TCNT1 0x05ffff12 /* short */
#define ITU_GRA1 0x05ffff14 /* short */
#define ITU_GRB1 0x05ffff16 /* short */
/*ITU CHANNEL 2*/
#define ITU_TCR2 0x05ffff18 /* char */
#define ITU_TIOR2 0x05ffff19 /* char */
#define ITU_TIER2 0x05ffff1A /* char */
#define ITU_TSR2 0x05ffff1B /* char */
#define ITU_TCNT2 0x05ffff1C /* short */
#define ITU_GRA2 0x05ffff1E /* short */
#define ITU_GRB2 0x05ffff20 /* short */
/*ITU CHANNEL 3*/
#define ITU_TCR3 0x05ffff22 /* char */
#define ITU_TIOR3 0x05ffff23 /* char */
#define ITU_TIER3 0x05ffff24 /* char */
#define ITU_TSR3 0x05ffff25 /* char */
#define ITU_TCNT3 0x05ffff26 /* short */
#define ITU_GRA3 0x05ffff28 /* short */
#define ITU_GRB3 0x05ffff2A /* short */
#define ITU_BRA3 0x05ffff2C /* short */
#define ITU_BRB3 0x05ffff2E /* short */
/*ITU CHANNELS 0-4 SHARED*/
#define ITU_TOCR 0x05ffff31 /* char */
/*ITU CHANNEL 4*/
#define ITU_TCR4 0x05ffff32 /* char */
#define ITU_TIOR4 0x05ffff33 /* char */
#define ITU_TIER4 0x05ffff34 /* char */
#define ITU_TSR4 0x05ffff35 /* char */
#define ITU_TCNT4 0x05ffff36 /* short */
#define ITU_GRA4 0x05ffff38 /* short */
#define ITU_GRB4 0x05ffff3A /* short */
#define ITU_BRA4 0x05ffff3C /* short */
#define ITU_BRB4 0x05ffff3E /* short */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR 0x05ffff48 /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 0x05ffff40 /* long */
#define DMA_DAR0 0x05ffff44 /* long */
#define DMA_TCR0 0x05ffff4a /* short */
#define DMA_CHCR0 0x05ffff4e /* short */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 0x05ffff50 /* long */
#define DMA_DAR1 0x05ffff54 /* long */
#define DMA_TCR1 0x05fffF5a /* short */
#define DMA_CHCR1 0x05ffff5e /* short */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 0x05ffff60 /* long */
#define DMA_DAR3 0x05ffff64 /* long */
#define DMA_TCR3 0x05fffF6a /* short */
#define DMA_CHCR3 0x05ffff6e /* short */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 0x05ffff70 /* long */
#define DMA_DAR4 0x05ffff74 /* long */
#define DMA_TCR4 0x05fffF7a /* short */
#define DMA_CHCR4 0x05ffff7e /* short */
/*INTC*/
#define INTC_IPRA 0x05ffff84 /* short */
#define INTC_IPRB 0x05ffff86 /* short */
#define INTC_IPRC 0x05ffff88 /* short */
#define INTC_IPRD 0x05ffff8A /* short */
#define INTC_IPRE 0x05ffff8C /* short */
#define INTC_ICR 0x05ffff8E /* short */
/*UBC*/
#define UBC_BARH 0x05ffff90 /* short */
#define UBC_BARL 0x05ffff92 /* short */
#define UBC_BAMRH 0x05ffff94 /* short */
#define UBC_BAMRL 0x05ffff96 /* short */
#define UBC_BBR 0x05ffff98 /* short */
/*BSC*/
#define BSC_BCR 0x05ffffA0 /* short */
#define BSC_WCR1 0x05ffffA2 /* short */
#define BSC_WCR2 0x05ffffA4 /* short */
#define BSC_WCR3 0x05ffffA6 /* short */
#define BSC_DCR 0x05ffffA8 /* short */
#define BSC_PCR 0x05ffffAA /* short */
#define BSC_RCR 0x05ffffAC /* short */
#define BSC_RTCSR 0x05ffffAE /* short */
#define BSC_RTCNT 0x05ffffB0 /* short */
#define BSC_RTCOR 0x05ffffB2 /* short */
/*WDT*/
#define WDT_TCSR 0x05ffffB8 /* char */
#define WDT_TCNT 0x05ffffB9 /* char */
#define WDT_RSTCSR 0x05ffffBB /* char */
/*POWER DOWN STATE*/
#define PDT_SBYCR 0x05ffffBC /* char */
/*PORT A*/
#define PADR 0x05ffffC0 /* short */
/*PORT B*/
#define PBDR 0x05ffffC2 /* short */
/*PORT C*/
#define PCDR 0x05ffffD0 /* short */
/*PFC*/
#define PFC_PAIOR 0x05ffffC4 /* short */
#define PFC_PBIOR 0x05ffffC6 /* short */
#define PFC_PACR1 0x05ffffC8 /* short */
#define PFC_PACR2 0x05ffffCA /* short */
#define PFC_PBCR1 0x05ffffCC /* short */
#define PFC_PBCR2 0x05ffffCE /* short */
#define PFC_CASCR 0x05ffffEE /* short */
/*TPC*/
#define TPC_TPMR 0x05ffffF0 /* short */
#define TPC_TPCR 0x05ffffF1 /* short */
#define TPC_NDERH 0x05ffffF2 /* short */
#define TPC_NDERL 0x05ffffF3 /* short */
#define TPC_NDRB 0x05ffffF4 /* char */
#define TPC_NDRA 0x05ffff5F /* char */
#define TPC_NDRB1 0x05ffffF6 /* char */
#define TPC_NDRA1 0x05ffffF7 /* char */
#endif

252
c/src/exec/score/cpu/sh/ispsh7032.c Normal file
View File

@@ -0,0 +1,252 @@
/*
* This file contains the isp frames for the user interrupts.
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/shtypes.h>
#include <rtems/score/cpu_isps.h>
/*
* This is a exception vector table
*
* It has the same structure like the actual vector table (vectab)
*/
proc_ptr _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
/* irq 64 ... */
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
_wdt_isp,
/* 113 */ _dref_isp
};
#define Str(a)#a
/*
* Some versions of gcc and all version of egcs at least until egcs-1.0.2
* are not able to handle #praga interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
#define isp( name, number, func)\
asm (".global _"Str(name)"\n\t" \
"_"Str(name)": \n\t" \
" mov.l r0,@-r15 \n\t" \
" mov.l r1,@-r15 \n\t" \
" mov.l r2,@-r15 \n\t" \
" mov.l r3,@-r15 \n\t" \
" mov.l r4,@-r15 \n\t" \
" mov.l r5,@-r15 \n\t" \
" mov.l r6,@-r15 \n\t" \
" mov.l r7,@-r15 \n\t" \
" mov.l r14,@-r15 \n\t" \
" sts.l pr,@-r15 \n\t" \
" sts.l mach,@-r15 \n\t" \
" sts.l macl,@-r15 \n\t" \
" mov r15,r14 \n\t" \
" mov.l "Str(name)"_k, r1\n\t" \
" jsr @r1 \n\t" \
" mov #"Str(number)", r4\n\t" \
" mov r14,r15 \n\t" \
" lds.l @r15+,macl \n\t" \
" lds.l @r15+,mach \n\t" \
" lds.l @r15+,pr \n\t" \
" mov.l @r15+,r14 \n\t" \
" mov.l @r15+,r7 \n\t" \
" mov.l @r15+,r6 \n\t" \
" mov.l @r15+,r5 \n\t" \
" mov.l @r15+,r4 \n\t" \
" mov.l @r15+,r3 \n\t" \
" mov.l @r15+,r2 \n\t" \
" mov.l @r15+,r1 \n\t" \
" mov.l @r15+,r0 \n\t" \
" rte \n\t" \
" nop \n\t" \
" .align 2 \n\t" \
#name"_k: \n\t" \
".long "Str(func));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
asm(" .section .text
.global __dummy_isp
__dummy_isp:
mov.l r14,@-r15
mov r15, r14
trapa #34
mov.l @r15+,r14
rte
nop");
/*****************************
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Interrupt timer unit
*****************************/
/*****************************
* Timer 0
*****************************/
isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler);
/*****************************
* Timer 1
*****************************/
isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler);
/*****************************
* Timer 2
*****************************/
isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler);
/*****************************
* Timer 3
*****************************/
isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler);
/*****************************
* Timer 4
*****************************/
isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
*****************************/
/*****************************
* Serial interface 0
*****************************/
isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
/*****************************
* Serial interface 1
*****************************/
isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
*****************************/
isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
/******************************
* Analog digital converter
* ADC
******************************/
isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);

71
c/src/exec/score/cpu/sh/rtems.c Normal file
View File

@@ -0,0 +1,71 @@
/*
* This file contains the single entry point code for
* the SH implementation of RTEMS.
*
* NOTE: This is supposed to be a .S or .s file NOT a C file.
*
* NOTE: UNTESTED, very likely this does not not work.
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" rtems file.
*/
/* #include <rtems/system.h> */
/* #include <rtems/score/cpu.h> */
/* #include "asm.h" */
/*
* This should work but due to a bug in rtems building scheme it doesn't work
*/
/* #include <rtems/directives.h> */
extern void* _Entry_points[] ;
/*
* RTEMS
*
* This routine jumps to the directive indicated in the
* CPU defined register. This routine is used when RTEMS is
* linked by itself and placed in ROM. This routine is the
* first address in the ROM space for RTEMS. The user "calls"
* this address with the directive arguments in the normal place.
* This routine then jumps indirectly to the correct directive
* preserving the arguments. The directive should not realize
* it has been "wrapped" in this way. The table "_Entry_points"
* is used to look up the directive.
*/
void __RTEMS()
{
asm volatile (
".global _RTEMS
_RTEMS:" );
asm volatile (
"jmp %0
rts
nop"
:: "m" (_Entry_points) );
}

174
c/src/exec/score/cpu/sh/sh.h Normal file
View File

@@ -0,0 +1,174 @@
/* sh.h
*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _sh_h
#define _sh_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "SH" family.
*
* It does this by setting variables to indicate which implementation
* dependent features are present in a particular member of the family.
*/
#if defined(sh7032)
#define CPU_MODEL_NAME "SH 7032"
#define SH_HAS_FPU 0
/*
* If the following macro is set to 0 there will be no software irq stack
*/
#define SH_HAS_SEPARATE_STACKS 1
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "Hitachi SH"
#ifndef ASM
/*
* Mask for disabling interrupts
*/
#define SH_IRQDIS_VALUE 0xf0
#define sh_disable_interrupts( _level ) \
asm volatile ( \
"stc sr,%0\n\t" \
"ldc %1,sr\n\t"\
: "=r" (_level ) \
: "r" (SH_IRQDIS_VALUE) );
#define sh_enable_interrupts( _level ) \
asm volatile( "ldc %0,sr\n\t" \
"nop\n\t" \
:: "r" (_level) );
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define sh_flash_interrupts( _level ) \
asm volatile( \
"ldc %1,sr\n\t" \
"nop\n\t" \
"ldc %0,sr\n\t" \
"nop\n\t" \
: : "r" (SH_IRQDIS_VALUE), "r" (_level) );
#define sh_get_interrupt_level( _level ) \
{ \
register unsigned32 _tmpsr ; \
\
asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
_level = (_tmpsr & 0xf0) >> 4 ; \
}
#define sh_set_interrupt_level( _newlevel ) \
{ \
register unsigned32 _tmpsr; \
\
asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
_tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \
asm volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
}
/*
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*/
static inline unsigned int sh_swap_u32(
unsigned int value
)
{
register unsigned int swapped ;
asm volatile (
"swap.b %1,%0
swap.w %0,%0
swap.b %0,%0"
: "=r" (swapped)
: "r" (value) );
return( swapped );
}
#define CPU_swap_u32( value ) sh_swap_u32( value )
/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*
* Since we don't have a real time clock, this is a very rough
* approximation, assuming that each cycle of the delay loop takes
* approx. 4 machine cycles.
*
* e.g.: MHZ = 20 => 5e-8 secs per instruction
* => 4 * 5e-8 secs per delay loop
*/
#define sh_delay( microseconds ) \
{ register unsigned int _delay = (microseconds) * (MHZ / 4 ); \
asm volatile ( \
"0: add #-1,%0\n \
nop\n \
cmp/pl %0\n \
bt 0b\
nop" \
:: "r" (_delay) ); \
}
#define CPU_delay( microseconds ) sh_delay( microseconds )
extern unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio );
#endif /* !ASM */
#ifdef __cplusplus
}
#endif
#endif

48
c/src/exec/score/cpu/sh/sh_io.h Normal file
View File

@@ -0,0 +1,48 @@
/*
* These are some macros to access memory mapped devices
* on the SH7000-architecture.
*
* Inspired from the linux kernel's include/asm/io.h
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1996-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _asm_io_h
#define _asm_io_h
#define readb(addr) (*(volatile unsigned char *) (addr))
#define readw(addr) (*(volatile unsigned short *) (addr))
#define readl(addr) (*(volatile unsigned int *) (addr))
#define read8(addr) (*(volatile unsigned8 *) (addr))
#define read16(addr) (*(volatile unsigned16 *) (addr))
#define read32(addr) (*(volatile unsigned32 *) (addr))
#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
#define write8(b,addr) ((*(volatile unsigned8 *) (addr)) = (b))
#define write16(b,addr) ((*(volatile unsigned16 *) (addr)) = (b))
#define write32(b,addr) ((*(volatile unsigned32 *) (addr)) = (b))
#define inb(addr) readb(addr)
#define outb(b,addr) writeb(b,addr)
#endif

67
c/src/exec/score/cpu/sh/shtypes.h Normal file
View File

@@ -0,0 +1,67 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_SH_TYPES_h
#define __CPU_SH_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned16 boolean; /* Boolean value, external */
/* data bus has 16 bits */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void sh_isr;
typedef void ( *sh_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif

15
c/src/lib/libbsp/sh/Makefile.in Normal file
View File

@@ -0,0 +1,15 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH=@srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
# Descend into the $(RTEMS_BSP_FAMILY) directory
SUB_DIRS=$(RTEMS_BSP_FAMILY)

22
c/src/lib/libbsp/sh/gensh1/Makefile.in Normal file
View File

@@ -0,0 +1,22 @@
#
# $Id $
#
@SET_MAKE@
srcdir = @srcdir@
VPATH=@srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
# wrapup is the one that actually builds and installs the library
# from the individual .rel files built in other directories
# was:
# SUB_DIRS=include startup clock console shmsupp timer wrapup
# is
SUB_DIRS=include \
startup \
wrapup

50
c/src/lib/libbsp/sh/gensh1/README Normal file
View File

@@ -0,0 +1,50 @@
#
# $Id$
#
# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
#
BSP NAME: generic SH1 (gensh1)
BOARD: n/a
BUS: n/a
CPU FAMILY: Hitachi SH
CPU: SH 7032
COPROCESSORS: none
MODE: n/a
DEBUG MONITOR: gdb
PERIPHERALS
===========
TIMERS: on-chip
RESOLUTION: cf. Hitachi SH 703X Hardware Manual (Phi/4)
SERIAL PORTS: on-chip (with 2 ports)
REAL-TIME CLOCK: none
DMA: not used
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: on-chip timer
IOSUPP DRIVER: default
SHMSUPP: default
TIMER DRIVER: on-chip timer
TTY DRIVER: /dev/null (stub)
STDIO
=====
PORT: /dev/null (stub)
ELECTRICAL: n/a
BAUD: n/a
BITS PER CHARACTER: n/a
PARITY: n/a
STOP BITS: n/a
NOTES
=====
(1) Only stub console driver available at the moment.
Driver for the on-chip serial devices (sci) will be available soon.

22
c/src/lib/libbsp/sh/gensh1/bsp_specs Normal file
View File

@@ -0,0 +1,22 @@
%rename cpp old_cpp
%rename lib old_lib
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*cpp:
%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
*lib:
%{!qrtems: %(old_lib)} \
%{qrtems: --start-group %{!qrtems_debug: -lrtemsall } %{qrtems_debug: -lrtemsall_g} \
-lc -lgcc --end-group \
%{!qnolinkcmds: -T linkcmds%s}}
*startfile:
%{!qrtems: %(old_startfile)} \
%{qrtems: %{qrtems_debug: start_g.o%s} %{!qrtems_debug: start.o%s}}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e _start}

37
c/src/lib/libbsp/sh/gensh1/include/Makefile.in Normal file
View File

@@ -0,0 +1,37 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH=@srcdir@
RTEMS_ROOT=@top_srcdir@
PROJECT_ROOT=@PROJECT_ROOT@
H_FILES = \
$(srcdir)/bsp.h \
$(srcdir)/coverhd.h
#
# Equate files are for including from assembly preprocessed by
# gm4 or gasp. No examples are provided except for those for
# other CPUs. The best way to generate them would be to
# provide a program which generates the constants used based
# on the C equivalents.
#
EQ_FILES =
SRCS=$(H_FILES) $(EQ_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: $(SRCS)
$(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)
$(INSTALL) -m 444 $(EQ_FILES) $(PROJECT_INCLUDE)
install: all

133
c/src/lib/libbsp/sh/gensh1/include/bsp.h Normal file
View File

@@ -0,0 +1,133 @@
/*
* This include file contains all board IO definitions.
*
* generic sh1
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __gensh1_h
#define __gensh1_h
#ifdef __cplusplus
extern "C" {
#endif
#define CPU_CONSOLE_DEVNAME "/dev/null"
#include <rtems.h>
#include <clockdrv.h>
#include <sh/null.h>
#include <console.h>
/*
* Define the time limits for RTEMS Test Suite test durations.
* Long test and short test duration limits are provided. These
* values are in seconds and need to be converted to ticks for the
* application.
*
*/
#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */
#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 0
#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
#define Cause_tm27_intr()
#define Clear_tm27_intr()
#define Lower_tm27_intr()
/* Constants */
#define MHZ 20
/*
* Defined in the linker script 'linkcmds'
*/
extern unsigned32 HeapStart ;
extern unsigned32 HeapEnd ;
extern unsigned32 WorkSpaceStart ;
extern unsigned32 WorkSpaceEnd ;
extern void *CPU_Interrupt_stack_low ;
extern void *CPU_Interrupt_stack_high ;
/* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration;
extern int bsp_start( int argc, char **argv, char **env );
extern void bsp_cleanup( void );
/*
* Device Driver Table Entries
*/
/*
* We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console
*/
#if defined(CONSOLE_DRIVER_TABLE_ENTRY)
#warning Overwriting CONSOLE_DRIVER_TABLE_ENTRY
#undef CONSOLE_DRIVER_TABLE_ENTRY
#endif
#define CONSOLE_DRIVER_TABLE_ENTRY \
DEVNULL_DRIVER_TABLE_ENTRY, \
{ console_initialize, console_open, console_close, \
console_read, console_write, console_control }
/*
* NOTE: Use the standard Clock driver entry
*/
/*
* How many libio files we want
*/
#define BSP_LIBIO_MAX_FDS 20
/*
* FIXME: Should this go to libcpu/sh/sh7032 ?
*/
/* functions */
sh_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
);
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

130
c/src/lib/libbsp/sh/gensh1/include/coverhd.h Normal file
View File

@@ -0,0 +1,130 @@
/* coverhd.h
*
* This include file has defines to represent the overhead associated
* with calling a particular directive from C. These are used in the
* Timing Test Suite to ignore the overhead required to pass arguments
* to directives. On some CPUs and/or target boards, this overhead
* is significant and makes it difficult to distinguish internal
* RTEMS execution time from that used to call the directive.
* This file should be updated after running the C overhead timing
* test. Once this update has been performed, the RTEMS Time Test
* Suite should be rebuilt to account for these overhead times in the
* timing results.
*
* NOTE: If these are all zero, then the times reported include all
* all calling overhead including passing of arguments.
*
*
* These are the figures tmoverhd.exe reported with egcs-980205 -O3
* on a Diesner OktagonSH/Amos-2.1 board with SH7032/20MHz
*
* These results are assumed to be applicable to most SH7032/20MHz boards
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __COVERHD_h
#define __COVERHD_h
#ifdef __cplusplus
extern "C" {
#endif
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4
#define CALLING_OVERHEAD_TASK_CREATE 9
#define CALLING_OVERHEAD_TASK_IDENT 6
#define CALLING_OVERHEAD_TASK_START 5
#define CALLING_OVERHEAD_TASK_RESTART 5
#define CALLING_OVERHEAD_TASK_DELETE 4
#define CALLING_OVERHEAD_TASK_SUSPEND 4
#define CALLING_OVERHEAD_TASK_RESUME 4
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5
#define CALLING_OVERHEAD_TASK_MODE 5
#define CALLING_OVERHEAD_TASK_GET_NOTE 5
#define CALLING_OVERHEAD_TASK_SET_NOTE 5
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 14
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4
#define CALLING_OVERHEAD_INTERRUPT_CATCH 5
#define CALLING_OVERHEAD_CLOCK_GET 16
#define CALLING_OVERHEAD_CLOCK_SET 14
#define CALLING_OVERHEAD_CLOCK_TICK 3
#define CALLING_OVERHEAD_TIMER_CREATE 4
#define CALLING_OVERHEAD_TIMER_IDENT 4
#define CALLING_OVERHEAD_TIMER_DELETE 4
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 20
#define CALLING_OVERHEAD_TIMER_RESET 4
#define CALLING_OVERHEAD_TIMER_CANCEL 4
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 7
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 5
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5
#define CALLING_OVERHEAD_EVENT_SEND 6
#define CALLING_OVERHEAD_EVENT_RECEIVE 5
#define CALLING_OVERHEAD_SIGNAL_CATCH 4
#define CALLING_OVERHEAD_SIGNAL_SEND 4
#define CALLING_OVERHEAD_PARTITION_CREATE 9
#define CALLING_OVERHEAD_PARTITION_IDENT 5
#define CALLING_OVERHEAD_PARTITION_DELETE 4
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 6
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 6
#define CALLING_OVERHEAD_REGION_CREATE 9
#define CALLING_OVERHEAD_REGION_IDENT 5
#define CALLING_OVERHEAD_REGION_DELETE 4
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 9
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5
#define CALLING_OVERHEAD_PORT_CREATE 9
#define CALLING_OVERHEAD_PORT_IDENT 4
#define CALLING_OVERHEAD_PORT_DELETE 4
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 7
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 8
#define CALLING_OVERHEAD_IO_INITIALIZE 5
#define CALLING_OVERHEAD_IO_OPEN 5
#define CALLING_OVERHEAD_IO_CLOSE 5
#define CALLING_OVERHEAD_IO_READ 5
#define CALLING_OVERHEAD_IO_WRITE 5
#define CALLING_OVERHEAD_IO_CONTROL 5
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

59
c/src/lib/libbsp/sh/gensh1/startup/Makefile.in Normal file
View File

@@ -0,0 +1,59 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH=@srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
PGM=${ARCH}/startup.rel
# C source names, if any, go here -- minus the .c
C_PIECES=bspstart bspclean sbrk setvec main
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_FILES=
# Assembly source names, if any, go here -- minus the .s
S_PIECES=
S_FILES=$(S_PIECES:%=%.s)
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
SRCS=linkcmds $(C_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${SRCS} ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(PGM)
$(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile

40
c/src/lib/libbsp/sh/gensh1/startup/bspclean.c Normal file
View File

@@ -0,0 +1,40 @@
/* bsp_cleanup()
*
* This routine normally is part of start.s and usually returns
* control to a monitor.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* You should have received a copy of the GNU General Public License
* along with this program; If not, write to the Free Software Foundation,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems.h>
#include <bsp.h>
void bsp_cleanup( void )
{
}

278
c/src/lib/libbsp/sh/gensh1/startup/bspstart.c Normal file
View File

@@ -0,0 +1,278 @@
/* bsp_start()
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <libcsupport.h>
#include <string.h>
#include <fcntl.h>
#ifdef STACK_CHECKER_ON
#include <stackchk.h>
#endif
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
char *rtems_progname;
/* Initialize whatever libc we are using
* called from postdriver hook
*/
void bsp_libc_init()
{
/*
* The last parameter to RTEMS_Malloc_Initialize is the "chunk"
* size which a multiple of will be requested on each sbrk()
* call by malloc(). A value of 0 indicates that sbrk() should
* not be called to extend the heap.
*/
RTEMS_Malloc_Initialize(&HeapStart, sizeof(unsigned32) * (&HeapEnd - &HeapStart), 0);
/*
* Init the RTEMS libio facility to provide UNIX-like system
* calls for use by newlib (ie: provide __rtems_open, __rtems_close, etc)
* Uses malloc() to get area for the iops, so must be after malloc init
*/
rtems_libio_init();
/*
* Set up for the libc handling.
*/
if (BSP_Configuration.ticks_per_timeslice > 0)
libc_init(1); /* reentrant if possible */
else
libc_init(0); /* non-reentrant */
}
/*
* Function: bsp_pretasking_hook
*
* Description:
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*
* NOTES:
* Must not use libc (to do io) from here, since drivers are
* not yet initialized.
*
*/
void
bsp_pretasking_hook(void)
{
bsp_libc_init();
#ifdef STACK_CHECKER_ON
/*
* Initialize the stack bounds checker
* We can either turn it on here or from the app.
*/
Stack_check_Initialize();
#endif
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
/*
* After drivers are setup, register some "filenames"
* and open stdin, stdout, stderr files
*
* Newlib will automatically associate the files with these
* (it hardcodes the numbers)
*/
void
bsp_postdriver_hook(void)
{
int stdin_fd, stdout_fd, stderr_fd;
int error_code;
error_code = 'S' << 24 | 'T' << 16;
if ((stdin_fd = __rtems_open("/dev/console", O_RDONLY, 0)) == -1)
rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' );
if ((stdout_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1)
rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' );
if ((stderr_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1)
rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' );
if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2))
rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' );
}
int bsp_start(
int argc,
char **argv,
char **environp
)
{
/*
For real boards you need to setup the hardware
and need to copy the vector table from rom to ram.
Depending on the board this can ether be done from inside the rom
startup code, rtems startup code or here.
*/
if ((argc > 0) && argv && argv[0])
rtems_progname = argv[0];
else
rtems_progname = "RTEMS";
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
/*
* Copy the Configuration Table .. so we can change it
*/
BSP_Configuration = Configuration;
/*
* Add 1 region for the RTEMS Malloc
*/
BSP_Configuration.RTEMS_api_configuration->maximum_regions++;
/*
* Add 1 extension for newlib libc
*/
#ifdef RTEMS_NEWLIB
BSP_Configuration.maximum_extensions++;
#endif
/*
* Add 1 extension for newlib libc
*/
#ifdef RTEMS_NEWLIB
BSP_Configuration.maximum_extensions++;
#endif
#ifdef STACK_CHECKER_ON
/*
* Add 1 extension for stack checker
*/
BSP_Configuration.maximum_extensions++;
#endif
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
BSP_Configuration.work_space_size =
(unsigned32) &WorkSpaceEnd -
(unsigned32) &WorkSpaceStart ;
/*
* initialize the CPU table for this BSP
*/
#if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE )
_CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low ;
_CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ;
/* This isn't used anywhere */
Cpu_table.interrupt_stack_size =
(unsigned32) (&CPU_Interrupt_stack_high) -
(unsigned32) (&CPU_Interrupt_stack_low) ;
#endif
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.predriver_hook = NULL;
Cpu_table.postdriver_hook = bsp_postdriver_hook;
Cpu_table.idle_task = NULL; /* do not override system IDLE task */
Cpu_table.do_zero_of_workspace = TRUE;
#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE )
Cpu_table.interrupt_stack_size = 4096;
#endif
Cpu_table.extra_mpci_receive_server_stack = 0;
/*
* Don't forget the other CPU Table entries.
*/
/*
* Tell libio how many fd's we want and allow it to tweak config
*/
rtems_libio_config(&BSP_Configuration, BSP_LIBIO_MAX_FDS);
/*
* Start RTEMS
*/
rtems_initialize_executive( &BSP_Configuration, &Cpu_table );
bsp_cleanup();
return 0;
}

203
c/src/lib/libbsp/sh/gensh1/startup/linkcmds Normal file
View File

@@ -0,0 +1,203 @@
/*
* This is an adapted linker script from egcs-1.0.1
*
* Memory layout for an SH 7032 with main memory in area 2
* This memory layout it very similar to that used for Hitachi's
* EVB with CMON in rom
*
* NOTE: The ram start address may vary, all other start addresses are fixed
* Not suiteable for gdb's simulator
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
OUTPUT_FORMAT("coff-sh")
OUTPUT_ARCH(sh)
ENTRY(_start)
MEMORY
{
rom : o = 0x00000000, l = 128k
onchip_peri : o = 0x05000000, l = 512
ram : o = 0x0A040000, l = 256k
onchip_ram : o = 0x0f000000, l = 8k
}
SECTIONS
{
/* boot vector table */
.monvects 0x00000000 (NOLOAD): {
_monvects = . ;
} > rom
/* monitor play area */
.monram 0x0A040000 (NOLOAD) :
{
_ramstart = .;
} > ram
/* monitor vector table */
.vects 0x0A042000 (NOLOAD) : {
_vectab = . ;
*(.vects);
}
/* Read-only sections, merged into text segment: */
. = 0x0a044000 ;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.text :
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
.rela.text :
{ *(.rela.text) *(.rela.gnu.linkonce.t*) }
.rel.data :
{ *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rela.data :
{ *(.rela.data) *(.rela.gnu.linkonce.d*) }
.rel.rodata :
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
.rela.rodata :
{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) } =0
.plt : { *(.plt) }
.text . :
{
*(.text)
*(.stub)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.fini . : { *(.fini) } =0
.rodata . : { *(.rodata) *(.gnu.linkonce.r*) }
.rodata1 . : { *(.rodata1) }
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data . :
{
*(.data)
*(.gnu.linkonce.d*)
CONSTRUCTORS
} > ram
.data1 . : { *(.data1) }
.ctors . :
{
___ctors = .;
*(.ctors)
___ctors_end = .;
}
.dtors . :
{
___dtors = .;
*(.dtors)
___dtors_end = .;
}
.got . : { *(.got.plt) *(.got) }
.dynamic . : { *(.dynamic) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata . : { *(.sdata) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.sbss . : { *(.sbss) *(.scommon) }
.bss . :
{
*(.dynbss)
*(.bss)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
_HeapStart = . ;
. = . + 1024 * 20 ;
PROVIDE( _HeapEnd = . );
_WorkSpaceStart = . ;
. = 0x0a080000 ;
PROVIDE(_WorkSpaceEnd = .);
_CPU_Interrupt_stack_low = 0x0f000000 ;
_CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.stack 0x0f001ff0 : { _stack = .; *(.stack) } > onchip_ram
/* These must appear regardless of . */
}

195
c/src/lib/libbsp/sh/gensh1/times Normal file
View File

@@ -0,0 +1,195 @@
#
# Timing Test Suite Results for the generic sh1
#
# NOTE: Due to memory shortage the timing test suite could not yet be run.
#
# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
#
# $Id$
#
Board: Diesner OktagonSH/AMOS-2.1
CPU: Hitachi SH 7032
Clock Speed: 20MHz
Memory Configuration: 8k on-chip ram, 256k external RAM in Area 4
Wait States:
Times Reported in: cycles, microseconds, etc
Timer Source: Count Down Timer, on-CPU cycle counter, etc
Column A:
Column B:
# DESCRIPTION A B
== ================================================================= ==== ====
1 rtems_semaphore_create X
rtems_semaphore_delete X
rtems_semaphore_obtain: available X
rtems_semaphore_obtain: not available -- NO_WAIT X
rtems_semaphore_release: no waiting tasks X
2 rtems_semaphore_obtain: not available -- caller blocks X
3 rtems_semaphore_release: task readied -- preempts caller X
4 rtems_task_restart: blocked task -- preempts caller X
rtems_task_restart: ready task -- preempts caller X
rtems_semaphore_release: task readied -- returns to caller X
rtems_task_create X
rtems_task_start X
rtems_task_restart: suspended task -- returns to caller X
rtems_task_delete: suspended task X
rtems_task_restart: ready task -- returns to caller X
rtems_task_restart: blocked task -- returns to caller X
rtems_task_delete: blocked task X
5 rtems_task_suspend: calling task X
rtems_task_resume: task readied -- preempts caller X
6 rtems_task_restart: calling task X
rtems_task_suspend: returns to caller X
rtems_task_resume: task readied -- returns to caller X
rtems_task_delete: ready task X
7 rtems_task_restart: suspended task -- preempts caller X
8 rtems_task_set_priority: obtain current priority X
rtems_task_set_priority: returns to caller X
rtems_task_mode: obtain current mode X
rtems_task_mode: no reschedule X
rtems_task_mode: reschedule -- returns to caller X
rtems_task_mode: reschedule -- preempts caller X
rtems_task_set_note X
rtems_task_get_note X
rtems_clock_set X
rtems_clock_get X
9 rtems_message_queue_create X
rtems_message_queue_send: no waiting tasks X
rtems_message_queue_urgent: no waiting tasks X
rtems_message_queue_receive: available X
rtems_message_queue_flush: no messages flushed X
rtems_message_queue_flush: messages flushed X
rtems_message_queue_delete X
10 rtems_message_queue_receive: not available -- NO_WAIT X
rtems_message_queue_receive: not available -- caller blocks X
11 rtems_message_queue_send: task readied -- preempts caller X
12 rtems_message_queue_send: task readied -- returns to caller X
13 rtems_message_queue_urgent: task readied -- preempts caller X
14 rtems_message_queue_urgent: task readied -- returns to caller X
15 rtems_event_receive: obtain current events X
rtems_event_receive: not available -- NO_WAIT X
rtems_event_receive: not available -- caller blocks X
rtems_event_send: no task readied X
rtems_event_receive: available X
rtems_event_send: task readied -- returns to caller X
16 rtems_event_send: task readied -- preempts caller X
17 rtems_task_set_priority: preempts caller X
18 rtems_task_delete: calling task X
19 rtems_signal_catch X
rtems_signal_send: returns to caller X
rtems_signal_send: signal to self X
exit ASR overhead: returns to calling task X
exit ASR overhead: returns to preempting task X
20 rtems_partition_create X
rtems_region_create X
rtems_partition_get_buffer: available X
rtems_partition_get_buffer: not available X
rtems_partition_return_buffer X
rtems_partition_delete X
rtems_region_get_segment: available X
rtems_region_get_segment: not available -- NO_WAIT X
rtems_region_return_segment: no waiting tasks X
rtems_region_get_segment: not available -- caller blocks X
rtems_region_return_segment: task readied -- preempts caller X
rtems_region_return_segment: task readied -- returns to caller X
rtems_region_delete X
rtems_io_initialize X
rtems_io_open X
rtems_io_close X
rtems_io_read X
rtems_io_write X
rtems_io_control X
21 rtems_task_ident X
rtems_message_queue_ident X
rtems_semaphore_ident X
rtems_partition_ident X
rtems_region_ident X
rtems_port_ident X
rtems_timer_ident X
rtems_rate_monotonic_ident X
22 rtems_message_queue_broadcast: task readied -- returns to caller X
rtems_message_queue_broadcast: no waiting tasks X
rtems_message_queue_broadcast: task readied -- preempts caller X
23 rtems_timer_create X
rtems_timer_fire_after: inactive X
rtems_timer_fire_after: active X
rtems_timer_cancel: active X
rtems_timer_cancel: inactive X
rtems_timer_reset: inactive X
rtems_timer_reset: active X
rtems_timer_fire_when: inactive X
rtems_timer_fire_when: active X
rtems_timer_delete: active X
rtems_timer_delete: inactive X
rtems_task_wake_when X
24 rtems_task_wake_after: yield -- returns to caller X
rtems_task_wake_after: yields -- preempts caller X
25 rtems_clock_tick X
26 _ISR_Disable X
_ISR_Flash X
_ISR_Enable X
_Thread_Disable_dispatch X
_Thread_Enable_dispatch X
_Thread_Set_state X
_Thread_Disptach (NO FP) X
context switch: no floating point contexts X
context switch: self X
context switch: to another task X
context switch: restore 1st FP task X
fp context switch: save idle, restore idle X
fp context switch: save idle, restore initialized X
fp context switch: save initialized, restore initialized X
_Thread_Resume X
_Thread_Unblock X
_Thread_Ready X
_Thread_Get X
_Semaphore_Get X
_Thread_Get: invalid id X
27 interrupt entry overhead: returns to interrupted task X
interrupt exit overhead: returns to interrupted task X
interrupt entry overhead: returns to nested interrupt X
interrupt exit overhead: returns to nested interrupt X
interrupt entry overhead: returns to preempting task X
interrupt exit overhead: returns to preempting task X
28 rtems_port_create X
rtems_port_external_to_internal X
rtems_port_internal_to_external X
rtems_port_delete X
29 rtems_rate_monotonic_create X
rtems_rate_monotonic_period: initiate period -- returns to caller X
rtems_rate_monotonic_period: obtain status X
rtems_rate_monotonic_cancel X
rtems_rate_monotonic_delete: inactive X
rtems_rate_monotonic_delete: active X
rtems_rate_monotonic_period: conclude periods -- caller blocks X

64
c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in Normal file
View File

@@ -0,0 +1,64 @@
#
# $Id $
#
# $Id$
#
# build and install libbsp
#
@SET_MAKE@
srcdir = @srcdir@
VPATH=@srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
BSP_PIECES=startup
GENERIC_PIECES=
# pieces to pick up out of libcpu/sh
CPU_PIECES=\
sh7032/null \
sh7032/clock \
sh7032/console \
sh7032/timer
# bummer; have to use $foreach since % pattern subst rules only replace 1x
OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \
$(foreach piece, $(CPU_PIECES), \
../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(notdir $(piece)).rel) \
$(foreach piece, $(GENERIC_PIECES), ../../../../$(piece)/$(ARCH)/$(piece).rel)
LIB=$(ARCH)/libbsp.a
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/lib.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
$(LIB): ${OBJS}
$(make-library)
all: ${ARCH} $(SRCS) $(LIB)
$(INSTALL_VARIANT) -m 644 $(LIB) ${PROJECT_RELEASE}/lib
install: all

311
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c Normal file
View File

@@ -0,0 +1,311 @@
/*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language
*
* NOTE: This port uses a C file with inline assembler instructions
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" cpu_asm file. An
* implementation in assembly should include "cpu_asm.h"
*/
#include <rtems/system.h>
#include <rtems/score/cpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/thread.h>
#include <rtems/score/cpu_isps.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/sh.h>
#include <rtems/score/iosh7030.h>
/* from cpu_isps.c */
extern proc_ptr _Hardware_isr_Table[];
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("r15");
/*
* sh_set_irq_priority
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
unsigned32 shiftcount;
unsigned32 prioreg;
unsigned16 temp16;
unsigned32 level;
/*
* first check for valid interrupt
*/
if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
return -1;
/*
* check for valid irq priority
*/
if( prio > 15 )
return -1;
/*
* look up appropriate interrupt priority register
*/
if( irq > 71)
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
case 1: { prioreg = INTC_IPRD; break;}
case 2: { prioreg = INTC_IPRE; break;}
default: return -1;
}
}
else
{
shiftcount = 12 - 4 * ( irq % 4);
if( irq > 67)
prioreg = INTC_IPRB;
else
prioreg = INTC_IPRA;
}
/*
* Set the interrupt priority register
*/
_CPU_ISR_Disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_CPU_ISR_Enable( level );
return 0;
}
/*
* _CPU_Context_save_fp_context
*
* This routine is responsible for saving the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
)
{
}
/*
* _CPU_Context_restore_fp_context
*
* This routine is responsible for restoring the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
)
{
}
/* _CPU_Context_switch
*
* This routine performs a normal non-FP context switch.
*/
/* within __CPU_Context_switch:
* _CPU_Context_switch
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: It should be safe not to store r4, r5
*
* NOTE: It is doubtful if r0 is really needed to be stored
*
* NOTE: gbr is added, but should not be necessary, as it is
* only used globally in this port.
*/
/*
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* the offset each time Context_Control is changed
*/
void __CPU_Context_switch(
Context_Control *run, /* r4 */
Context_Control *heir /* r5 */
)
{
asm volatile("
.global __CPU_Context_switch
__CPU_Context_switch:
add %0,r4
stc.l sr,@-r4
stc.l gbr,@-r4
mov.l r0,@-r4
mov.l r1,@-r4
mov.l r2,@-r4
mov.l r3,@-r4
mov.l r6,@-r4
mov.l r7,@-r4
mov.l r8,@-r4
mov.l r9,@-r4
mov.l r10,@-r4
mov.l r11,@-r4
mov.l r12,@-r4
mov.l r13,@-r4
mov.l r14,@-r4
sts.l pr,@-r4
sts.l mach,@-r4
sts.l macl,@-r4
mov.l r15,@-r4
mov r5, r4"
:: "I" (sizeof(Context_Control))
);
asm volatile("
.global __CPU_Context_restore
__CPU_Context_restore:
mov.l @r4+,r15
lds.l @r4+,macl
lds.l @r4+,mach
lds.l @r4+,pr
mov.l @r4+,r14
mov.l @r4+,r13
mov.l @r4+,r12
mov.l @r4+,r11
mov.l @r4+,r10
mov.l @r4+,r9
mov.l @r4+,r8
mov.l @r4+,r7
mov.l @r4+,r6
mov.l @r4+,r3
mov.l @r4+,r2
mov.l @r4+,r1
mov.l @r4+,r0
ldc.l @r4+,gbr
ldc.l @r4+,sr
rts
nop" );
}
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( unsigned32 vector)
{
register unsigned32 level;
_CPU_ISR_Disable( level );
_Thread_Dispatch_disable_level++;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0 )
{
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high;
}
#endif
_ISR_Nest_level++;
_CPU_ISR_Enable( level );
/* call isp */
if( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_CPU_ISR_Disable( level );
_ISR_Nest_level--;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
#endif
_Thread_Dispatch_disable_level--;
_CPU_ISR_Enable( level );
if ( _Thread_Dispatch_disable_level == 0 )
{
if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
{
_ISR_Signals_to_thread_executing = FALSE;
_Thread_Dispatch();
}
}
}

252
c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c Normal file
View File

@@ -0,0 +1,252 @@
/*
* This file contains the isp frames for the user interrupts.
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/shtypes.h>
#include <rtems/score/cpu_isps.h>
/*
* This is a exception vector table
*
* It has the same structure like the actual vector table (vectab)
*/
proc_ptr _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
/* irq 64 ... */
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
_wdt_isp,
/* 113 */ _dref_isp
};
#define Str(a)#a
/*
* Some versions of gcc and all version of egcs at least until egcs-1.0.2
* are not able to handle #praga interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
#define isp( name, number, func)\
asm (".global _"Str(name)"\n\t" \
"_"Str(name)": \n\t" \
" mov.l r0,@-r15 \n\t" \
" mov.l r1,@-r15 \n\t" \
" mov.l r2,@-r15 \n\t" \
" mov.l r3,@-r15 \n\t" \
" mov.l r4,@-r15 \n\t" \
" mov.l r5,@-r15 \n\t" \
" mov.l r6,@-r15 \n\t" \
" mov.l r7,@-r15 \n\t" \
" mov.l r14,@-r15 \n\t" \
" sts.l pr,@-r15 \n\t" \
" sts.l mach,@-r15 \n\t" \
" sts.l macl,@-r15 \n\t" \
" mov r15,r14 \n\t" \
" mov.l "Str(name)"_k, r1\n\t" \
" jsr @r1 \n\t" \
" mov #"Str(number)", r4\n\t" \
" mov r14,r15 \n\t" \
" lds.l @r15+,macl \n\t" \
" lds.l @r15+,mach \n\t" \
" lds.l @r15+,pr \n\t" \
" mov.l @r15+,r14 \n\t" \
" mov.l @r15+,r7 \n\t" \
" mov.l @r15+,r6 \n\t" \
" mov.l @r15+,r5 \n\t" \
" mov.l @r15+,r4 \n\t" \
" mov.l @r15+,r3 \n\t" \
" mov.l @r15+,r2 \n\t" \
" mov.l @r15+,r1 \n\t" \
" mov.l @r15+,r0 \n\t" \
" rte \n\t" \
" nop \n\t" \
" .align 2 \n\t" \
#name"_k: \n\t" \
".long "Str(func));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
asm(" .section .text
.global __dummy_isp
__dummy_isp:
mov.l r14,@-r15
mov r15, r14
trapa #34
mov.l @r15+,r14
rte
nop");
/*****************************
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Interrupt timer unit
*****************************/
/*****************************
* Timer 0
*****************************/
isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler);
/*****************************
* Timer 1
*****************************/
isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler);
/*****************************
* Timer 2
*****************************/
isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler);
/*****************************
* Timer 3
*****************************/
isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler);
/*****************************
* Timer 4
*****************************/
isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
*****************************/
/*****************************
* Serial interface 0
*****************************/
isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
/*****************************
* Serial interface 1
*****************************/
isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
*****************************/
isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
/******************************
* Analog digital converter
* ADC
******************************/
isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);

311
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c Normal file
View File

@@ -0,0 +1,311 @@
/*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language
*
* NOTE: This port uses a C file with inline assembler instructions
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" cpu_asm file. An
* implementation in assembly should include "cpu_asm.h"
*/
#include <rtems/system.h>
#include <rtems/score/cpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/thread.h>
#include <rtems/score/cpu_isps.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/sh.h>
#include <rtems/score/iosh7030.h>
/* from cpu_isps.c */
extern proc_ptr _Hardware_isr_Table[];
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("r15");
/*
* sh_set_irq_priority
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
unsigned32 shiftcount;
unsigned32 prioreg;
unsigned16 temp16;
unsigned32 level;
/*
* first check for valid interrupt
*/
if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
return -1;
/*
* check for valid irq priority
*/
if( prio > 15 )
return -1;
/*
* look up appropriate interrupt priority register
*/
if( irq > 71)
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
case 1: { prioreg = INTC_IPRD; break;}
case 2: { prioreg = INTC_IPRE; break;}
default: return -1;
}
}
else
{
shiftcount = 12 - 4 * ( irq % 4);
if( irq > 67)
prioreg = INTC_IPRB;
else
prioreg = INTC_IPRA;
}
/*
* Set the interrupt priority register
*/
_CPU_ISR_Disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_CPU_ISR_Enable( level );
return 0;
}
/*
* _CPU_Context_save_fp_context
*
* This routine is responsible for saving the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
)
{
}
/*
* _CPU_Context_restore_fp_context
*
* This routine is responsible for restoring the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
)
{
}
/* _CPU_Context_switch
*
* This routine performs a normal non-FP context switch.
*/
/* within __CPU_Context_switch:
* _CPU_Context_switch
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: It should be safe not to store r4, r5
*
* NOTE: It is doubtful if r0 is really needed to be stored
*
* NOTE: gbr is added, but should not be necessary, as it is
* only used globally in this port.
*/
/*
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* the offset each time Context_Control is changed
*/
void __CPU_Context_switch(
Context_Control *run, /* r4 */
Context_Control *heir /* r5 */
)
{
asm volatile("
.global __CPU_Context_switch
__CPU_Context_switch:
add %0,r4
stc.l sr,@-r4
stc.l gbr,@-r4
mov.l r0,@-r4
mov.l r1,@-r4
mov.l r2,@-r4
mov.l r3,@-r4
mov.l r6,@-r4
mov.l r7,@-r4
mov.l r8,@-r4
mov.l r9,@-r4
mov.l r10,@-r4
mov.l r11,@-r4
mov.l r12,@-r4
mov.l r13,@-r4
mov.l r14,@-r4
sts.l pr,@-r4
sts.l mach,@-r4
sts.l macl,@-r4
mov.l r15,@-r4
mov r5, r4"
:: "I" (sizeof(Context_Control))
);
asm volatile("
.global __CPU_Context_restore
__CPU_Context_restore:
mov.l @r4+,r15
lds.l @r4+,macl
lds.l @r4+,mach
lds.l @r4+,pr
mov.l @r4+,r14
mov.l @r4+,r13
mov.l @r4+,r12
mov.l @r4+,r11
mov.l @r4+,r10
mov.l @r4+,r9
mov.l @r4+,r8
mov.l @r4+,r7
mov.l @r4+,r6
mov.l @r4+,r3
mov.l @r4+,r2
mov.l @r4+,r1
mov.l @r4+,r0
ldc.l @r4+,gbr
ldc.l @r4+,sr
rts
nop" );
}
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( unsigned32 vector)
{
register unsigned32 level;
_CPU_ISR_Disable( level );
_Thread_Dispatch_disable_level++;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0 )
{
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high;
}
#endif
_ISR_Nest_level++;
_CPU_ISR_Enable( level );
/* call isp */
if( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_CPU_ISR_Disable( level );
_ISR_Nest_level--;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
#endif
_Thread_Dispatch_disable_level--;
_CPU_ISR_Enable( level );
if ( _Thread_Dispatch_disable_level == 0 )
{
if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
{
_ISR_Signals_to_thread_executing = FALSE;
_Thread_Dispatch();
}
}
}

137
cpukit/score/cpu/sh/asm.h Normal file
View File

@@ -0,0 +1,137 @@
/* asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_SH_ASM_h
#define __CPU_SH_ASM_h
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#ifndef ASM
#define ASM
#endif
#include <rtems/score/targopts.h>
#include <rtems/score/sh.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
#define r0 REG (r0)
#define r1 REG (r1)
#define r2 REG (r2)
#define r3 REG (r3)
#define r4 REG (r4)
#define r5 REG (r5)
#define r6 REG (r6)
#define r7 REG (r7)
#define r8 REG (r8)
#define r9 REG (r9)
#define r10 REG (r10)
#define r11 REG (r11)
#define r12 REG (r12)
#define r13 REG (r13)
#define r14 REG (r14)
#define r15 REG (r15)
#define vbr REG (vbr)
#define gbr REG (gbr)
#define pr REG (pr)
#define mach REG (mach)
#define macl REG (macl)
#define sr REG (sr)
#define pc REG (pc)
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .global SYM (sym)
#define EXTERN(sym) .global SYM (sym)
#endif

232
cpukit/score/cpu/sh/cpu.c Normal file
View File

@@ -0,0 +1,232 @@
/*
* This file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/cpu.h>
#include <rtems/score/sh.h>
/* referenced in start.s */
extern proc_ptr vectab[] ;
proc_ptr vectab[256] ;
extern proc_ptr _Hardware_isr_Table[];
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS:
* cpu_table - CPU table to initialize
* thread_dispatch - address of disptaching routine
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch) /* ignored on this CPU */
)
{
register unsigned32 level = 0;
/*
* The thread_dispatch argument is the address of the entry point
* for the routine called at the end of an ISR once it has been
* decided a context switch is necessary. On some compilation
* systems it is difficult to call a high-level language routine
* from assembly. This allows us to trick these systems.
*
* If you encounter this problem save the entry point in a CPU
* dependent variable.
*/
_CPU_Thread_dispatch_pointer = thread_dispatch;
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
_CPU_Table = *cpu_table;
/* enable interrupts */
_CPU_ISR_Set_level( level);
}
/*PAGE
*
* _CPU_ISR_Get_level
*/
unsigned32 _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
*/
register unsigned32 _mask ;
sh_get_interrupt_level( _mask );
return ( _mask);
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/*
* This is where we install the interrupt handler into the "raw" interrupt
* table used by the CPU to dispatch interrupt handlers.
*/
volatile proc_ptr *vbr ;
#if SH_PARANOID_ISR
unsigned32 level ;
sh_disable_interrupts( level );
#endif
/* get vbr */
asm ( "stc vbr,%0" : "=r" (vbr) );
*old_handler = vbr[vector] ;
vbr[vector] = new_handler ;
#if SH_PARANOID_ISR
sh_enable_interrupts( level );
#endif
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
proc_ptr ignored ;
if(( vector <= 113) && ( vector >= 11))
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* If the interrupt vector table is a table of pointer to isr entry
* points, then we need to install the appropriate RTEMS interrupt
* handler for this vector number.
*/
_CPU_ISR_install_raw_handler(vector,
_Hardware_isr_Table[vector],
&ignored );
/*
* We put the actual user ISR address in '_ISR_Vector_table'.
* This will be used by __ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
}
/*PAGE
*
* _CPU_Thread_Idle_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*/
#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
void _CPU_Thread_Idle_body( void )
{
for( ; ; )
{
asm volatile("nop");
}
/* insert your "halt" instruction here */ ;
}
#endif
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
unsigned8 _bit_set_table[16] =
{ 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
#endif
void _CPU_Context_Initialize(
Context_Control *_the_context,
void *_stack_base,
unsigned32 _size,
unsigned32 _isr,
void (*_entry_point)(void),
int _is_fp )
{
_the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
_the_context->sr = (_isr << 4) & 0x00f0 ;
_the_context->pr = (unsigned32*) _entry_point ;
}

137
cpukit/score/cpu/sh/rtems/asm.h Normal file
View File

@@ -0,0 +1,137 @@
/* asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_SH_ASM_h
#define __CPU_SH_ASM_h
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#ifndef ASM
#define ASM
#endif
#include <rtems/score/targopts.h>
#include <rtems/score/sh.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
#define r0 REG (r0)
#define r1 REG (r1)
#define r2 REG (r2)
#define r3 REG (r3)
#define r4 REG (r4)
#define r5 REG (r5)
#define r6 REG (r6)
#define r7 REG (r7)
#define r8 REG (r8)
#define r9 REG (r9)
#define r10 REG (r10)
#define r11 REG (r11)
#define r12 REG (r12)
#define r13 REG (r13)
#define r14 REG (r14)
#define r15 REG (r15)
#define vbr REG (vbr)
#define gbr REG (gbr)
#define pr REG (pr)
#define mach REG (mach)
#define macl REG (macl)
#define sr REG (sr)
#define pc REG (pc)
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .global SYM (sym)
#define EXTERN(sym) .global SYM (sym)
#endif