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2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>

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PR 1573/cpukit
	* mpc5xx/irq/irq.c, mpc5xx/irq/irq_asm.S,
	new-exceptions/bspsupport/ppc_exc.S,
	new-exceptions/bspsupport/ppc_exc_asm_macros.h,
	new-exceptions/bspsupport/ppc_exc_hdl.c: Add a per cpu data structure
	which contains the information required by RTEMS for each CPU core.
	This encapsulates information such as thread executing, heir, idle
	and dispatch needed.
This commit is contained in:
Joel Sherrill
2010-06-29 00:39:39 +00:00
parent da4d03d084
commit 5048a0a0b8
6 changed files with 32 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc.S
View File

@@ -13,6 +13,10 @@
*/
/* Load macro definitions */
#include <rtems/asm.h>
#include <rtems/system.h>
#include <rtems/score/percpu.h>
#include "ppc_exc_asm_macros.h"
/******************************************************/

10
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h
View File

@@ -422,11 +422,12 @@ wrap_no_save_frame_register_\_FLVR:
*/
/* Increment ISR nest level and thread dispatch disable level */
lwz SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
lis SCRATCH_REGISTER_2, ISR_NEST_LEVEL@ha
lwz SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
lwz SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
addi SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1
addi SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1
stw SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
stw SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
stw SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
/*
@@ -612,11 +613,12 @@ wrap_handler_done_\_FLVR:
*/
/* Decrement ISR nest level and thread dispatch disable level */
lwz SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
lis SCRATCH_REGISTER_2, ISR_NEST_LEVEL@ha
lwz SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
lwz SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
subi SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1
subic. SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1
stw SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
stw SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
stw SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
/* Branch to skip thread dispatching */

13
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c
View File

@@ -86,18 +86,5 @@ void ppc_exc_wrapup(BSP_Exception_frame *frame)
* interrupts around the execution of _Thread_Dispatch();
*/
_Thread_Dispatch();
} else if ( _ISR_Signals_to_thread_executing ) {
_ISR_Signals_to_thread_executing = 0;
/*
* Process pending signals that have not already been
* processed by _Thread_Dispatch. This happens quite
* unfrequently : the ISR must have posted an action
* to the current running thread.
*/
if ( _Thread_Do_post_task_switch_extension ||
_Thread_Executing->do_post_task_switch_extension ) {
_Thread_Executing->do_post_task_switch_extension = false;
_API_extensions_Run_postswitch();
}
}
}