forked from Imagelibrary/rtems
2011-10-17 Sebastian Huber <sebastian.huber@embedded-brains.de>
* include/start-config.h, make/custom/lpc24xx_plx800_rom_int.cfg, startup/linkcmds.lpc24xx_plx800_rom_int, startup/start-config-emc-dynamic.c, startup/start-config-emc-static.c, startup/start-config-pinsel.c: New files. * Makefile.am, configure.ac, preinstall.am: Reflect changes above. * startup/bspstarthooks.c: Use configuration tables for EMC initialization.
This commit is contained in:
Sebastian Huber
@@ -1,3 +1,13 @@
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2011-10-17 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* include/start-config.h, make/custom/lpc24xx_plx800_rom_int.cfg,
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startup/linkcmds.lpc24xx_plx800_rom_int,
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startup/start-config-emc-dynamic.c, startup/start-config-emc-static.c,
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startup/start-config-pinsel.c: New files.
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* Makefile.am, configure.ac, preinstall.am: Reflect changes above.
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* startup/bspstarthooks.c: Use configuration tables for EMC
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initialization.
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2011-08-08 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* irq/irq-dispatch.c: New file.
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@@ -39,16 +39,17 @@ include_bsp_HEADERS += ../shared/lpc/include/lpc-i2s.h
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include_bsp_HEADERS += ../shared/lpc/include/lpc-emc.h
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include_bsp_HEADERS += ../shared/lpc/include/lpc-dma.h
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include_bsp_HEADERS += ../shared/lpc/include/lpc-lcd.h
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include_bsp_HEADERS += include/irq.h
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include_bsp_HEADERS += include/lpc24xx.h
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include_bsp_HEADERS += include/system-clocks.h
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include_bsp_HEADERS += include/ssp.h
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include_bsp_HEADERS += include/dma.h
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include_bsp_HEADERS += include/i2c.h
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include_bsp_HEADERS += include/io.h
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include_bsp_HEADERS += include/irq.h
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include_bsp_HEADERS += include/lcd.h
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include_bsp_HEADERS += include/lpc24xx.h
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include_bsp_HEADERS += include/lpc-clock-config.h
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include_bsp_HEADERS += include/lpc-ethernet-config.h
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include_bsp_HEADERS += include/ssp.h
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include_bsp_HEADERS += include/start-config.h
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include_bsp_HEADERS += include/system-clocks.h
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include_HEADERS += ../../shared/include/tm27.h
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@@ -63,12 +64,14 @@ libbspstart_a_SOURCES = ../shared/start/start.S
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project_lib_DATA = start.$(OBJEXT)
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project_lib_DATA += startup/linkcmds
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EXTRA_DIST = startup/linkcmds.lpc24xx_ea
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EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_int
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EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext
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EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram
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EXTRA_DIST =
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EXTRA_DIST += startup/linkcmds.lpc2362
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EXTRA_DIST += startup/linkcmds.lpc23xx_tli800
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EXTRA_DIST += startup/linkcmds.lpc24xx_ea
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EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_ram
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EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_ext
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EXTRA_DIST += startup/linkcmds.lpc24xx_ncs_rom_int
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EXTRA_DIST += startup/linkcmds.lpc24xx_plx800_rom_int
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###############################################################################
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# LibBSP #
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@@ -142,6 +145,9 @@ libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
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# Start hooks
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libbsp_a_SOURCES += startup/bspstarthooks.c
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libbsp_a_SOURCES += startup/start-config-emc-dynamic.c
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libbsp_a_SOURCES += startup/start-config-emc-static.c
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libbsp_a_SOURCES += startup/start-config-pinsel.c
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###############################################################################
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# Network #
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@@ -33,6 +33,7 @@ RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768U])
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RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
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RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc23*],[58982400U])
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RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[lpc24xx_plx800*],[51612800U])
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RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000U])
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RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz])
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@@ -43,12 +44,16 @@ RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc24xx_ea],[1])
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RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[*],[])
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RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[enable RMII for Ethernet])
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RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc24xx_plx800_rom_*],[1])
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RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc24xx_ncs_rom_*],[1])
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RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MICRON],[enable Micron configuration for EMC])
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RTEMS_BSPOPTS_SET([LPC24XX_EMC_NUMONYX],[lpc24xx_ncs_rom_*],[1])
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RTEMS_BSPOPTS_HELP([LPC24XX_EMC_NUMONYX],[enable Numonyx configuration for EMC])
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RTEMS_BSPOPTS_SET([LPC24XX_EMC_W9825G2JB],[lpc24xx_plx800_rom_*],[1])
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RTEMS_BSPOPTS_HELP([LPC24XX_EMC_W9825G2JB],[enable Winbond W9825G2JB configuration for EMC])
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RTEMS_BSPOPTS_SET([LPC24XX_EMC_TEST],[*],[])
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RTEMS_BSPOPTS_HELP([LPC24XX_EMC_TEST],[enable tests for EMC])
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98
c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
Normal file
98
c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
Normal file
@@ -0,0 +1,98 @@
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/**
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* @file
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*
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* @ingroup lpc24xx
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*
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* @brief BSP start configuration.
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*/
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/*
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* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#ifndef LIBBSP_ARM_LPC24XX_START_CONFIG_H
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#define LIBBSP_ARM_LPC24XX_START_CONFIG_H
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#include <bsp.h>
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#include <bsp/start.h>
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#include <bsp/lpc-emc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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typedef struct {
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uint32_t refresh;
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uint32_t readconfig;
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uint32_t trp;
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uint32_t tras;
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uint32_t tsrex;
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uint32_t tapr;
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uint32_t tdal;
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uint32_t twr;
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uint32_t trc;
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uint32_t trfc;
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uint32_t txsr;
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uint32_t trrd;
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uint32_t tmrd;
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} lpc24xx_emc_dynamic_config;
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typedef struct {
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volatile lpc_emc_dynamic *chip_select;
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uint32_t address;
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uint32_t config;
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uint32_t rascas;
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uint32_t mode;
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} lpc24xx_emc_dynamic_chip_config;
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typedef struct {
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volatile lpc_emc_static *chip_select;
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struct {
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uint32_t config;
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uint32_t waitwen;
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uint32_t waitoen;
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uint32_t waitrd;
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uint32_t waitpage;
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uint32_t waitwr;
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uint32_t waitrun;
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} config;
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} lpc24xx_emc_static_chip_config;
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extern const BSP_START_DATA_SECTION uint32_t
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lpc24xx_start_config_pinsel_5_9 [];
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extern const BSP_START_DATA_SECTION size_t
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lpc24xx_start_config_pinsel_5_9_size;
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extern const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
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lpc24xx_start_config_emc_dynamic [];
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extern const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
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lpc24xx_start_config_emc_dynamic_chip [];
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extern const BSP_START_DATA_SECTION size_t
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lpc24xx_start_config_emc_dynamic_chip_count;
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extern const BSP_START_DATA_SECTION lpc24xx_emc_static_chip_config
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lpc24xx_start_config_emc_static_chip [];
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extern const BSP_START_DATA_SECTION size_t
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lpc24xx_start_config_emc_static_chip_count;
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_LPC24XX_START_CONFIG_H */
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@@ -0,0 +1,7 @@
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#
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# Config file for LPC24XX (PLX800).
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#
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# $Id$
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#
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include $(RTEMS_ROOT)/make/custom/lpc24xx.inc
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@@ -101,22 +101,6 @@ $(PROJECT_INCLUDE)/bsp/lpc-lcd.h: ../shared/lpc/include/lpc-lcd.h $(PROJECT_INCL
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-lcd.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-lcd.h
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$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
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$(PROJECT_INCLUDE)/bsp/lpc24xx.h: include/lpc24xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc24xx.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc24xx.h
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$(PROJECT_INCLUDE)/bsp/system-clocks.h: include/system-clocks.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/system-clocks.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/system-clocks.h
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$(PROJECT_INCLUDE)/bsp/ssp.h: include/ssp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ssp.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ssp.h
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$(PROJECT_INCLUDE)/bsp/dma.h: include/dma.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/dma.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/dma.h
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@@ -129,10 +113,18 @@ $(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h
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$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
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$(PROJECT_INCLUDE)/bsp/lcd.h: include/lcd.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lcd.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lcd.h
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$(PROJECT_INCLUDE)/bsp/lpc24xx.h: include/lpc24xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc24xx.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc24xx.h
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$(PROJECT_INCLUDE)/bsp/lpc-clock-config.h: include/lpc-clock-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
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@@ -141,6 +133,18 @@ $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h: include/lpc-ethernet-config.h $(PR
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
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$(PROJECT_INCLUDE)/bsp/ssp.h: include/ssp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ssp.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ssp.h
|
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$(PROJECT_INCLUDE)/bsp/start-config.h: include/start-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start-config.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start-config.h
|
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|
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$(PROJECT_INCLUDE)/bsp/system-clocks.h: include/system-clocks.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/system-clocks.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/system-clocks.h
|
||||
|
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$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
|
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
|
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
|
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@@ -27,286 +27,141 @@
|
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#include <bsp/linker-symbols.h>
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#include <bsp/lpc24xx.h>
|
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#include <bsp/lpc-emc.h>
|
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#include <bsp/start-config.h>
|
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|
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#if defined(LPC24XX_EMC_MICRON) || defined(LPC24XX_EMC_NUMONYX)
|
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#define LPC24XX_EMC_INIT
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#endif
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static void BSP_START_TEXT_SECTION lpc24xx_cpu_delay(unsigned ticks)
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{
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unsigned i = 0;
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|
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static volatile lpc_emc *const emc = (lpc_emc *) EMC_BASE_ADDR;
|
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/* One loop execution needs four instructions */
|
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ticks /= 4;
|
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|
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typedef struct {
|
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uint32_t refresh;
|
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uint32_t readconfig;
|
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uint32_t trp;
|
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uint32_t tras;
|
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uint32_t tsrex;
|
||||
uint32_t tapr;
|
||||
uint32_t tdal;
|
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uint32_t twr;
|
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uint32_t trc;
|
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uint32_t trfc;
|
||||
uint32_t txsr;
|
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uint32_t trrd;
|
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uint32_t tmrd;
|
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} lpc24xx_emc_dynamic_config;
|
||||
|
||||
typedef struct {
|
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uint32_t config;
|
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uint32_t rascas;
|
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uint32_t mode;
|
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} lpc24xx_emc_dynamic_chip_config;
|
||||
|
||||
typedef struct {
|
||||
uint32_t config;
|
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uint32_t waitwen;
|
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uint32_t waitoen;
|
||||
uint32_t waitrd;
|
||||
uint32_t waitpage;
|
||||
uint32_t waitwr;
|
||||
uint32_t waitrun;
|
||||
} lpc24xx_emc_static_chip_config;
|
||||
|
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#ifdef LPC24XX_EMC_MICRON
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_ram_test_32(void)
|
||||
{
|
||||
#ifdef LPC24XX_EMC_TEST
|
||||
int *begin = (int *) 0xa0000000;
|
||||
const int *end = (const int *) 0xa0800000;
|
||||
int *out = begin;
|
||||
|
||||
while (out != end) {
|
||||
*out = (int) out;
|
||||
++out;
|
||||
}
|
||||
|
||||
out = begin;
|
||||
while (out != end) {
|
||||
if (*out != (int) out) {
|
||||
while (true) {
|
||||
/* Do nothing */
|
||||
}
|
||||
}
|
||||
++out;
|
||||
}
|
||||
#endif
|
||||
for (i = 0; i <= ticks; ++i) {
|
||||
__asm__ volatile ("nop");
|
||||
}
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_cpu_delay(unsigned ticks)
|
||||
{
|
||||
unsigned i = 0;
|
||||
|
||||
/* One loop execution needs four instructions */
|
||||
ticks /= 4;
|
||||
|
||||
for (i = 0; i <= ticks; ++i) {
|
||||
__asm__ volatile ("nop");
|
||||
}
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_udelay(unsigned us)
|
||||
{
|
||||
lpc24xx_cpu_delay(us * (LPC24XX_CCLK / 1000000));
|
||||
}
|
||||
#endif
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_udelay(unsigned us)
|
||||
{
|
||||
lpc24xx_cpu_delay(us * (LPC24XX_CCLK / 1000000));
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_init_emc_pinsel(void)
|
||||
{
|
||||
#ifdef LPC24XX_EMC_INIT
|
||||
static const BSP_START_DATA_SECTION uint32_t pinsel_5_9 [5] = {
|
||||
0x05010115,
|
||||
0x55555555,
|
||||
0x0,
|
||||
0x55555555,
|
||||
0x40050155
|
||||
};
|
||||
|
||||
bsp_start_memcpy(
|
||||
(int *) &PINSEL5,
|
||||
(const int *) &pinsel_5_9,
|
||||
sizeof(pinsel_5_9)
|
||||
);
|
||||
#endif
|
||||
bsp_start_memcpy(
|
||||
(int *) &PINSEL5,
|
||||
(const int *) &lpc24xx_start_config_pinsel_5_9,
|
||||
lpc24xx_start_config_pinsel_5_9_size
|
||||
);
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_init_emc_static(void)
|
||||
{
|
||||
#ifdef LPC24XX_EMC_NUMONYX
|
||||
/*
|
||||
* Static Memory 1: Numonyx M29W160EB
|
||||
*
|
||||
* 1 clock cycle = 1/72MHz = 13.9ns
|
||||
*/
|
||||
static const BSP_START_DATA_SECTION lpc24xx_emc_static_chip_config chip_config = {
|
||||
/*
|
||||
* 16 bit, page mode disabled, active LOW chip select, extended wait
|
||||
* disabled, writes not protected, byte lane state LOW/LOW (!).
|
||||
*/
|
||||
.config = 0x81,
|
||||
size_t i = 0;
|
||||
size_t chip_count = lpc24xx_start_config_emc_static_chip_count;
|
||||
|
||||
/* 1 clock cycles delay from the chip select 1 to the write enable */
|
||||
.waitwen = 0,
|
||||
|
||||
/*
|
||||
* 0 clock cycles delay from the chip select 1 or address change
|
||||
* (whichever is later) to the output enable
|
||||
*/
|
||||
.waitoen = 0,
|
||||
|
||||
/* 7 clock cycles delay from the chip select 1 to the read access */
|
||||
.waitrd = 0x6,
|
||||
|
||||
/*
|
||||
* 32 clock cycles delay for asynchronous page mode sequential accesses
|
||||
*/
|
||||
.waitpage = 0x1f,
|
||||
|
||||
/* 5 clock cycles delay from the chip select 1 to the write access */
|
||||
.waitwr = 0x3,
|
||||
|
||||
/* 16 bus turnaround cycles */
|
||||
.waitrun = 0xf
|
||||
};
|
||||
for (i = 0; i < chip_count; ++i) {
|
||||
const lpc24xx_emc_static_chip_config *chip_config =
|
||||
&lpc24xx_start_config_emc_static_chip [i];
|
||||
lpc24xx_emc_static_chip_config chip_config_on_stack;
|
||||
size_t config_size = sizeof(chip_config_on_stack.config);
|
||||
|
||||
bsp_start_memcpy(
|
||||
(int *) &chip_config_on_stack,
|
||||
(const int *) &chip_config,
|
||||
sizeof(chip_config_on_stack)
|
||||
(int *) &chip_config_on_stack.config,
|
||||
(const int *) &chip_config->config,
|
||||
config_size
|
||||
);
|
||||
bsp_start_memcpy(
|
||||
(int *) EMC_STA_BASE_1,
|
||||
(const int *) &chip_config_on_stack,
|
||||
sizeof(chip_config_on_stack)
|
||||
(int *) chip_config->chip_select,
|
||||
(const int *) &chip_config_on_stack.config,
|
||||
config_size
|
||||
);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_init_emc_memory_map(void)
|
||||
{
|
||||
#ifdef LPC24XX_EMC_INIT
|
||||
/* Use normal memory map */
|
||||
EMC_CTRL &= ~0x2U;
|
||||
#endif
|
||||
/* Use normal memory map */
|
||||
EMC_CTRL &= ~0x2U;
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_init_emc_dynamic(void)
|
||||
{
|
||||
#ifdef LPC24XX_EMC_MICRON
|
||||
/* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
|
||||
size_t chip_count = lpc24xx_start_config_emc_dynamic_chip_count;
|
||||
|
||||
static const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config dynamic_config = {
|
||||
/* Auto-refresh command every 15.6 us */
|
||||
.refresh = 0x46,
|
||||
if (chip_count > 0) {
|
||||
bool do_initialization = true;
|
||||
size_t i = 0;
|
||||
|
||||
/* Use command delayed strategy */
|
||||
.readconfig = 1,
|
||||
for (i = 0; do_initialization && i < chip_count; ++i) {
|
||||
const lpc24xx_emc_dynamic_chip_config *chip_cfg =
|
||||
&lpc24xx_start_config_emc_dynamic_chip [i];
|
||||
volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select;
|
||||
|
||||
/* Precharge command period 20 ns */
|
||||
.trp = 1,
|
||||
do_initialization = (chip_select->config & EMC_DYN_CFG_B) == 0;
|
||||
}
|
||||
|
||||
/* Active to precharge command period 44 ns */
|
||||
.tras = 3,
|
||||
if (do_initialization) {
|
||||
volatile lpc_emc *emc = (volatile lpc_emc *) EMC_BASE_ADDR;
|
||||
const lpc24xx_emc_dynamic_config *cfg =
|
||||
&lpc24xx_start_config_emc_dynamic [0];
|
||||
uint32_t dynamiccontrol = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS;
|
||||
|
||||
/* FIXME */
|
||||
.tsrex = 5,
|
||||
emc->dynamicreadconfig = cfg->readconfig;
|
||||
|
||||
/* FIXME */
|
||||
.tapr = 2,
|
||||
/* Timings */
|
||||
emc->dynamictrp = cfg->trp;
|
||||
emc->dynamictras = cfg->tras;
|
||||
emc->dynamictsrex = cfg->tsrex;
|
||||
emc->dynamictapr = cfg->tapr;
|
||||
emc->dynamictdal = cfg->tdal;
|
||||
emc->dynamictwr = cfg->twr;
|
||||
emc->dynamictrc = cfg->trc;
|
||||
emc->dynamictrfc = cfg->trfc;
|
||||
emc->dynamictxsr = cfg->txsr;
|
||||
emc->dynamictrrd = cfg->trrd;
|
||||
emc->dynamictmrd = cfg->tmrd;
|
||||
|
||||
/* Data-in to active command period tWR + tRP */
|
||||
.tdal = 4,
|
||||
|
||||
/* Write recovery time 15 ns */
|
||||
.twr = 1,
|
||||
|
||||
/* Active to active command period 66 ns */
|
||||
.trc = 4,
|
||||
|
||||
/* Auto refresh period 66 ns */
|
||||
.trfc = 4,
|
||||
|
||||
/* Exit self refresh to active command period 75 ns */
|
||||
.txsr = 5,
|
||||
|
||||
/* Active bank a to active bank b command period 15 ns */
|
||||
.trrd = 1,
|
||||
|
||||
/* Load mode register to active or refresh command period 2 tCK */
|
||||
.tmrd = 1,
|
||||
};
|
||||
static const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config chip_config = {
|
||||
/*
|
||||
* Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected writes
|
||||
*/
|
||||
.config = 0x280,
|
||||
|
||||
.rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
|
||||
.mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
|
||||
};
|
||||
|
||||
volatile lpc_emc_dynamic *chip = &emc->dynamic [0];
|
||||
uint32_t dynamiccontrol = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS;
|
||||
|
||||
/* Check if we need to initialize it */
|
||||
if ((chip->config & EMC_DYN_CFG_B) == 0) {
|
||||
/*
|
||||
* The buffer enable bit is not set. Now we assume that the controller
|
||||
* is not properly initialized.
|
||||
*/
|
||||
|
||||
/* Global dynamic settings */
|
||||
emc->dynamicreadconfig = dynamic_config.readconfig;
|
||||
emc->dynamictrp = dynamic_config.trp;
|
||||
emc->dynamictras = dynamic_config.tras;
|
||||
emc->dynamictsrex = dynamic_config.tsrex;
|
||||
emc->dynamictapr = dynamic_config.tapr;
|
||||
emc->dynamictdal = dynamic_config.tdal;
|
||||
emc->dynamictwr = dynamic_config.twr;
|
||||
emc->dynamictrc = dynamic_config.trc;
|
||||
emc->dynamictrfc = dynamic_config.trfc;
|
||||
emc->dynamictxsr = dynamic_config.txsr;
|
||||
emc->dynamictrrd = dynamic_config.trrd;
|
||||
emc->dynamictmrd = dynamic_config.tmrd;
|
||||
|
||||
/* Wait 100us after the power is applied and the clocks have stabilized */
|
||||
lpc24xx_udelay(100);
|
||||
|
||||
/* NOP period, disable self-refresh */
|
||||
/* NOP period */
|
||||
emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_NOP;
|
||||
lpc24xx_udelay(200);
|
||||
|
||||
/* Precharge all */
|
||||
/* Precharge */
|
||||
emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_PALL;
|
||||
emc->dynamicrefresh = 1;
|
||||
|
||||
/*
|
||||
* Perform several refresh cycles with a memory refresh every 16 AHB
|
||||
* clock cycles. Wait until eight SDRAM refresh cycles have occurred
|
||||
* (128 AHB clock cycles).
|
||||
*/
|
||||
emc->dynamicrefresh = 1;
|
||||
lpc24xx_cpu_delay(128);
|
||||
|
||||
/* Set refresh period */
|
||||
emc->dynamicrefresh = dynamic_config.refresh;
|
||||
/* Refresh timing */
|
||||
emc->dynamicrefresh = cfg->refresh;
|
||||
lpc24xx_cpu_delay(128);
|
||||
|
||||
/* Operational values for the chip */
|
||||
chip->rascas = chip_config.rascas;
|
||||
chip->config = chip_config.config;
|
||||
for (i = 0; i < chip_count; ++i) {
|
||||
const lpc24xx_emc_dynamic_chip_config *chip_cfg =
|
||||
&lpc24xx_start_config_emc_dynamic_chip [i];
|
||||
volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select;
|
||||
uint32_t config = chip_cfg->config;
|
||||
|
||||
/* Mode */
|
||||
emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE;
|
||||
*((volatile uint32_t *) chip_config.mode);
|
||||
/* Chip select */
|
||||
chip_select->config = config;
|
||||
chip_select->rascas = chip_cfg->rascas;
|
||||
|
||||
/* Normal operation */
|
||||
emc->dynamiccontrol = 0;
|
||||
/* Set modes */
|
||||
emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE;
|
||||
*(volatile uint32_t *)(chip_cfg->address + chip_cfg->mode);
|
||||
|
||||
/* Enable buffer */
|
||||
chip->config |= EMC_DYN_CFG_B;
|
||||
/* Enable buffer */
|
||||
chip_select->config = config | EMC_DYN_CFG_B;
|
||||
}
|
||||
|
||||
/* Test RAM */
|
||||
lpc24xx_ram_test_32();
|
||||
emc->dynamiccontrol = dynamiccontrol;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static void BSP_START_TEXT_SECTION lpc24xx_pll_config(
|
||||
@@ -400,9 +255,19 @@ static void BSP_START_TEXT_SECTION lpc24xx_init_pll(void)
|
||||
|
||||
/* Set PLL */
|
||||
#if LPC24XX_OSCILLATOR_MAIN == 12000000U
|
||||
lpc24xx_set_pll(1, 0, 11, 3);
|
||||
#if LPC24XX_CCLK == 72000000U
|
||||
lpc24xx_set_pll(1, 0, 11, 3);
|
||||
#elif LPC24XX_CCLK == 51612800U
|
||||
lpc24xx_set_pll(1, 30, 399, 5);
|
||||
#else
|
||||
#error "unexpected CCLK"
|
||||
#endif
|
||||
#elif LPC24XX_OSCILLATOR_MAIN == 3686400U
|
||||
lpc24xx_set_pll(1, 0, 47, 5);
|
||||
#if LPC24XX_CCLK == 58982400U
|
||||
lpc24xx_set_pll(1, 0, 47, 5);
|
||||
#else
|
||||
#error "unexpected CCLK"
|
||||
#endif
|
||||
#else
|
||||
#error "unexpected main oscillator frequency"
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief Memory map for PLX800 (LPC2478).
|
||||
*/
|
||||
|
||||
MEMORY {
|
||||
RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
|
||||
RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 8M
|
||||
ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 512k - 8k
|
||||
NIRVANA : ORIGIN = 0, LENGTH = 0
|
||||
}
|
||||
|
||||
REGION_ALIAS ("REGION_START", ROM_INT);
|
||||
REGION_ALIAS ("REGION_VECTOR", RAM_INT);
|
||||
REGION_ALIAS ("REGION_TEXT", ROM_INT);
|
||||
REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
|
||||
REGION_ALIAS ("REGION_RODATA", ROM_INT);
|
||||
REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
|
||||
REGION_ALIAS ("REGION_DATA", RAM_EXT);
|
||||
REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
|
||||
REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
|
||||
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
|
||||
REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
|
||||
REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
|
||||
REGION_ALIAS ("REGION_BSS", RAM_EXT);
|
||||
REGION_ALIAS ("REGION_WORK", RAM_EXT);
|
||||
REGION_ALIAS ("REGION_STACK", RAM_INT);
|
||||
|
||||
INCLUDE linkcmds.armv4
|
||||
119
c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
Normal file
119
c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
Normal file
@@ -0,0 +1,119 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup lpc24xx
|
||||
*
|
||||
* @brief BSP start EMC dynamic memory configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <bsp/start-config.h>
|
||||
#include <bsp/lpc24xx.h>
|
||||
|
||||
const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
|
||||
lpc24xx_start_config_emc_dynamic [] = {
|
||||
#if defined(LPC24XX_EMC_MICRON)
|
||||
/* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
|
||||
{
|
||||
/* Auto-refresh command every 15.6 us */
|
||||
.refresh = 0x46,
|
||||
|
||||
/* Use command delayed strategy */
|
||||
.readconfig = 1,
|
||||
|
||||
/* Precharge command period 20 ns */
|
||||
.trp = 1,
|
||||
|
||||
/* Active to precharge command period 44 ns */
|
||||
.tras = 3,
|
||||
|
||||
/* FIXME */
|
||||
.tsrex = 5,
|
||||
|
||||
/* FIXME */
|
||||
.tapr = 2,
|
||||
|
||||
/* Data-in to active command period tWR + tRP */
|
||||
.tdal = 4,
|
||||
|
||||
/* Write recovery time 15 ns */
|
||||
.twr = 1,
|
||||
|
||||
/* Active to active command period 66 ns */
|
||||
.trc = 4,
|
||||
|
||||
/* Auto refresh period 66 ns */
|
||||
.trfc = 4,
|
||||
|
||||
/* Exit self refresh to active command period 75 ns */
|
||||
.txsr = 5,
|
||||
|
||||
/* Active bank a to active bank b command period 15 ns */
|
||||
.trrd = 1,
|
||||
|
||||
/* Load mode register to active or refresh command period 2 tCK */
|
||||
.tmrd = 1
|
||||
}
|
||||
#elif defined(LPC24XX_EMC_K4S561632E)
|
||||
{
|
||||
.refresh = 35,
|
||||
.readconfig = 1,
|
||||
.trp = 2,
|
||||
.tras = 4,
|
||||
.tsrex = 5,
|
||||
.tapr = 1,
|
||||
.tdal = 5,
|
||||
.twr = 3,
|
||||
.trc = 5,
|
||||
.trfc = 5,
|
||||
.txsr = 5,
|
||||
.trrd = 3,
|
||||
.tmrd = 2
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
|
||||
lpc24xx_start_config_emc_dynamic_chip [] = {
|
||||
#if defined(LPC24XX_EMC_MICRON)
|
||||
{
|
||||
.chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
|
||||
|
||||
/*
|
||||
* Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
|
||||
* writes.
|
||||
*/
|
||||
.config = 0x280,
|
||||
|
||||
.rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
|
||||
.mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
|
||||
}
|
||||
#elif defined(LPC24XX_EMC_K4S561632E)
|
||||
{
|
||||
.chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
|
||||
.config = 0x680,
|
||||
.rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
|
||||
.mode = 0xa0000000 | (0x33 << 12)
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
const BSP_START_DATA_SECTION size_t
|
||||
lpc24xx_start_config_emc_dynamic_chip_count =
|
||||
sizeof(lpc24xx_start_config_emc_dynamic_chip)
|
||||
/ sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
|
||||
@@ -0,0 +1,75 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup lpc24xx
|
||||
*
|
||||
* @brief BSP start EMC static memory configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <bsp/start-config.h>
|
||||
#include <bsp/lpc24xx.h>
|
||||
|
||||
const BSP_START_DATA_SECTION lpc24xx_emc_static_chip_config
|
||||
lpc24xx_start_config_emc_static_chip [] = {
|
||||
#ifdef LPC24XX_EMC_NUMONYX
|
||||
/*
|
||||
* Static Memory 1: Numonyx M29W160EB
|
||||
*
|
||||
* 1 clock cycle = 1/72MHz = 13.9ns
|
||||
*/
|
||||
{
|
||||
.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_1,
|
||||
.config = {
|
||||
/*
|
||||
* 16 bit, page mode disabled, active LOW chip select, extended wait
|
||||
* disabled, writes not protected, byte lane state LOW/LOW (!).
|
||||
*/
|
||||
.config = 0x81,
|
||||
|
||||
/* 1 clock cycles delay from the chip select 1 to the write enable */
|
||||
.waitwen = 0,
|
||||
|
||||
/*
|
||||
* 0 clock cycles delay from the chip select 1 or address change
|
||||
* (whichever is later) to the output enable
|
||||
*/
|
||||
.waitoen = 0,
|
||||
|
||||
/* 7 clock cycles delay from the chip select 1 to the read access */
|
||||
.waitrd = 0x6,
|
||||
|
||||
/*
|
||||
* 32 clock cycles delay for asynchronous page mode sequential accesses
|
||||
*/
|
||||
.waitpage = 0x1f,
|
||||
|
||||
/* 5 clock cycles delay from the chip select 1 to the write access */
|
||||
.waitwr = 0x3,
|
||||
|
||||
/* 16 bus turnaround cycles */
|
||||
.waitrun = 0xf
|
||||
}
|
||||
}
|
||||
#endif /* LPC24XX_EMC_NUMONYX */
|
||||
};
|
||||
|
||||
const BSP_START_DATA_SECTION size_t
|
||||
lpc24xx_start_config_emc_static_chip_count =
|
||||
sizeof(lpc24xx_start_config_emc_static_chip)
|
||||
/ sizeof(lpc24xx_start_config_emc_static_chip [0]);
|
||||
46
c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c
Normal file
46
c/src/lib/libbsp/arm/lpc24xx/startup/start-config-pinsel.c
Normal file
@@ -0,0 +1,46 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup lpc24xx
|
||||
*
|
||||
* @brief BSP start pin selection configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Obere Lagerstr. 30
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <bsp/start-config.h>
|
||||
|
||||
const BSP_START_DATA_SECTION uint32_t lpc24xx_start_config_pinsel_5_9 [] = {
|
||||
#if defined(LPC24XX_EMC_MICRON) \
|
||||
|| defined(LPC24XX_EMC_K4S561632E) \
|
||||
|| defined(LPC24XX_EMC_NUMONYX)
|
||||
0x05010115,
|
||||
0x55555555,
|
||||
0x0,
|
||||
#ifdef LPC24XX_EMC_K4S561632E
|
||||
0x15555555,
|
||||
0x0a040000
|
||||
#else
|
||||
0x55555555,
|
||||
0x40050155
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
const BSP_START_DATA_SECTION size_t
|
||||
lpc24xx_start_config_pinsel_5_9_size =
|
||||
sizeof(lpc24xx_start_config_pinsel_5_9);
|
||||
Reference in New Issue
Block a user