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score: Doxygen Clean Up Task #16

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This commit is contained in:
Alex Ivanov
2013-01-08 13:36:13 -06:00
committed by Jennifer Averett
parent f597cc1ba2
commit 4f5740fd6c
19 changed files with 1387 additions and 1313 deletions
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14
cpukit/score/cpu/bfin/rtems/asm.h
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@@ -1,17 +1,20 @@
/**
* @file rtems/asm.h
* @file
*
* @brief Address the Problems Caused by Incompatible Flavor of
* Assemblers and Toolsets
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
* @note The spacing in the use of these macros
* is critical to them working as advertised.
*/
/*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
@@ -95,7 +98,8 @@
#define BEGIN_DATA
/** This macro is used to denote the end of a data section. */
#define END_DATA
/** This macro is used to denote the beginning of the
/**
* This macro is used to denote the beginning of the
* unitialized data section.
*/
#define BEGIN_BSS

15
cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
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@@ -1,5 +1,7 @@
/**
*@file bf52x.h
* @file
*
* @brief Basic MMR for the Blackfin 52x CPU
*
* This file defines basic MMR for the Blackfin 52x CPU.
* The MMR have been taken from the ADSP-BF52x Blackfin Processor
@@ -7,7 +9,9 @@
* refer to this Documentation.
*
* Based on bf533.h
*
*/
/*
* COPYRIGHT (c) 2006.
* Atos Automacao Industrial LTDA.
* modified by Alain Schaefer <alain.schaefer@easc.ch>
@@ -18,11 +22,8 @@
* http://www.rtems.com/license/LICENSE.
*
*
* @author Rohan Kangralkar, ECE Department Northeastern University
* @date 02/15/2011
*
* HISTORY:
*
* Author: Rohan Kangralkar, ECE Department Northeastern University
* Date: 02/15/2011
*/
#ifndef _RTEMS_BFIN_52x_H

8
cpukit/score/cpu/bfin/rtems/bfin/bf533.h
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@@ -1,4 +1,7 @@
/* bfin.h
/**
* @file
*
* @brief Basic MMR for the Blackfin 531/532/533 CPU
*
* This file defines basic MMR for the Blackfin 531/532/533 CPU.
* The MMR have been taken from the ADSP-BF533 Blackfin Processor
@@ -8,7 +11,8 @@
* The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF)
* and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined
* in bfin.h which is included.
*
*/
/*
* COPYRIGHT (c) 2006.
* Atos Automacao Industrial LTDA.
* modified by Alain Schaefer <alain.schaefer@easc.ch>

8
cpukit/score/cpu/bfin/rtems/bfin/bfin.h
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@@ -1,8 +1,12 @@
/* bfin.h
/**
* @file
*
* @brief Macros for MMR register common to all Blackfin Processors
*
* This file defines Macros for MMR register common to all Blackfin
* Processors.
*
*/
/*
* COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
* modified by Alain Schaefer <alain.schaefer@easc.ch>
* and Antonio Giovanini <antonio@atos.com.br>

10
cpukit/score/cpu/bfin/rtems/score/bfin.h
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@@ -1,10 +1,16 @@
/* bfin.h
/**
* @file
*
* @brief Blackfin Set up Basic CPU Dependency Settings Based on
* Compiler Settings
*
* This file sets up basic CPU dependency settings based on
* compiler settings. For example, it can determine if
* floating point is available. This particular implementation
* is specified to the Blackfin port.
*
*/
/*
*
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).

63
cpukit/score/cpu/bfin/rtems/score/cpu.h
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@@ -1,11 +1,13 @@
/**
* @file rtems/score/cpu.h
* @file
*
* @brief Blackfin CPU Department Source
*
* This include file contains information pertaining to the Blackfin
* processor.
*/
/*
* This include file contains information pertaining to the Blackfin
* processor.
*
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
* adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
@@ -360,10 +362,11 @@ extern "C" {
* @defgroup CPUEndian Processor Dependent Endianness Support
*
* This group assists in issues related to processor endianness.
*
* @{
*/
/**
* @ingroup CPUEndian
* Define what is required to specify how the network to host conversion
* routines are handled.
*
@@ -379,7 +382,6 @@ extern "C" {
#define CPU_BIG_ENDIAN FALSE
/**
* @ingroup CPUEndian
* Define what is required to specify how the network to host conversion
* routines are handled.
*
@@ -394,6 +396,8 @@ extern "C" {
*/
#define CPU_LITTLE_ENDIAN TRUE
/** @} */
/**
* @ingroup CPUInterrupt
* The following defines the number of bits actually used in the
@@ -456,12 +460,13 @@ extern "C" {
* Port Specific Information:
*
* XXX document implementation including references if appropriate
*
* @{
*/
#ifndef ASM
/**
* @ingroup CPUContext Management
* This defines the minimal set of integer and processor state registers
* that must be saved during a voluntary context switch from one thread
* to another.
@@ -490,7 +495,6 @@ typedef struct {
(_context)->register_sp
/**
* @ingroup CPUContext Management
* This defines the complete set of floating point registers that must
* be saved during any context switch from one thread to another.
*/
@@ -500,7 +504,6 @@ typedef struct {
} Context_Control_fp;
/**
* @ingroup CPUContext Management
* This defines the set of integer and processor state registers that must
* be saved during an interrupt. This set does not include any which are
* in @ref Context_Control.
@@ -525,6 +528,8 @@ typedef struct {
*/
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/** @} */
/**
* @defgroup CPUInterrupt Processor Dependent Interrupt Management
*
@@ -542,6 +547,8 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
* Port Specific Information:
*
* XXX document implementation including references if appropriate
*
* @{
*/
/*
@@ -604,6 +611,8 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
*/
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
/** @} */
/**
* @ingroup CPUContext
* Should be large enough to run all RTEMS tests. This ensures
@@ -690,7 +699,12 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
*/
/**
* @ingroup CPUInterrupt
* @addtogroup CPUInterrupt
*
* @{
*/
/**
* Support routine to initialize the RTEMS vector table after it is allocated.
*
* Port Specific Information:
@@ -700,7 +714,6 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_Initialize_vectors()
/**
* @ingroup CPUInterrupt
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in @a _isr_cookie.
*
@@ -717,7 +730,6 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/**
* @ingroup CPUInterrupt
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* @a _isr_cookie is not modified.
@@ -733,7 +745,6 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
}
/**
* @ingroup CPUInterrupt
* This temporarily restores the interrupt to @a _isr_cookie before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter @a _isr_cookie is not
@@ -751,8 +762,6 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
}
/**
* @ingroup CPUInterrupt
*
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
@@ -775,7 +784,6 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#ifndef ASM
/**
* @ingroup CPUInterrupt
* Return the current interrupt disable level for this task in
* the format used by the interrupt level portion of the task mode.
*
@@ -789,6 +797,8 @@ uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/** @} */
/* Context handler macros */
/**
@@ -929,17 +939,17 @@ void _CPU_Context_Initialize(
*
* This set of routines are used to implement fast searches for
* the most important ready task.
*
* @{
*/
/**
* @ingroup CPUBitfield
* This definition is set to TRUE if the port uses the generic bitfield
* manipulation implementation.
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
/**
* @ingroup CPUBitfield
* This definition is set to TRUE if the port uses the data tables provided
* by the generic bitfield manipulation implementation.
* This can occur when actually using the generic bitfield manipulation
@@ -950,7 +960,6 @@ void _CPU_Context_Initialize(
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
/**
* @ingroup CPUBitfield
* This routine sets @a _output to the bit number of the first bit
* set in @a _value. @a _value is of CPU dependent type
* @a Priority_bit_map_Control. This type may be either 16 or 32 bits
@@ -1024,6 +1033,8 @@ void _CPU_Context_Initialize(
/* end of Bitfield handler macros */
/** @} */
/**
* This routine builds the mask which corresponds to the bit fields
* as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion
@@ -1065,7 +1076,7 @@ void _CPU_Context_Initialize(
/* functions */
/**
* @brief CPU Initialize
* @brief CPU initialize.
* This routine performs CPU dependent initialization.
*
* Port Specific Information:
@@ -1137,7 +1148,12 @@ void _CPU_Install_interrupt_stack( void );
void *_CPU_Thread_Idle_body( uintptr_t ignored );
/**
* @ingroup CPUContext
* @addtogroup CPUContext
*
* @{
*/
/**
* This routine switches from the run context to the heir context.
*
* @param[in] run points to the context of the currently executing task
@@ -1153,7 +1169,6 @@ void _CPU_Context_switch(
);
/**
* @ingroup CPUContext
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in @ref _CPU_Context_switch.
*
@@ -1170,7 +1185,6 @@ void _CPU_Context_restore(
) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
/**
* @ingroup CPUContext
* This routine saves the floating point context passed to it.
*
* @param[in] fp_context_ptr is a pointer to a pointer to a floating
@@ -1188,7 +1202,6 @@ void _CPU_Context_save_fp(
);
/**
* @ingroup CPUContext
* This routine restores the floating point context passed to it.
*
* @param[in] fp_context_ptr is a pointer to a pointer to a floating
@@ -1205,6 +1218,8 @@ void _CPU_Context_restore_fp(
Context_Control_fp **fp_context_ptr
);
/** @} */
/* FIXME */
typedef CPU_Interrupt_frame CPU_Exception_frame;

8
cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
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@@ -1,10 +1,12 @@
/**
* @file rtems/score/cpu_asm.h
* @file
*
* @brief Blackfin Assembly File
*
* Defines a couple of Macros used in cpu_asm.S
*/
/*
* Defines a couple of Macros used in cpu_asm.S
*
* COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
* written by Alain Schaefer <alain.schaefer@easc.ch>
* and Antonio Giovanini <antonio@atos.com.br>

10
cpukit/score/cpu/bfin/rtems/score/types.h
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@@ -1,7 +1,13 @@
/*
/**
* @file
*
* @brief Blackfin CPU Type Definitions
*
* This include file contains type definitions pertaining to the
* Blackfin processor family.
*
*/
/*
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
*

19
cpukit/score/cpu/nios2/rtems/score/cpu.h
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@@ -1,3 +1,9 @@
/**
* @file
*
* @brief Altera Nios II CPU Department Source
*/
/*
* Copyright (c) 2011 embedded brains GmbH
*
@@ -253,8 +259,8 @@ void _CPU_Initialize_vectors( void );
* _CPU_ISR_Disable(). The value is not modified.
*
* This flash code is optimal for all Nios II configurations. The rdctl does
* not flush the pipeline and has only a late result penalty. The wrctl on the
* other hand leads to a pipeline flush.
* not flush the pipeline and has only a late result penalty. The wrctl on
* the other hand leads to a pipeline flush.
*/
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
@@ -319,14 +325,12 @@ void _CPU_Context_Initialize(
void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
/**
* @brief CPU Initialize
*
* @brief CPU initialization.
*/
void _CPU_Initialize( void );
/**
* @brief CPU ISR Install Raw Handler
*
* @brief CPU ISR install raw handler.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
@@ -335,8 +339,7 @@ void _CPU_ISR_install_raw_handler(
);
/**
* @brief CPU ISR Install Vector.
*
* @brief CPU ISR install vector.
*/
void _CPU_ISR_install_vector(
uint32_t vector,

12
cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
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@@ -1,12 +1,14 @@
/**
* @file rtems/score/cpu_asm.h
*/
/*
* @file
*
* @brief Altera Nios II Assembly File
*
* Very loose template for an include file for the cpu_asm.? file
* if it is implemented as a ".S" file (preprocessed by cpp) instead
* of a ".s" file (preprocessed by gm4 or gasp).
*
*/
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*

10
cpukit/score/cpu/nios2/rtems/score/types.h
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@@ -1,11 +1,13 @@
/**
* @file rtems/score/types.h
* @file
*
* @brief Altera Nios II CPU Type Definitions
*
* This include file contains type definitions pertaining to the
* Altera Nios II processor family.
*/
/*
* This include file contains type definitions pertaining to the
* Altera Nios II processor family.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*

11
cpukit/score/cpu/sh/rtems/asm.h
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@@ -1,20 +1,23 @@
/**
* @file rtems/asm.h
* @file
*
* @brief Address the Problems Caused by Incompatible Flavor of
* Assemblers and Toolsets
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
* @note The spacing in the use of these macros
* is critical to them working as advertised.
*/
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available

10
cpukit/score/cpu/sh/rtems/score/sh.h
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@@ -1,11 +1,13 @@
/**
* @file rtems/score/sh.h
* @file
*
* @brief Hitachi SH CPU Department Source
*
* This include file contains information pertaining to the Hitachi SH
* processor.
*/
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*

10
cpukit/score/cpu/sh/rtems/score/sh_io.h
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@@ -1,11 +1,13 @@
/**
* @file rtems/score/sh_io.h
* @file
*
* @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture
*
* These are some macros to access memory mapped devices
* on the SH7000-architecture.
*/
/*
* These are some macros to access memory mapped devices
* on the SH7000-architecture.
*
* Inspired from the linux kernel's include/asm/io.h
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and

10
cpukit/score/cpu/sh/rtems/score/types.h
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@@ -1,11 +1,13 @@
/**
* @file rtems/score/types.h
* @file
*
* @brief Hitachi SH CPU Type Definitions
*
* This include file contains information pertaining to the Hitachi SH
* processor.
*/
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*

18
cpukit/score/cpu/v850/rtems/asm.h
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@@ -1,26 +1,27 @@
/**
* @file rtems/asm.h
* @file
*
* @brief Address the Problems Caused by Incompatible Flavor of
* Assemblers and Toolsets
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*
* @note The spacing in the use of these macros
* is critical to them working as advertised.
*/
/*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*/
/*
*
* COPYRIGHT (c) 1994-2012.
* On-Line Applications Research Corporation (OAR).
*/
@@ -97,7 +98,8 @@
#define BEGIN_DATA
/** This macro is used to denote the end of a data section. */
#define END_DATA
/** This macro is used to denote the beginning of the
/**
* This macro is used to denote the beginning of the
* unitialized data section.
*/
#define BEGIN_BSS

66
cpukit/score/cpu/v850/rtems/score/cpu.h
View File

@@ -1,8 +1,8 @@
/**
* @file rtems/score/cpu.h
*/
/*
* @file
*
* @brief V850 CPU Department Source
*
* This include file contains information pertaining to the v850
* processor.
*/
@@ -347,10 +347,11 @@ extern "C" {
* @defgroup CPUEndian Processor Dependent Endianness Support
*
* This group assists in issues related to processor endianness.
*
* @{
*/
/**
* @ingroup CPUEndian
* Define what is required to specify how the network to host conversion
* routines are handled.
*
@@ -366,7 +367,6 @@ extern "C" {
#define CPU_BIG_ENDIAN FALSE
/**
* @ingroup CPUEndian
* Define what is required to specify how the network to host conversion
* routines are handled.
*
@@ -381,6 +381,8 @@ extern "C" {
*/
#define CPU_LITTLE_ENDIAN TRUE
/** @} */
/**
* @ingroup CPUInterrupt
* The following defines the number of bits actually used in the
@@ -434,10 +436,11 @@ extern "C" {
*
* On the v850, this port saves special registers and those that are
* callee saved.
*
* @{
*/
/**
* @ingroup CPUContext Management
* This defines the minimal set of integer and processor state registers
* that must be saved during a voluntary context switch from one thread
* to another.
@@ -461,8 +464,6 @@ typedef struct {
} Context_Control;
/**
* @ingroup CPUContext Management
*
* This macro returns the stack pointer associated with @a _context.
*
* @param[in] _context is the thread context area to access
@@ -473,7 +474,6 @@ typedef struct {
(_context)->r3_stack_pointer
/**
* @ingroup CPUContext Management
* This defines the complete set of floating point registers that must
* be saved during any context switch from one thread to another.
*/
@@ -483,7 +483,6 @@ typedef struct {
} Context_Control_fp;
/**
* @ingroup CPUContext Management
* This defines the set of integer and processor state registers that must
* be saved during an interrupt. This set does not include any which are
* in @ref Context_Control.
@@ -496,6 +495,8 @@ typedef struct {
uint32_t special_interrupt_register;
} CPU_Interrupt_frame;
/** @} */
/**
* @defgroup CPUInterrupt Processor Dependent Interrupt Management
*
@@ -513,6 +514,8 @@ typedef struct {
* Port Specific Information:
*
* XXX document implementation including references if appropriate
*
* @{
*/
/**
@@ -546,7 +549,6 @@ typedef struct {
/* XXX evaluate removing it */
#if 0
/**
* @ingroup CPUInterrupt
* This defines the number of entries in the @ref _ISR_Vector_table managed
* by RTEMS.
*
@@ -558,18 +560,18 @@ typedef struct {
#endif
/**
* @ingroup CPUInterrupt
* This defines the highest interrupt vector number for this port.
*/
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/**
* @ingroup CPUInterrupt
* This is defined if the port has a special way to report the ISR nesting
* level. Most ports maintain the variable @a _ISR_Nest_level.
*/
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
/** @} */
/**
* @ingroup CPUContext
* Should be large enough to run all RTEMS tests. This ensures
@@ -657,7 +659,12 @@ typedef struct {
*/
/**
* @ingroup CPUInterrupt
* @addtogroup CPUInterrupt
*
* @{
*/
/**
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in @a _isr_cookie.
*
@@ -677,7 +684,6 @@ typedef struct {
} while (0)
/**
* @ingroup CPUInterrupt
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* @a _isr_cookie is not modified.
@@ -696,7 +702,6 @@ typedef struct {
} while (0)
/**
* @ingroup CPUInterrupt
* This temporarily restores the interrupt to @a _isr_cookie before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter @a _isr_cookie is not
@@ -716,8 +721,6 @@ typedef struct {
} while (0)
/**
* @ingroup CPUInterrupt
*
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
@@ -741,7 +744,6 @@ typedef struct {
} while (0)
/**
* @ingroup CPUInterrupt
* Return the current interrupt disable level for this task in
* the format used by the interrupt level portion of the task mode.
*
@@ -755,6 +757,8 @@ uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/** @} */
/* Context handler macros */
/**
@@ -897,17 +901,17 @@ void _CPU_Context_Initialize(
*
* This set of routines are used to implement fast searches for
* the most important ready task.
*
* @{
*/
/**
* @ingroup CPUBitfield
* This definition is set to TRUE if the port uses the generic bitfield
* manipulation implementation.
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
/**
* @ingroup CPUBitfield
* This definition is set to TRUE if the port uses the data tables provided
* by the generic bitfield manipulation implementation.
* This can occur when actually using the generic bitfield manipulation
@@ -925,7 +929,6 @@ void _CPU_Context_Initialize(
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
/**
* @ingroup CPUBitfield
* This routine sets @a _output to the bit number of the first bit
* set in @a _value. @a _value is of CPU dependent type
* @a Priority_bit_map_Control. This type may be either 16 or 32 bits
@@ -1016,7 +1019,6 @@ void _CPU_Context_Initialize(
#endif
/**
* @ingroup CPUBitfield
* This routine translates the bit numbers returned by
* @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
* a major or minor component of a priority. See the discussion
@@ -1038,10 +1040,12 @@ void _CPU_Context_Initialize(
/* end of Priority handler macros */
/** @} */
/* functions */
/**
* @brief CPU Initialize
* @brief CPU initialize.
* This routine performs CPU dependent initialization.
*
* Port Specific Information:
@@ -1053,7 +1057,12 @@ void _CPU_Context_Initialize(
void _CPU_Initialize(void);
/**
* @ingroup CPUContext
* @addtogroup CPUContext
*
* @{
*/
/**
* This routine switches from the run context to the heir context.
*
* @param[in] run points to the context of the currently executing task
@@ -1069,7 +1078,6 @@ void _CPU_Context_switch(
);
/**
* @ingroup CPUContext
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in @ref _CPU_Context_switch.
*
@@ -1088,7 +1096,6 @@ void _CPU_Context_restore(
/* XXX this should be possible to remove */
#if 0
/**
* @ingroup CPUContext
* This routine saves the floating point context passed to it.
*
* @param[in] fp_context_ptr is a pointer to a pointer to a floating
@@ -1109,7 +1116,6 @@ void _CPU_Context_save_fp(
/* XXX this should be possible to remove */
#if 0
/**
* @ingroup CPUContext
* This routine restores the floating point context passed to it.
*
* @param[in] fp_context_ptr is a pointer to a pointer to a floating
@@ -1127,6 +1133,8 @@ void _CPU_Context_restore_fp(
);
#endif
/** @} */
/* FIXME */
typedef CPU_Interrupt_frame CPU_Exception_frame;

10
cpukit/score/cpu/v850/rtems/score/types.h
View File

@@ -1,11 +1,13 @@
/**
* @file rtems/score/types.h
* @file
*
* @brief V850 CPU Type Definitions
*
* This include file contains type definitions pertaining to the
* v850 processor family.
*/
/*
* This include file contains type definitions pertaining to the
* v850 processor family.
*
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
*

6
cpukit/score/cpu/v850/rtems/score/v850.h
View File

@@ -1,4 +1,8 @@
/*
/**
* @file
*
* @brief V850 Set up Basic CPU Dependency Settings Based on Compiler Settings
*
* This file sets up basic CPU dependency settings based on
* compiler settings. For example, it can determine if
* floating point is available. This particular implementation