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2010-12-29 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* new-exceptions/bspsupport/ppc_exc_address.c,
	new-exceptions/bspsupport/ppc_exc_initialize.c: Fixed IVOR handling for
	e200z0 and e200z1.
This commit is contained in:
Sebastian Huber
2010-12-29 10:48:08 +00:00
parent ef8dff0531
commit 4e9d8ea602
2 changed files with 12 additions and 4 deletions
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8
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_address.c
View File

@@ -57,10 +57,10 @@ static const uint8_t ivor_values [] = {
[ASM_BOOKE_DTLBMISS_VECTOR] = 13,
[ASM_BOOKE_ITLBMISS_VECTOR] = 14,
[ASM_BOOKE_DEBUG_VECTOR] = 15,
[ASM_E500_SPE_UNAVAILABLE_VECTOR] = 32,
[ASM_E500_EMB_FP_DATA_VECTOR] = 33,
[ASM_E500_EMB_FP_ROUND_VECTOR] = 34,
[ASM_E500_PERFMON_VECTOR] = 35
[ASM_E500_SPE_UNAVAILABLE_VECTOR] = 16,
[ASM_E500_EMB_FP_DATA_VECTOR] = 17,
[ASM_E500_EMB_FP_ROUND_VECTOR] = 18,
[ASM_E500_PERFMON_VECTOR] = 19
};
void *ppc_exc_vector_address(unsigned vector)

8
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
View File

@@ -38,6 +38,14 @@ static void ppc_exc_initialize_booke(void)
/* Interupt vector prefix register */
MTIVPR(ppc_exc_vector_base);
if (ppc_cpu_is(PPC_e200z0) || ppc_cpu_is(PPC_e200z1)) {
/*
* These cores have hard wired IVOR registers. An access will case a
* program exception.
*/
return;
}
/* Interupt vector offset registers */
MTIVOR(0, ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR));
MTIVOR(1, ppc_exc_vector_address(ASM_MACH_VECTOR));