forked from Imagelibrary/rtems
bsps: Rework cache manager implementation
The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
This commit is contained in:
Sebastian Huber
184
bsps/arm/shared/cache/cache-cp15.c
vendored
Normal file
184
bsps/arm/shared/cache/cache-cp15.c
vendored
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@@ -0,0 +1,184 @@
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/**
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* @file
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*
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* @ingroup arm
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*
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* @brief ARM cache defines and implementation.
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*/
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/*
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* Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <libcpu/arm-cp15.h>
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#include "cache-cp15.h"
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#define CPU_DATA_CACHE_ALIGNMENT 32
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
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#if defined(__ARM_ARCH_7A__)
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/* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */
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#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
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#endif
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#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
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ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
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static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
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{
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arm_cache_l1_flush_1_data_line(d_addr);
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}
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static inline void
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_CPU_cache_flush_data_range(
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const void *d_addr,
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size_t n_bytes
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)
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{
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_ARM_Data_synchronization_barrier();
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arm_cache_l1_flush_data_range(
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d_addr,
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n_bytes
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);
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#if !defined(__ARM_ARCH_7A__)
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arm_cp15_drain_write_buffer();
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#endif
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_ARM_Data_synchronization_barrier();
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}
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static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
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{
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arm_cache_l1_invalidate_1_data_line(d_addr);
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}
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static inline void
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_CPU_cache_invalidate_data_range(
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const void *addr_first,
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size_t n_bytes
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)
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{
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arm_cache_l1_invalidate_data_range(
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addr_first,
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n_bytes
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);
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}
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static inline void _CPU_cache_freeze_data(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
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{
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arm_cache_l1_invalidate_1_instruction_line(d_addr);
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}
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static inline void
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_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
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{
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arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
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_ARM_Instruction_synchronization_barrier();
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_flush_entire_data(void)
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{
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_ARM_Data_synchronization_barrier();
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#if defined(__ARM_ARCH_7A__)
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arm_cp15_data_cache_clean_all_levels();
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#else
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arm_cp15_data_cache_clean_and_invalidate();
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arm_cp15_drain_write_buffer();
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#endif
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_ARM_Data_synchronization_barrier();
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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#if defined(__ARM_ARCH_7A__)
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arm_cp15_data_cache_invalidate_all_levels();
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#else
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arm_cp15_data_cache_invalidate();
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#endif
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}
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static inline void _CPU_cache_enable_data(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_local_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl |= ARM_CP15_CTRL_C;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_local_enable(level);
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}
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static inline void _CPU_cache_disable_data(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_local_disable(level);
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arm_cp15_data_cache_test_and_clean_and_invalidate();
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ctrl = arm_cp15_get_control();
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ctrl &= ~ARM_CP15_CTRL_C;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_local_enable(level);
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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arm_cache_l1_invalidate_entire_instruction();
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_ARM_Instruction_synchronization_barrier();
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_local_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl |= ARM_CP15_CTRL_I;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_local_enable(level);
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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uint32_t ctrl;
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rtems_interrupt_local_disable(level);
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ctrl = arm_cp15_get_control();
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ctrl &= ~ARM_CP15_CTRL_I;
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arm_cp15_set_control(ctrl);
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rtems_interrupt_local_enable(level);
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}
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#include "../../shared/cache/cacheimpl.h"
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407
bsps/arm/shared/cache/cache-cp15.h
vendored
Normal file
407
bsps/arm/shared/cache/cache-cp15.h
vendored
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@@ -0,0 +1,407 @@
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/**
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* @ingroup arm_shared
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*
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* @brief Level 1 Cache definitions and functions.
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*
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* This file implements handling for the ARM Level 1 cache controller
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*/
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/*
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* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_CACHE_L1_H
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#define LIBBSP_ARM_SHARED_CACHE_L1_H
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#include <bsp.h>
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#include <libcpu/arm-cp15.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* These two defines also ensure that the rtems_cache_* functions have bodies */
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#define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32
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#define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
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#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
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#define ARM_CACHE_L1_CSS_ID_DATA \
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(ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
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#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
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(ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
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#define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
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#define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
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( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \
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- 1 )
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/* Errata Handlers */
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static void arm_cache_l1_errata_764369_handler( void )
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{
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#ifdef RTEMS_SMP
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_ARM_Data_synchronization_barrier();
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#endif
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}
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/*
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* @param l1LineSize Number of bytes in cache line expressed as power of
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* 2 value
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* @param l1Associativity Associativity of cache. The associativity does not
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* have to be a power of 2.
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* qparam liNumSets Number of sets in cache
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* */
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static inline void arm_cache_l1_properties_for_level(
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uint32_t *l1LineSize,
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uint32_t *l1Associativity,
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uint32_t *l1NumSets,
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uint32_t level_and_inst_dat
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)
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{
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uint32_t ccsidr;
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ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
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/* Cache line size in words + 2 -> bytes) */
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*l1LineSize = arm_ccsidr_get_line_power(ccsidr);
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/* Number of Ways */
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*l1Associativity = arm_ccsidr_get_associativity(ccsidr);
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/* Number of Sets */
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*l1NumSets = arm_ccsidr_get_num_sets(ccsidr);
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}
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/*
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* @param log_2_line_bytes The number of bytes per cache line expressed in log2
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* @param associativity The associativity of the cache beeing operated
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* @param cache_level_idx The level of the cache beeing operated minus 1 e.g 0
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* for cache level 1
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* @param set Number of the set to operate on
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* @param way Number of the way to operate on
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* */
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static inline uint32_t arm_cache_l1_get_set_way_param(
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const uint32_t log_2_line_bytes,
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const uint32_t associativity,
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const uint32_t cache_level_idx,
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const uint32_t set,
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const uint32_t way )
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{
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uint32_t way_shift = __builtin_clz( associativity - 1 );
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return ( 0
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| ( way
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<< way_shift ) | ( set << log_2_line_bytes ) | ( cache_level_idx << 1 ) );
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}
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static inline void arm_cache_l1_flush_1_data_line( const void *d_addr )
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{
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/* Flush the Data cache */
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arm_cp15_data_cache_clean_and_invalidate_line( d_addr );
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/* Wait for L1 flush to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_flush_entire_data( void )
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{
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uint32_t l1LineSize, l1Associativity, l1NumSets;
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uint32_t s, w;
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uint32_t set_way_param;
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/* ensure ordering with previous memory accesses */
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_ARM_Data_memory_barrier();
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/* Get the L1 cache properties */
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arm_cache_l1_properties_for_level( &l1LineSize,
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&l1Associativity, &l1NumSets,
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ARM_CACHE_L1_CSS_ID_DATA);
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for ( w = 0; w < l1Associativity; ++w ) {
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for ( s = 0; s < l1NumSets; ++s ) {
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set_way_param = arm_cache_l1_get_set_way_param(
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l1LineSize,
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l1Associativity,
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0,
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s,
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w
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);
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arm_cp15_data_cache_clean_line_by_set_and_way( set_way_param );
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}
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}
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/* Wait for L1 flush to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_invalidate_entire_data( void )
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{
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uint32_t l1LineSize, l1Associativity, l1NumSets;
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uint32_t s, w;
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uint32_t set_way_param;
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/* ensure ordering with previous memory accesses */
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_ARM_Data_memory_barrier();
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/* Get the L1 cache properties */
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arm_cache_l1_properties_for_level( &l1LineSize,
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&l1Associativity, &l1NumSets,
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ARM_CACHE_L1_CSS_ID_DATA);
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for ( w = 0; w < l1Associativity; ++w ) {
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for ( s = 0; s < l1NumSets; ++s ) {
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set_way_param = arm_cache_l1_get_set_way_param(
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l1LineSize,
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l1Associativity,
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0,
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s,
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w
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);
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arm_cp15_data_cache_invalidate_line_by_set_and_way( set_way_param );
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}
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}
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/* Wait for L1 invalidate to complete */
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_ARM_Data_synchronization_barrier();
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}
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static inline void arm_cache_l1_clean_and_invalidate_entire_data( void )
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{
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uint32_t l1LineSize, l1Associativity, l1NumSets;
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uint32_t s, w;
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uint32_t set_way_param;
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/* ensure ordering with previous memory accesses */
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_ARM_Data_memory_barrier();
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/* Get the L1 cache properties */
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arm_cache_l1_properties_for_level( &l1LineSize,
|
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&l1Associativity, &l1NumSets,
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ARM_CACHE_L1_CSS_ID_DATA);
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for ( w = 0; w < l1Associativity; ++w ) {
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for ( s = 0; s < l1NumSets; ++s ) {
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set_way_param = arm_cache_l1_get_set_way_param(
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l1LineSize,
|
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l1Associativity,
|
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0,
|
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s,
|
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w
|
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);
|
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arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(
|
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set_way_param );
|
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}
|
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}
|
||||
|
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/* Wait for L1 invalidate to complete */
|
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_ARM_Data_synchronization_barrier();
|
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}
|
||||
|
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static inline void arm_cache_l1_flush_data_range(
|
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const void *d_addr,
|
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size_t n_bytes
|
||||
)
|
||||
{
|
||||
if ( n_bytes != 0 ) {
|
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uint32_t adx = (uint32_t) d_addr
|
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& ~ARM_CACHE_L1_DATA_LINE_MASK;
|
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const uint32_t ADDR_LAST =
|
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(uint32_t)( (size_t) d_addr + n_bytes - 1 );
|
||||
|
||||
arm_cache_l1_errata_764369_handler();
|
||||
|
||||
for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
|
||||
/* Store and invalidate the Data cache line */
|
||||
arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx );
|
||||
}
|
||||
/* Wait for L1 store to complete */
|
||||
_ARM_Data_synchronization_barrier();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static inline void arm_cache_l1_invalidate_1_data_line(
|
||||
const void *d_addr )
|
||||
{
|
||||
/* Invalidate the data cache line */
|
||||
arm_cp15_data_cache_invalidate_line( d_addr );
|
||||
|
||||
/* Wait for L1 invalidate to complete */
|
||||
_ARM_Data_synchronization_barrier();
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_freeze_data( void )
|
||||
{
|
||||
/* To be implemented as needed, if supported by hardware at all */
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_unfreeze_data( void )
|
||||
{
|
||||
/* To be implemented as needed, if supported by hardware at all */
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_invalidate_1_instruction_line(
|
||||
const void *i_addr )
|
||||
{
|
||||
/* Invalidate the Instruction cache line */
|
||||
arm_cp15_instruction_cache_invalidate_line( i_addr );
|
||||
|
||||
/* Wait for L1 invalidate to complete */
|
||||
_ARM_Data_synchronization_barrier();
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_invalidate_data_range(
|
||||
const void *d_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
if ( n_bytes != 0 ) {
|
||||
uint32_t adx = (uint32_t) d_addr
|
||||
& ~ARM_CACHE_L1_DATA_LINE_MASK;
|
||||
const uint32_t end =
|
||||
(uint32_t)( (size_t)d_addr + n_bytes -1);
|
||||
|
||||
arm_cache_l1_errata_764369_handler();
|
||||
|
||||
/* Back starting address up to start of a line and invalidate until end */
|
||||
for (;
|
||||
adx <= end;
|
||||
adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
|
||||
/* Invalidate the Instruction cache line */
|
||||
arm_cp15_data_cache_invalidate_line( (void*)adx );
|
||||
}
|
||||
/* Wait for L1 invalidate to complete */
|
||||
_ARM_Data_synchronization_barrier();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_invalidate_instruction_range(
|
||||
const void *i_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
if ( n_bytes != 0 ) {
|
||||
uint32_t adx = (uint32_t) i_addr
|
||||
& ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
|
||||
const uint32_t end =
|
||||
(uint32_t)( (size_t)i_addr + n_bytes -1);
|
||||
|
||||
arm_cache_l1_errata_764369_handler();
|
||||
|
||||
/* Back starting address up to start of a line and invalidate until end */
|
||||
for (;
|
||||
adx <= end;
|
||||
adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
|
||||
/* Invalidate the Instruction cache line */
|
||||
arm_cp15_instruction_cache_invalidate_line( (void*)adx );
|
||||
}
|
||||
/* Wait for L1 invalidate to complete */
|
||||
_ARM_Data_synchronization_barrier();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_invalidate_entire_instruction( void )
|
||||
{
|
||||
uint32_t ctrl = arm_cp15_get_control();
|
||||
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
|
||||
/* invalidate I-cache inner shareable */
|
||||
arm_cp15_instruction_cache_inner_shareable_invalidate_all();
|
||||
|
||||
/* I+BTB cache invalidate */
|
||||
arm_cp15_instruction_cache_invalidate();
|
||||
#else /* RTEMS_SMP */
|
||||
/* I+BTB cache invalidate */
|
||||
arm_cp15_instruction_cache_invalidate();
|
||||
#endif /* RTEMS_SMP */
|
||||
|
||||
if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) {
|
||||
#if defined(__ARM_ARCH_7A__)
|
||||
arm_cp15_branch_predictor_inner_shareable_invalidate_all();
|
||||
#endif
|
||||
#if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__)
|
||||
arm_cp15_branch_predictor_invalidate_all();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_freeze_instruction( void )
|
||||
{
|
||||
/* To be implemented as needed, if supported by hardware at all */
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_unfreeze_instruction( void )
|
||||
{
|
||||
/* To be implemented as needed, if supported by hardware at all */
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_disable_data( void )
|
||||
{
|
||||
/* Clean and invalidate the Data cache */
|
||||
arm_cache_l1_flush_entire_data();
|
||||
|
||||
/* Disable the Data cache */
|
||||
arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
|
||||
}
|
||||
|
||||
static inline void arm_cache_l1_disable_instruction( void )
|
||||
{
|
||||
/* Synchronize the processor */
|
||||
_ARM_Data_synchronization_barrier();
|
||||
|
||||
/* Invalidate the Instruction cache */
|
||||
arm_cache_l1_invalidate_entire_instruction();
|
||||
|
||||
/* Disable the Instruction cache */
|
||||
arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
|
||||
}
|
||||
|
||||
static inline size_t arm_cache_l1_get_data_cache_size( void )
|
||||
{
|
||||
size_t size;
|
||||
uint32_t line_size = 0;
|
||||
uint32_t associativity = 0;
|
||||
uint32_t num_sets = 0;
|
||||
|
||||
arm_cache_l1_properties_for_level( &line_size,
|
||||
&associativity, &num_sets,
|
||||
ARM_CACHE_L1_CSS_ID_DATA);
|
||||
|
||||
size = (1 << line_size) * associativity * num_sets;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static inline size_t arm_cache_l1_get_instruction_cache_size( void )
|
||||
{
|
||||
size_t size;
|
||||
uint32_t line_size = 0;
|
||||
uint32_t associativity = 0;
|
||||
uint32_t num_sets = 0;
|
||||
|
||||
arm_cache_l1_properties_for_level( &line_size,
|
||||
&associativity, &num_sets,
|
||||
ARM_CACHE_L1_CSS_ID_INSTRUCTION);
|
||||
|
||||
size = (1 << line_size) * associativity * num_sets;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_SHARED_CACHE_L1_H */
|
||||
1333
bsps/arm/shared/cache/cache-l2c-310.c
vendored
Normal file
1333
bsps/arm/shared/cache/cache-l2c-310.c
vendored
Normal file
File diff suppressed because it is too large
Load Diff
141
bsps/arm/shared/cache/cache-v7m.c
vendored
Normal file
141
bsps/arm/shared/cache/cache-v7m.c
vendored
Normal file
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright (c) 2016 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <chip.h>
|
||||
|
||||
#define CPU_DATA_CACHE_ALIGNMENT 32
|
||||
|
||||
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
|
||||
|
||||
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
|
||||
|
||||
static inline void _CPU_cache_flush_data_range(
|
||||
const void *d_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
SCB_CleanInvalidateDCache_by_Addr(
|
||||
RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
|
||||
n_bytes
|
||||
);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_invalidate_data_range(
|
||||
const void *d_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
SCB_InvalidateDCache_by_Addr(
|
||||
RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
|
||||
n_bytes
|
||||
);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_freeze_data(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_unfreeze_data(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_invalidate_instruction_range(
|
||||
const void *i_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_InvalidateICache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_freeze_instruction(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_unfreeze_instruction(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_flush_entire_data(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_CleanDCache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_invalidate_entire_data(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_InvalidateDCache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_enable_data(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_EnableDCache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_disable_data(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_DisableDCache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_invalidate_entire_instruction(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_InvalidateICache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_enable_instruction(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_EnableICache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_disable_instruction(void)
|
||||
{
|
||||
rtems_interrupt_level level;
|
||||
|
||||
rtems_interrupt_disable(level);
|
||||
SCB_DisableICache();
|
||||
rtems_interrupt_enable(level);
|
||||
}
|
||||
|
||||
#include "../../shared/cache/cacheimpl.h"
|
||||
Reference in New Issue
Block a user