forked from Imagelibrary/rtems
bsps: Convert README to MarkDown
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@@ -1,76 +0,0 @@
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# Goal is to have BSPs build almost completely automatically from a template
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# and information that comes from SOPC Builder as a .PTF file. Most of the
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# code will go to a shared/ BSP directory.
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#
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# Ideally, updates to the PTF shouldn't cause any pain for the maintainer
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# of a specific BSP (possibly with enhancements not covered by the
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# automatic BSP creation).
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#
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# Some first steps toward utilizing SOPC Builder PTF output can be found
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# in top level /tools/cpu/nios2. Also see the README there.
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#
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# Implemented (in shared/ subdirectory)
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# Clock driver
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# Timer driver
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# Console via JTAG UART
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#
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# Todo;
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# Support more peripherals. My priorities:
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# - (improve) Altera Avalon JTAG UART
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# - Altera Avalon UART
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# - OpenCores.org I2C Master
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# - Altera SPI Core / EPCS Configuration Device
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# - OpenCores.org 10/100 Ethernet MAC (use existing driver)
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# - (more) Altera Avalon Timer
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#
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# Put all drivers aside in a shared/ subdirectory.
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# Update the "times" file for NIOS2 with and without icache.
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#
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# Missing (although it looks like it's there)
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# Data cache handling (for now, don't use the "fast" NIOS2)
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# SHM support (just taken over the code from no_cpu/no_bsp)
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#
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# Kolja Waschk, 6/2006
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#
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BSP NAME: nios2_eb2_1
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BOARD: Altera Instruction Set Simulator Default plus second timer
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BUS: Avalon
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CPU FAMILY: nios2
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CPU: small
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COPROCESSORS: none
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MODE: 32 bit mode
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DEBUG MONITOR: none
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PERIPHERALS
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===========
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TIMERS: Altera Avalon Timer
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RESOLUTION: .0001 microseconds
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SERIAL PORTS: Altera Avalon JTAG UART
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REAL-TIME CLOCK: none
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DMA: none
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VIDEO: none
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SCSI: none
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NETWORKING: none
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DRIVER INFORMATION
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==================
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CLOCK DRIVER: Altera Avalon Timer
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IOSUPP DRIVER: none
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SHMSUPP: polled
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TIMER DRIVER: Altera Avalon Timer
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TTY DRIVER: none
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STDIO
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=====
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PORT: Console port 0
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ELECTRICAL: JTAG
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BAUD: 115200
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BITS PER CHARACTER: 8
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PARITY: None
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STOP BITS: 1
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NOTES
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=====
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80
bsps/nios2/README.md
Normal file
80
bsps/nios2/README.md
Normal file
@@ -0,0 +1,80 @@
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nios2
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=====
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Goal is to have BSPs build almost completely automatically from a template
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and information that comes from SOPC Builder as a .PTF file. Most of the
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code will go to a shared/ BSP directory.
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Ideally, updates to the PTF shouldn't cause any pain for the maintainer
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of a specific BSP (possibly with enhancements not covered by the
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automatic BSP creation).
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||||
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Some first steps toward utilizing SOPC Builder PTF output can be found
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in top level /tools/cpu/nios2. Also see the README there.
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Implemented (in shared/ subdirectory)
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Clock driver
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Timer driver
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Console via JTAG UART
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||||
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Todo;
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Support more peripherals. My priorities:
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- (improve) Altera Avalon JTAG UART
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||||
- Altera Avalon UART
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- OpenCores.org I2C Master
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- Altera SPI Core / EPCS Configuration Device
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- OpenCores.org 10/100 Ethernet MAC (use existing driver)
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- (more) Altera Avalon Timer
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||||
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Put all drivers aside in a shared/ subdirectory.
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Update the "times" file for NIOS2 with and without icache.
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||||
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Missing (although it looks like it's there)
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Data cache handling (for now, don't use the "fast" NIOS2)
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SHM support (just taken over the code from no_cpu/no_bsp)
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```
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BSP NAME: nios2_eb2_1
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BOARD: Altera Instruction Set Simulator Default plus second timer
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BUS: Avalon
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CPU FAMILY: nios2
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CPU: small
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COPROCESSORS: none
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MODE: 32 bit mode
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DEBUG MONITOR: none
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```
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PERIPHERALS
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-----------
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```
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TIMERS: Altera Avalon Timer
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RESOLUTION: .0001 microseconds
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SERIAL PORTS: Altera Avalon JTAG UART
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REAL-TIME CLOCK: none
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DMA: none
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VIDEO: none
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SCSI: none
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NETWORKING: none
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```
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DRIVER INFORMATION
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------------------
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```
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CLOCK DRIVER: Altera Avalon Timer
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IOSUPP DRIVER: none
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SHMSUPP: polled
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TIMER DRIVER: Altera Avalon Timer
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TTY DRIVER: none
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```
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STDIO
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-----
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```
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PORT: Console port 0
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ELECTRICAL: JTAG
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BAUD: 115200
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BITS PER CHARACTER: 8
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PARITY: None
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STOP BITS: 1
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```
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