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various changes to gen83xx BSP and others

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This commit is contained in:
Thomas Doerfler
2008-08-26 11:55:31 +00:00
parent 0fc02b16c2
commit 4b23c94504
14 changed files with 175 additions and 29 deletions
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10
c/src/lib/libcpu/powerpc/ChangeLog
View File

@@ -1,3 +1,13 @@
2008-08-26 Thomas Doerfler <Thomas.Doerflerr@embedded-brains.de>
* mpc83xx/i2c/mpc83xx_i2cdrv.c: wait for proper end of transfer
* mpc83xx/include/mpc83xx.h: add some register definitions
2008-08-26 Sebastian Huber <sebastian.huber@embedded-brains.de>
* mpc83xx/network/tsec.c: Clear the interrupt mask and all pending
events during the hardware initialization.
2008-08-22 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/include/powerpc-utility.h: Fixed parameter evaluation in

11
c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c
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@@ -172,6 +172,11 @@ static void mpc83xx_i2c_irq_handler
{
mpc83xx_i2c_softc_t *softc_ptr = (mpc83xx_i2c_softc_t *)handle;
/*
* clear IRQ flag
*/
softc_ptr->reg_ptr->i2csr &= ~MPC83XX_I2CSR_MIF;
/*
* disable interrupt mask
*/
@@ -561,6 +566,12 @@ static int mpc83xx_i2c_read_bytes
*p++ = softc_ptr->reg_ptr->i2cdr;
}
/*
* wait 'til end of last transfer
*/
rc = mpc83xx_i2c_wait(softc_ptr, MPC83XX_I2CSR_MCF, MPC83XX_I2CSR_MCF);
#if defined(DEBUG)
printk("... exit OK, rc=%d\r\n",p-buf);
#endif

63
c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
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@@ -67,7 +67,7 @@ typedef struct m83xxSysConRegisters_ {
volatile uint32_t sicrl; /* 0x0_0114 I/O configuration register low (SICRL) R/W 0x0000_0000 5.3.2.5/5-21 */
volatile uint32_t sicrh; /* 0x0_0118 I/O configuration register high (SICRH) R/W 0x0000_00007 5.3.2.6/5-24 */
uint8_t reserved0_011C[0x00128-0x0011C];/* 0x0_011C--0x0_0128 Reserved */
volatile uint32_t ddrcdr; /* 0x0_0128 control driver register (DDRCDR) R/W 0x0004_0000 5.3.2.8/5-28 */
volatile uint32_t ddrcdr; /* 0x0_0128 control driver register (DDRCDR) R/W 0x7304_0001 5.3.2.8/5-28 */
volatile uint32_t ddrdsr; /* 0x0_012C debug status register (DDRDSR) R 0x3300_0000 5.3.2.9/5-30 */
uint8_t reserved0_0130[0x00200-0x00130];/* 0x0_0130--0x0_01FC Reserved */
} m83xxSysConRegisters_t;
@@ -421,7 +421,7 @@ typedef struct m83xxDMARegisters_ {
volatile uint32_t imisr; /* 0x0_8080 Inbound message interrupt status register R/W 0x0000_0000 12.4.6/12-9 */
volatile uint32_t imimr; /* 0x0_8084 Inbound message interrupt mask register R/W 0x0000_0000 12.4.7/12-11 */
uint8_t reserved0_8088[0x080A8-0x08088];/* 0x0_8088-0x0_80A7 Reserved */
struct {
struct m83xxDMAChannelRegisters_ {
uint8_t reserved0_80A8[0x08100-0x080A8];/* 0x0_80A8-0x0_80FF Reserved */
volatile uint32_t dmamr0; /* 0x0_8100 DMA 0 mode register R/W 0x0000_0000 12.4.8.1/12-12 */
volatile uint32_t dmasr0; /* 0x0_8104 DMA 0 status register R/W 0x0000_0000 12.4.8.2/12-14 */
@@ -438,6 +438,65 @@ typedef struct m83xxDMARegisters_ {
uint8_t reserved0_82AC[0x082FF-0x082AC]; /* 0x0_82AC-0x0_82FF Reserved, should be cleared */
} m83xxDMARegisters_t;
/* Registers in DMA section use little-endian byte order */
/* DMA mode register */
#define MPC83XX_DMAMR_DRCNT_1 (5 << 24)
#define MPC83XX_DMAMR_DRCNT_2 (6 << 24)
#define MPC83XX_DMAMR_DRCNT_4 (7 << 24)
#define MPC83XX_DMAMR_DRCNT_8 (8 << 24)
#define MPC83XX_DMAMR_DRCNT_16 (9 << 24)
#define MPC83XX_DMAMR_DRCNT_32 (0xA << 24)
#define MPC83XX_DMAMR_BWC_1 (0 << 21)
#define MPC83XX_DMAMR_BWC_2 (1 << 21)
#define MPC83XX_DMAMR_BWC_4 (2 << 21)
#define MPC83XX_DMAMR_BWC_8 (3 << 21)
#define MPC83XX_DMAMR_BWC_16 (4 << 21)
#define MPC83XX_DMAMR_DMSEN (1 << 20)
#define MPC83XX_DMAMR_IRQS (1 << 19)
#define MPC83XX_DMAMR_EMSEN (1 << 18)
#define MPC83XX_DMAMR_DAHTS_1 (0 << 16)
#define MPC83XX_DMAMR_DAHTS_2 (1 << 16)
#define MPC83XX_DMAMR_DAHTS_4 (2 << 16)
#define MPC83XX_DMAMR_DAHTS_8 (3 << 16)
#define MPC83XX_DMAMR_SAHTS_1 (0 << 14)
#define MPC83XX_DMAMR_SAHTS_2 (1 << 14)
#define MPC83XX_DMAMR_SAHTS_4 (2 << 14)
#define MPC83XX_DMAMR_SAHTS_8 (3 << 14)
#define MPC83XX_DMAMR_DAHE (1 << 13)
#define MPC83XX_DMAMR_SAHE (1 << 12)
#define MPC83XX_DMAMR_PRC_PCI_READ (0 << 10)
#define MPC83XX_DMAMR_PRC_PCI_READ_LINE (1 << 10)
#define MPC83XX_DMAMR_PRC_PCI_READ_MULTIPLE (2 << 10)
#define MPC83XX_DMAMR_EOIIE (1 << 7)
#define MPC83XX_DMAMR_TEM (1 << 3)
#define MPC83XX_DMAMR_CTM (1 << 2)
#define MPC83XX_DMAMR_CC (1 << 1)
#define MPC83XX_DMAMR_CS (1 << 0)
/* DMA status register */
#define MPC83XX_DMASR_TE (1 << 7)
#define MPC83XX_DMASR_CB (1 << 2)
#define MPC83XX_DMASR_EOSI (1 << 1)
#define MPC83XX_DMASR_EOCDI (1 << 0)
/* DMA current descriptor address register */
#define MPC83XX_DMACDAR_SNEN (1 << 4)
#define MPC83XX_DMACDAR_EOSIE (1 << 3)
/* DMA next descriptor address register */
#define MPC83XX_DMANDAR_NSNEN (1 << 4)
#define MPC83XX_DMANDAR_NEOSIE (1 << 3)
#define MPC83XX_DMANDAR_EOTD (1 << 0)
typedef struct m83xxPCICfgRegisters_ {
/* PCI1 Software Configuration Registers */
volatile uint32_t config_address; /* 0x0_8300 PCI1 CONFIG_ADDRESS W 13.3.1.1/13-16 */

17
c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
View File

@@ -203,6 +203,10 @@ static void mpc83xx_tsec_hwinit
uint8_t *mac_addr;
size_t i;
/* Clear interrupt mask and all pending events */
reg_ptr->imask = 0;
reg_ptr->ievent = 0xffffffff;
/*
* init ECNTL register
* - clear statistics counters
@@ -211,7 +215,8 @@ static void mpc83xx_tsec_hwinit
*/
reg_ptr->ecntrl = ((reg_ptr->ecntrl & ~M83xx_TSEC_ECNTRL_AUTOZ)
| M83xx_TSEC_ECNTRL_CLRCNT
| M83xx_TSEC_ECNTRL_STEN);
| M83xx_TSEC_ECNTRL_STEN
| M83xx_TSEC_ECNTRL_R100M);
/*
* init DMA control register:
@@ -281,9 +286,9 @@ static void mpc83xx_tsec_hwinit
/*
* init MACCFG2 register
*/
reg_ptr->maccfg2 = (reg_ptr->maccfg2 & M83xx_TSEC_MACCFG2_IFMODE_MSK)
| M83xx_TSEC_MACCFG2_PRELEN( 7)
| M83xx_TSEC_MACCFG2_FULLDUPLEX;
reg_ptr->maccfg2 = ((reg_ptr->maccfg2 & M83xx_TSEC_MACCFG2_IFMODE_MSK)
| M83xx_TSEC_MACCFG2_PRELEN( 7)
| M83xx_TSEC_MACCFG2_FULLDUPLEX);
/*
* init station address register
@@ -1508,9 +1513,7 @@ static void mpc83xx_tsec_init
* for HSC CM01: we need to configure the PHY to use maximum skew adjust
*/
mpc83xx_tsec_mdio_write(-1,sc,31,1);
mpc83xx_tsec_mdio_write(-1,sc,28,0xf000);
mpc83xx_tsec_mdio_write(-1,sc,31,0);
mpc83xx_tsec_mdio_write(-1,sc,23,0x0100);
#endif
/*