score: Rename _ISR_Disable_without_giant()

Rename _ISR_Disable_without_giant() into _ISR_Local_disable().  Rename
_ISR_Enable_without_giant() into _ISR_Local_enable().

This is a preparation to remove the Giant lock.

Update #2555.

c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h

@@ -588,11 +588,11 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
     ISR_Level level; \
     uint32_t val; \
     uint32_t mybits = bits; \
-    _ISR_Disable_without_giant(level); \
+    _ISR_Local_disable(level); \
     val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
     val |= mybits; \
     PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
-    _ISR_Enable_without_giant(level); \
+    _ISR_Local_enable(level); \
   } while (0)
 
 /**
@@ -608,12 +608,12 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
     uint32_t val; \
     uint32_t mybits = bits; \
     uint32_t mymask = mask; \
-    _ISR_Disable_without_giant(level); \
+    _ISR_Local_disable(level); \
     val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
     val &= ~mymask; \
     val |= mybits; \
     PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
-    _ISR_Enable_without_giant(level); \
+    _ISR_Local_enable(level); \
   } while (0)
 
 /**
@@ -627,11 +627,11 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
     ISR_Level level; \
     uint32_t val; \
     uint32_t mybits = bits; \
-    _ISR_Disable_without_giant(level); \
+    _ISR_Local_disable(level); \
     val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
     val &= ~mybits; \
     PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
-    _ISR_Enable_without_giant(level); \
+    _ISR_Local_enable(level); \
   } while (0)
 
 /**
@@ -705,11 +705,11 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
     ISR_Level level; \
     uint32_t val; \
     uint32_t mybits = bits; \
-    _ISR_Disable_without_giant(level); \
+    _ISR_Local_disable(level); \
     val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
     val |= mybits; \
     PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
-    _ISR_Enable_without_giant(level); \
+    _ISR_Local_enable(level); \
   } while (0)
 
 /**
@@ -725,12 +725,12 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
     uint32_t val; \
     uint32_t mybits = bits; \
     uint32_t mymask = mask; \
-    _ISR_Disable_without_giant(level); \
+    _ISR_Local_disable(level); \
     val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
     val &= ~mymask; \
     val |= mybits; \
     PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
-    _ISR_Enable_without_giant(level); \
+    _ISR_Local_enable(level); \
   } while (0)
 
 /**
@@ -744,11 +744,11 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
     ISR_Level level; \
     uint32_t val; \
     uint32_t mybits = bits; \
-    _ISR_Disable_without_giant(level); \
+    _ISR_Local_disable(level); \
     val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
     val &= ~mybits; \
     PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
-    _ISR_Enable_without_giant(level); \
+    _ISR_Local_enable(level); \
   } while (0)
 
 static inline uint32_t ppc_time_base(void)

cpukit/rtems/include/rtems/rtems/intr.h

@@ -139,7 +139,7 @@ rtems_status_code rtems_interrupt_catch(
  * @see rtems_interrupt_local_enable().
  */
 #define rtems_interrupt_local_disable( _isr_cookie ) \
-  _ISR_Disable_without_giant( _isr_cookie )
+  _ISR_Local_disable( _isr_cookie )
 
 /**
  * @brief This macro restores the previous interrupt level on the current
@@ -149,7 +149,7 @@ rtems_status_code rtems_interrupt_catch(
  *   rtems_interrupt_local_disable().
  */
 #define rtems_interrupt_local_enable( _isr_cookie ) \
-  _ISR_Enable_without_giant( _isr_cookie )
+  _ISR_Local_enable( _isr_cookie )
 
 /**
  *  @brief RTEMS Interrupt Is in Progress

cpukit/score/cpu/sparc/sparcv8-atomic.c

@@ -47,7 +47,7 @@ static ISR_Level _SPARCV8_Acquire_the_one_lock( void )
 {
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 
 #if defined(RTEMS_SMP)
   do {
@@ -65,7 +65,7 @@ static void _SPARCV8_Release_the_one_lock( ISR_Level level )
 #if defined(RTEMS_SMP)
   _SPARCV8_The_one_lock = 0;
 #endif
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 }
 
 uint8_t __atomic_exchange_1( uint8_t *mem, uint8_t val, int model )

cpukit/score/include/rtems/score/isrlevel.h

@@ -136,13 +136,13 @@ typedef uint32_t   ISR_Level;
     RTEMS_COMPILER_MEMORY_BARRIER();  \
   } while (0)
 
-#define _ISR_Disable_without_giant( _level ) \
+#define _ISR_Local_disable( _level ) \
   do { \
     _CPU_ISR_Disable( _level ); \
     RTEMS_COMPILER_MEMORY_BARRIER(); \
   } while (0)
 
-#define _ISR_Enable_without_giant( _level ) \
+#define _ISR_Local_enable( _level ) \
   do { \
     RTEMS_COMPILER_MEMORY_BARRIER(); \
     _CPU_ISR_Enable( _level ); \

cpukit/score/include/rtems/score/isrlock.h

@@ -351,7 +351,7 @@ typedef struct {
 #if defined( RTEMS_SMP )
   #define _ISR_lock_ISR_disable( _context ) \
     do { \
-      _ISR_Disable_without_giant( ( _context )->Lock_context.isr_level ); \
+      _ISR_Local_disable( ( _context )->Lock_context.isr_level ); \
       _ISR_lock_ISR_disable_profile( _context ) \
     } while ( 0 )
 #else
@@ -374,7 +374,7 @@ typedef struct {
  */
 #if defined( RTEMS_SMP )
   #define _ISR_lock_ISR_enable( _context ) \
-    _ISR_Enable_without_giant( ( _context )->Lock_context.isr_level )
+    _ISR_Local_enable( ( _context )->Lock_context.isr_level )
 #else
   #define _ISR_lock_ISR_enable( _context ) \
     _ISR_Enable( ( _context )->isr_level )

cpukit/score/include/rtems/score/mrspimpl.h

@@ -251,9 +251,9 @@ RTEMS_INLINE_ROUTINE MRSP_Status _MRSP_Wait_for_ownership(
   if ( timeout > 0 ) {
     _Watchdog_Preinitialize( &rival.Watchdog, cpu_self );
     _Watchdog_Initialize( &rival.Watchdog, _MRSP_Timeout );
-    _ISR_Disable_without_giant( level );
+    _ISR_Local_disable( level );
     _Watchdog_Per_CPU_insert_relative( &rival.Watchdog, cpu_self, timeout );
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
   }
 
   life_state = _Thread_Set_life_protection( THREAD_LIFE_PROTECTED );
@@ -269,13 +269,13 @@ RTEMS_INLINE_ROUTINE MRSP_Status _MRSP_Wait_for_ownership(
   _Thread_Set_life_protection( life_state );
 
   if ( timeout > 0 ) {
-    _ISR_Disable_without_giant( level );
+    _ISR_Local_disable( level );
     _Watchdog_Per_CPU_remove(
       &rival.Watchdog,
       cpu_self,
       &cpu_self->Watchdog.Header[ PER_CPU_WATCHDOG_RELATIVE ]
     );
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
 
     if ( status == MRSP_TIMEOUT ) {
       _MRSP_Restore_priority( executing, initial_priority );

cpukit/score/include/rtems/score/percpu.h

@@ -493,7 +493,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
 #if defined( RTEMS_SMP )
 #define _Per_CPU_ISR_disable_and_acquire( cpu, isr_cookie ) \
   do { \
-    _ISR_Disable_without_giant( isr_cookie ); \
+    _ISR_Local_disable( isr_cookie ); \
     _Per_CPU_Acquire( cpu ); \
   } while ( 0 )
 #else
@@ -508,7 +508,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
 #define _Per_CPU_Release_and_ISR_enable( cpu, isr_cookie ) \
   do { \
     _Per_CPU_Release( cpu ); \
-    _ISR_Enable_without_giant( isr_cookie ); \
+    _ISR_Local_enable( isr_cookie ); \
   } while ( 0 )
 #else
 #define _Per_CPU_Release_and_ISR_enable( cpu, isr_cookie ) \
@@ -523,7 +523,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
   do { \
     uint32_t ncpus = _SMP_Get_processor_count(); \
     uint32_t cpu; \
-    _ISR_Disable_without_giant( isr_cookie ); \
+    _ISR_Local_disable( isr_cookie ); \
     for ( cpu = 0 ; cpu < ncpus ; ++cpu ) { \
       _Per_CPU_Acquire( _Per_CPU_Get_by_index( cpu ) ); \
     } \
@@ -541,7 +541,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
     for ( cpu = 0 ; cpu < ncpus ; ++cpu ) { \
       _Per_CPU_Release( _Per_CPU_Get_by_index( cpu ) ); \
     } \
-    _ISR_Enable_without_giant( isr_cookie ); \
+    _ISR_Local_enable( isr_cookie ); \
   } while ( 0 )
 #else
 #define _Per_CPU_Release_all( isr_cookie ) \
@@ -709,13 +709,13 @@ RTEMS_INLINE_ROUTINE struct _Thread_Control *_Thread_Get_executing( void )
   #if defined( RTEMS_SMP )
     ISR_Level level;
 
-    _ISR_Disable_without_giant( level );
+    _ISR_Local_disable( level );
   #endif
 
   executing = _Thread_Executing;
 
   #if defined( RTEMS_SMP )
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
   #endif
 
   return executing;

cpukit/score/include/rtems/score/smplock.h

@@ -251,7 +251,7 @@ static inline void _SMP_lock_ISR_disable_and_acquire(
   SMP_lock_Context *context
 )
 {
-  _ISR_Disable_without_giant( context->isr_level );
+  _ISR_Local_disable( context->isr_level );
   _SMP_lock_Acquire( lock, context );
 }
 
@@ -274,7 +274,7 @@ static inline void _SMP_lock_Release_and_ISR_enable(
 )
 {
   _SMP_lock_Release( lock, context );
-  _ISR_Enable_without_giant( context->isr_level );
+  _ISR_Local_enable( context->isr_level );
 }
 #endif
 

cpukit/score/include/rtems/score/threaddispatch.h

@@ -54,13 +54,13 @@ RTEMS_INLINE_ROUTINE bool _Thread_Dispatch_is_enabled(void)
 #if defined(RTEMS_SMP)
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 #endif
 
   enabled = _Thread_Dispatch_disable_level == 0;
 
 #if defined(RTEMS_SMP)
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 #endif
 
   return enabled;
@@ -325,7 +325,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self )
   if ( disable_level == 1 ) {
     ISR_Level level;
 
-    _ISR_Disable_without_giant( level );
+    _ISR_Local_disable( level );
 
     if ( cpu_self->dispatch_necessary ) {
       _Thread_Do_dispatch( cpu_self, level );
@@ -334,7 +334,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable( Per_CPU_Control *cpu_self )
       _Profiling_Thread_dispatch_enable( cpu_self, 0 );
     }
 
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
   } else {
     cpu_self->thread_dispatch_disable_level = disable_level - 1;
   }

cpukit/score/include/rtems/score/threadimpl.h

@@ -1381,7 +1381,7 @@ RTEMS_INLINE_ROUTINE bool _Thread_Wait_flags_try_change(
 #if !defined(RTEMS_SMP)
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 #endif
 
   success = _Thread_Wait_flags_try_change_critical(
@@ -1391,7 +1391,7 @@ RTEMS_INLINE_ROUTINE bool _Thread_Wait_flags_try_change(
   );
 
 #if !defined(RTEMS_SMP)
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 #endif
 
   return success;

cpukit/score/src/debugisthreaddispatchingallowed.c

@@ -26,10 +26,10 @@
     ISR_Level level;
     Per_CPU_Control *cpu_self;
 
-    _ISR_Disable_without_giant( level );
+    _ISR_Local_disable( level );
     cpu_self = _Per_CPU_Get_snapshot();
     dispatch_allowed = cpu_self->thread_dispatch_disable_level == 0;
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
 
     return dispatch_allowed;
   }

cpukit/score/src/interr.c

@@ -36,7 +36,7 @@ void _Terminate(
 {
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
   (void) level;
 
   _SMP_Request_shutdown();

cpukit/score/src/isrisinprogress.c

@@ -36,13 +36,13 @@ bool _ISR_Is_in_progress( void )
   #if defined( RTEMS_SMP )
     ISR_Level level;
 
-    _ISR_Disable_without_giant( level );
+    _ISR_Local_disable( level );
   #endif
 
   isr_nest_level = _ISR_Nest_level;
 
   #if defined( RTEMS_SMP )
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
   #endif
 
   return isr_nest_level != 0;

cpukit/score/src/smplock.c

@@ -89,7 +89,7 @@ void _SMP_lock_Release_and_ISR_enable(
   lock->owner = SMP_LOCK_NO_OWNER;
 #endif
   _SMP_lock_Release_body( lock, context );
-  _ISR_Enable_without_giant( context->isr_level );
+  _ISR_Local_enable( context->isr_level );
 }
 
 #if defined(RTEMS_DEBUG)

cpukit/score/src/smpmulticastaction.c

@@ -74,7 +74,7 @@ _SMP_Multicast_actions_try_process( void )
   Per_CPU_Control *cpu_self;
   ISR_Level isr_level;
 
-  _ISR_Disable_without_giant( isr_level );
+  _ISR_Local_disable( isr_level );
 
   cpu_self = _Per_CPU_Get();
 
@@ -88,7 +88,7 @@ _SMP_Multicast_actions_try_process( void )
     }
   }
 
-  _ISR_Enable_without_giant( isr_level );
+  _ISR_Local_enable( isr_level );
 }
 
 void _SMP_Multicast_action(

cpukit/score/src/threaddispatch.c

@@ -137,7 +137,7 @@ post_switch:
   cpu_self->thread_dispatch_disable_level = 0;
   _Profiling_Thread_dispatch_enable( cpu_self, 0 );
 
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 
   _Thread_Run_post_switch_actions( executing );
 }
@@ -147,7 +147,7 @@ void _Thread_Dispatch( void )
   ISR_Level        level;
   Per_CPU_Control *cpu_self;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 
   cpu_self = _Per_CPU_Get();
 
@@ -156,6 +156,6 @@ void _Thread_Dispatch( void )
     cpu_self->thread_dispatch_disable_level = 1;
     _Thread_Do_dispatch( cpu_self, level );
   } else {
-    _ISR_Enable_without_giant( level );
+    _ISR_Local_enable( level );
   }
 }

cpukit/score/src/threaddispatchdisablelevel.c

@@ -77,7 +77,7 @@ uint32_t _Thread_Dispatch_increment_disable_level( void )
   uint32_t disable_level;
   Per_CPU_Control *cpu_self;
 
-  _ISR_Disable_without_giant( isr_level );
+  _ISR_Local_disable( isr_level );
 
   /*
    * We must obtain the processor after interrupts are disabled to prevent
@@ -92,7 +92,7 @@ uint32_t _Thread_Dispatch_increment_disable_level( void )
   ++disable_level;
   cpu_self->thread_dispatch_disable_level = disable_level;
 
-  _ISR_Enable_without_giant( isr_level );
+  _ISR_Local_enable( isr_level );
 
   return disable_level;
 }
@@ -103,7 +103,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
   uint32_t disable_level;
   Per_CPU_Control *cpu_self;
 
-  _ISR_Disable_without_giant( isr_level );
+  _ISR_Local_disable( isr_level );
 
   cpu_self = _Per_CPU_Get();
   disable_level = cpu_self->thread_dispatch_disable_level;
@@ -114,7 +114,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
   _Giant_Do_release( cpu_self );
 
   _Profiling_Thread_dispatch_enable( cpu_self, disable_level );
-  _ISR_Enable_without_giant( isr_level );
+  _ISR_Local_enable( isr_level );
 
   return disable_level;
 }
@@ -123,20 +123,20 @@ void _Giant_Acquire( Per_CPU_Control *cpu_self )
 {
   ISR_Level isr_level;
 
-  _ISR_Disable_without_giant( isr_level );
+  _ISR_Local_disable( isr_level );
   _Assert( _Thread_Dispatch_disable_level != 0 );
   _Giant_Do_acquire( cpu_self );
-  _ISR_Enable_without_giant( isr_level );
+  _ISR_Local_enable( isr_level );
 }
 
 void _Giant_Release( Per_CPU_Control *cpu_self )
 {
   ISR_Level isr_level;
 
-  _ISR_Disable_without_giant( isr_level );
+  _ISR_Local_disable( isr_level );
   _Assert( _Thread_Dispatch_disable_level != 0 );
   _Giant_Do_release( cpu_self );
-  _ISR_Enable_without_giant( isr_level );
+  _ISR_Local_enable( isr_level );
 }
 
 #if defined( RTEMS_DEBUG )

cpukit/score/src/threadhandler.c

@@ -69,7 +69,7 @@ void _Thread_Handler( void )
    * Do not use the level of the thread control block, since it has a
    * different format.
    */
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 
   /*
    *  At this point, the dispatch disable level BETTER be 1.

testsuites/smptests/smpcache01/init.c

@@ -158,11 +158,11 @@ static void call_tests_isr_disabled( size_t set_size,
   for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) {
     ISR_Level isr_level;
 
-    _ISR_Disable_without_giant( isr_level );
+    _ISR_Local_disable( isr_level );
 
     call_test( set_size, cpu_set, bs, i );
 
-    _ISR_Enable_without_giant( isr_level );
+    _ISR_Local_enable( isr_level );
   }
 }
 

testsuites/smptests/smpload01/init.c

@@ -225,7 +225,7 @@ static void get_obtain_delay_estimate(test_context *ctx)
 
   _SMP_lock_Initialize(&lock, "test");
 
-  _ISR_Disable_without_giant(level);
+  _ISR_Local_disable(level);
 
   for (i = 0; i < n; ++i) {
     SMP_lock_Context lock_context;
@@ -240,7 +240,7 @@ static void get_obtain_delay_estimate(test_context *ctx)
     t[i] = rtems_counter_difference(b, a);
   }
 
-  _ISR_Enable_without_giant(level);
+  _ISR_Local_enable(level);
 
   _SMP_lock_Destroy(&lock);
 

testsuites/smptests/smpthreadlife01/init.c

@@ -200,7 +200,7 @@ static void delay_ipi_task(rtems_task_argument variant)
   test_context *ctx = &test_instance;
   ISR_Level level;
 
-  _ISR_Disable_without_giant(level);
+  _ISR_Local_disable(level);
 
   /* (C) */
   barrier(ctx, &ctx->worker_barrier_state);
@@ -215,7 +215,7 @@ static void delay_ipi_task(rtems_task_argument variant)
     _Thread_Dispatch_disable();
   }
 
-  _ISR_Enable_without_giant(level);
+  _ISR_Local_enable(level);
 
   /*
    * We get deleted as a side effect of enabling the thread life protection or
@@ -267,7 +267,7 @@ static void delay_switch_task(rtems_task_argument arg)
   rtems_status_code sc;
   ISR_Level level;
 
-  _ISR_Disable_without_giant(level);
+  _ISR_Local_disable(level);
   (void) level;
 
   ctx->delay_switch_for_executing = _Thread_Get_executing();
@@ -403,7 +403,7 @@ static void op_worker_task(rtems_task_argument arg)
   test_op op = arg;
   ISR_Level level;
 
-  _ISR_Disable_without_giant(level);
+  _ISR_Local_disable(level);
   (void) level;
 
   /* (E) */

testsuites/tmtests/tm26/task1.c

@@ -94,7 +94,7 @@ static void set_thread_dispatch_necessary( bool dispatch_necessary )
 #if defined( PREVENT_SMP_ASSERT_FAILURES )
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 #endif
 
   _Thread_Dispatch_necessary = dispatch_necessary;
@@ -104,7 +104,7 @@ static void set_thread_dispatch_necessary( bool dispatch_necessary )
   }
 
 #if defined( PREVENT_SMP_ASSERT_FAILURES )
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 #endif
 }
 
@@ -113,13 +113,13 @@ static void set_thread_heir( Thread_Control *thread )
 #if defined( PREVENT_SMP_ASSERT_FAILURES )
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 #endif
 
   _Thread_Heir = thread;
 
 #if defined( PREVENT_SMP_ASSERT_FAILURES )
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 #endif
 }
 
@@ -128,13 +128,13 @@ static void set_thread_executing( Thread_Control *thread )
 #if defined( PREVENT_SMP_ASSERT_FAILURES )
   ISR_Level level;
 
-  _ISR_Disable_without_giant( level );
+  _ISR_Local_disable( level );
 #endif
 
   _Thread_Executing = thread;
 
 #if defined( PREVENT_SMP_ASSERT_FAILURES )
-  _ISR_Enable_without_giant( level );
+  _ISR_Local_enable( level );
 #endif
 }
 

testsuites/tmtests/tm27/task1.c

@@ -188,7 +188,7 @@ rtems_task Task_1(
    */
 
 #if defined(RTEMS_SMP)
-  _ISR_Disable_without_giant(level);
+  _ISR_Local_disable(level);
 #endif
 
   _Thread_Executing =
@@ -197,7 +197,7 @@ rtems_task Task_1(
   _Thread_Dispatch_necessary = 1;
 
 #if defined(RTEMS_SMP)
-  _ISR_Enable_without_giant(level);
+  _ISR_Local_enable(level);
 #endif
 
   Interrupt_occurred = 0;