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Enable data cache.

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This commit is contained in:
Eric Norum
2009-07-30 15:56:38 +00:00
parent b1b6beb0e3
commit 4ac7e27202
4 changed files with 12 additions and 12 deletions
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5
c/src/lib/libbsp/m68k/uC5282/ChangeLog
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@@ -1,3 +1,8 @@
2009-07-30 Eric Norum <norume@aps.anl.gov>
* include/bsp.h, network/network.c, startup/bspstart.c: Try enabling
the data cache.
2009-07-28 Eric Norum <norume@aps.anl.gov> 2009-07-28 Eric Norum <norume@aps.anl.gov>
PR 1420/bsps PR 1420/bsps

2
c/src/lib/libbsp/m68k/uC5282/include/bsp.h
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@@ -31,7 +31,7 @@ extern "C" {
* Uncomment to use instruction/data cache * Uncomment to use instruction/data cache
* Leave commented to use instruction-only cache * Leave commented to use instruction-only cache
*/ */
/* #define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE */ #define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
/***************************************************************************/ /***************************************************************************/
/** Hardware data structure headers **/ /** Hardware data structure headers **/

8
c/src/lib/libbsp/m68k/uC5282/network/network.c
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@@ -492,13 +492,9 @@ fec_rxDaemon (void *arg)
#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
/* /*
* Invalidate the cache. The cache is so small that it's * Invalidate the cache. The cache is so small that it's
* more efficient to just invalidate the whole thing unless * reasonable to simply invalidate the whole thing.
* the packet is very small.
*/ */
if (len < 128) rtems_cache_invalidate_entire_data();
rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
else
rtems_cache_invalidate_entire_data();
#endif #endif
m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header); m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
eh = mtod(m, struct ether_header *); eh = mtod(m, struct ether_header *);

9
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
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@@ -114,7 +114,7 @@ void _CPU_cache_enable_instruction(void)
rtems_interrupt_disable(level); rtems_interrupt_disable(level);
mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI; mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
m68k_set_cacr(mcf5282_cacr_mode); m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
} }
@@ -148,8 +148,8 @@ void _CPU_cache_enable_data(void)
rtems_interrupt_level level; rtems_interrupt_level level;
rtems_interrupt_disable(level); rtems_interrupt_disable(level);
mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB; mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
m68k_set_cacr(mcf5282_cacr_mode); m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
#endif #endif
} }
@@ -160,8 +160,7 @@ void _CPU_cache_disable_data(void)
rtems_interrupt_level level; rtems_interrupt_level level;
rtems_interrupt_disable(level); rtems_interrupt_disable(level);
rtems_interrupt_disable(level); mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
m68k_set_cacr(mcf5282_cacr_mode); m68k_set_cacr(mcf5282_cacr_mode);
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
#endif #endif