forked from Imagelibrary/rtems
arm_edb7312: added new doxygen
This commit is contained in:
Daniel Ramirez
committed by
Gedare Bloom
Gedare Bloom
parent
3d6e1740ae
commit
49232d0650
@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup arm_edb7312
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* @brief Global BSP definitions.
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*/
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/*
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* Cirrus EP7312 BSP header file
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*
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@@ -24,22 +30,35 @@ extern "C" {
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#define BSP_FEATURE_IRQ_EXTENSION
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/*
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* Define the interrupt mechanism for Time Test 27
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/**
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* @defgroup arm_edb7312 EDB7312 Support
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* @ingroup bsp_arm
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* @brief EDB7312 Support Package
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* @{
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*/
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/**
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* @brief Define the interrupt mechanism for Time Test 27
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*
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* NOTE: Following are not defined and are board independent
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* NOTE: Following are not defined and are board independent
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*
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*/
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struct rtems_bsdnet_ifconfig;
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int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config,
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int attaching);
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/*
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* Network driver configuration
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/**
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* @name Network driver configuration
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* @{
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*/
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#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
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#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
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/** @} */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup edb7312_registers
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* @brief Register declarations.
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*/
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/*
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* Cirrus EP7312 register declarations
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*
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@@ -20,6 +26,13 @@
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#define EP7312_REG_BASE 0x80000000
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/**
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* @defgroup edb7312_registers Register Definitions
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* @ingroup arm_edb7312
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* @brief Cirrus EP7312 Register Definitions
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* @{
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*/
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#define EP7312_PADR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
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#define EP7312_PBDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001))
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#define EP7312_PDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003))
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@@ -89,7 +102,12 @@
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#define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C))
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/* serial port bits */
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/* BITS in UBRLCR1 */
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/**
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* @name BITS in UBRLCR1
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* @{
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*/
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#define EP7312_UART_WRDLEN5 0x00000000
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#define EP7312_UART_WRDLEN6 0x00020000
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#define EP7312_UART_WRDLEN7 0x00040000
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@@ -100,29 +118,60 @@
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#define EP7312_UART_PRTEN 0x00002000
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#define EP7312_UART_BREAK 0x00001000
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/* BITS in INTSR1 */
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/** @} */
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/**
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* @name BITS in INTSR1
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* @{
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*/
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#define EP7312_UART_UTXINT1 0x00002000
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#define EP7312_UART_URXINT1 0x00001000
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/* BITS in UARTTDR1 */
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/** @} */
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/**
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* @name BITS in UARTTDR1
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* @{
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*/
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#define EP7312_UART_FRMERR 0x00000100
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#define EP7312_UART_PARERR 0x00000200
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#define EP7312_UART_OVERR 0x00000400
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/* BITS in system status flag register 1 */
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/** @} */
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/**
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* @name BITS in system status flag register 1
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* @{
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*/
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#define EP7312_UART_UBUSY1 0x00000800
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#define EP7312_UART_URXFE1 0x00400000
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#define EP7312_UART_UTXFF1 0x00800000
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/** @} */
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/* system configuration bits */
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/* BITS in SYSCON1 */
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/**
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* @name BITS in SYSCON1
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* @{
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*/
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#define EP7312_SYSCON1_UART1EN 0x00000100
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#define EP7312_SYSCON1_TC1_PRESCALE 0x00000010
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#define EP7312_SYSCON1_TC1_512KHZ 0x00000020
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#define EP7312_SYSCON1_TC2_PRESCALE 0x00000040
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#define EP7312_SYSCON1_TC2_512KHZ 0x00000080
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/* INTR1 (Interrupt 1) mask/status register bits */
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/** @} */
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/**
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* @name INTR1 (Interrupt 1) mask/status register bits
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* @{
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*/
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#define EP7312_INTR1_EXTFIQ 0x00000001
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#define EP7312_INTR1_BLINT 0x00000002
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#define EP7312_INTR1_WEINT 0x00000004
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@@ -140,14 +189,30 @@
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#define EP7312_INTR1_UMSINT 0x00004000
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#define EP7312_INTR1_SSEOTI 0x00008000
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/* INTR2 (Interrupt 2) mask/status register bits */
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/** @} */
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/**
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* @name INTR2 (Interrupt 2) mask/status register bits
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* @{
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*/
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#define EP7312_INTR2_KBDINT 0x00000001
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#define EP7312_INTR2_SS2RX 0x00000002
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#define EP7312_INTR2_SS2TX 0x00000004
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#define EP7312_INTR2_URXINT2 0x00001000
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#define EP7312_INTR2_UTXINT2 0x00002000
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/* INTR3 (Interrupt 3) mask/status register bits */
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/** @} */
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/**
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* @name INTR3 (Interrupt 3) mask/status register bits
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* @{
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*/
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#define EP7312_INTR2_DAIINT 0x00000001
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/** @} */
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/** @} */
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#endif /* __EP7312_H__ */
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@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup edb7312_interrupt
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* @brief Interrupt definitions.
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*/
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/*
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* Cirrus EP7312 Intererrupt handler
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*
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@@ -23,7 +29,18 @@
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#endif /* __asm__ */
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/* int interrupt status/mask register 1 */
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/**
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* @defgroup edb7312_interrupt Interrupt Support
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* @ingroup arm_edb7312
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* @brief Interrupt Support
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* @{
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*/
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/**
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* @name int interrupt status/mask register 1
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* @{
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*/
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#define BSP_EXTFIQ 0
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#define BSP_BLINT 1
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#define BSP_WEINT 2
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@@ -40,18 +57,36 @@
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#define BSP_URXINT1 13
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#define BSP_UMSINT 14
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#define BSP_SSEOTI 15
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/* int interrupt status/mask register 2 */
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/** @} */
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/**
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* @name int interrupt status/mask register 2
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* @{
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*/
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#define BSP_KBDINT 16
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#define BSP_SS2RX 17
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#define BSP_SS2TX 18
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#define BSP_UTXINT2 19
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#define BSP_URXINT2 20
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/* int interrupt status/mask register 3 */
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/** @} */
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/**
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* @name int interrupt status/mask register 3
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* @{
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*/
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#define BSP_DAIINT 21
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#define BSP_MAX_INT 22
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/** @} */
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#define BSP_INTERRUPT_VECTOR_MIN 0
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#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1)
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/** @} */
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#endif /* __IRQ_H__ */
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