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2011-10-07 Daniel Hellstrom <daniel@gaisler.com>

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PR 1933/cpukit
	* shared/irq_asm.S: From code inspection I have found the following
	issues (most SMP), and some improvements in irq_asm.S. I would need a
	long test with interrupts to verify the interrupt handler better,
	however I can not see that these patches hurt. Please see comment per
	hunk below, One should go through the file to indent delay-slots
	correctly, I have fixed some in the patch areas. An extra space is
	added in front of delay slots to indicate a delay slot.
This commit is contained in:
Joel Sherrill
2011-10-07 14:35:03 +00:00
parent 8f582bc637
commit 47a61aa16f
2 changed files with 17 additions and 15 deletions
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11
c/src/lib/libbsp/sparc/ChangeLog
View File

@@ -1,3 +1,14 @@
2011-10-07 Daniel Hellstrom <daniel@gaisler.com>
PR 1933/cpukit
* shared/irq_asm.S: From code inspection I have found the following
issues (most SMP), and some improvements in irq_asm.S. I would need a
long test with interrupts to verify the interrupt handler better,
however I can not see that these patches hurt. Please see comment per
hunk below, One should go through the file to indent delay-slots
correctly, I have fixed some in the patch areas. An extra space is
added in front of delay slots to indicate a delay slot.
2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com> 2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1801 PR 1801

17
c/src/lib/libbsp/sparc/shared/irq_asm.S
View File

@@ -267,8 +267,6 @@ SYM(_ISR_PER_CPU):
add %l5, %l7, %l5 add %l5, %l7, %l5
#endif #endif
ld [%l5], %l5 /* l5 = pointer to per CPU */ ld [%l5], %l5 /* l5 = pointer to per CPU */
nop
nop
/* /*
* On multi-core system, we need to use SMP safe versions * On multi-core system, we need to use SMP safe versions
@@ -277,9 +275,8 @@ SYM(_ISR_PER_CPU):
* _ISR_SMP_Enter returns the interrupt nest level. If we are * _ISR_SMP_Enter returns the interrupt nest level. If we are
* outermost interrupt, then we need to switch stacks. * outermost interrupt, then we need to switch stacks.
*/ */
mov %sp, %fp
call SYM(_ISR_SMP_Enter), 0 call SYM(_ISR_SMP_Enter), 0
nop ! delay slot mov %sp, %fp ! delay slot
cmp %o0, 0 cmp %o0, 0
#else #else
/* /*
@@ -321,7 +318,7 @@ SYM(_ISR_PER_CPU):
/* /*
* Do we need to switch to the interrupt stack? * Do we need to switch to the interrupt stack?
*/ */
bnz dont_switch_stacks ! No, then do not switch stacks beq,a dont_switch_stacks ! No, then do not switch stacks
ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
dont_switch_stacks: dont_switch_stacks:
@@ -358,6 +355,7 @@ dont_switch_stacks:
nop ! delay slot nop ! delay slot
cmp %o0, 0 cmp %o0, 0
bz simple_return bz simple_return
nop
#else #else
!sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 !sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4
!ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7 !ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
@@ -413,11 +411,9 @@ dont_switch_stacks:
*/ */
ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5 ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5
nop
nop
orcc %l5, %g0, %g0 ! Is thread switch necessary? orcc %l5, %g0, %g0 ! Is thread switch necessary?
bz simple_return ! No, then return bz simple_return ! No, then return
nop
#endif #endif
/* /*
* Invoke interrupt dispatcher. * Invoke interrupt dispatcher.
@@ -479,16 +475,11 @@ isr_dispatch:
nop nop
#endif #endif
ld [%l5], %l5 /* l5 = pointer to per CPU */ ld [%l5], %l5 /* l5 = pointer to per CPU */
nop
nop
#else #else
sethi %hi(_Per_CPU_Information), %l5 sethi %hi(_Per_CPU_Information), %l5
add %l5, %lo(_Per_CPU_Information), %l5 add %l5, %lo(_Per_CPU_Information), %l5
#endif #endif
ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5 ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5
nop
nop
orcc %l5, %g0, %g0 ! Is thread switch necessary? orcc %l5, %g0, %g0 ! Is thread switch necessary?
bz allow_nest_again bz allow_nest_again
nop nop