forked from Imagelibrary/rtems
score: Move ISR level content to single file
This commit is contained in:
Sebastian Huber
@@ -96,65 +96,7 @@ SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
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*/
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void _ISR_Handler_initialization ( void );
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/**
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* @brief Disable interrupts on this core.
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*
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* This routine disables all interrupts so that a critical section
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* of code can be executing without being interrupted.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#define _ISR_Disable_on_this_core( _level ) \
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do { \
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_CPU_ISR_Disable( _level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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/**
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* @brief Enable interrupts on this core.
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*
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* This routine enables interrupts to the previous interrupt mask
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* LEVEL. It is used at the end of a critical section of code to
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* enable interrupts so they can be processed again.
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*
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* @param[in] _level contains the interrupt level mask level
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* previously returned by @ref _ISR_Disable_on_this_core.
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*/
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#define _ISR_Enable_on_this_core( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Enable( _level ); \
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} while (0)
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/**
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* @brief Temporarily enable interrupts on this core.
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*
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* This routine temporarily enables interrupts to the previous
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* interrupt mask level and then disables all interrupts so that
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* the caller can continue into the second part of a critical
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* section.
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*
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* This routine is used to temporarily enable interrupts
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* during a long critical section. It is used in long sections of
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* critical code when a point is reached at which interrupts can
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* be temporarily enabled. Deciding where to flash interrupts
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* in a long critical section is often difficult and the point
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* must be selected with care to ensure that the critical section
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* properly protects itself.
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*
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* @param[in] _level contains the interrupt level mask level
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* previously returned by @ref _ISR_Disable_on_this_core.
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*/
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#define _ISR_Flash_on_this_core( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Flash( _level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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#if defined(RTEMS_SMP)
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#if defined( RTEMS_SMP )
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/**
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* @brief Initialize SMP interrupt critical section support.
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*
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@@ -163,38 +105,6 @@ void _ISR_Handler_initialization ( void );
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*/
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void _ISR_SMP_Initialize(void);
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/**
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* @brief Enter interrupt critical section on SMP system.
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*
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* This method is used to enter an interrupt critical section that
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* is honored across all cores in an SMP system.
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*
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* @retval This method returns the previous interrupt mask level.
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*/
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ISR_Level _ISR_SMP_Disable(void);
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/**
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* @brief Exit interrupt critical section on SMP system.
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*
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* This method is used to exit an interrupt critical section that
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* is honored across all cores in an SMP system.
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*
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* @param[in] level contains the interrupt level mask level
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* previously returned by @ref _ISR_SMP_Disable.
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*/
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void _ISR_SMP_Enable(ISR_Level level);
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/**
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* @brief Temporarily exit interrupt critical section on SMP system.
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*
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* This method is used to temporarily exit an interrupt critical section
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* that is honored across all cores in an SMP system.
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*
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* @param[in] level contains the interrupt level mask level
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* previously returned by @ref _ISR_SMP_Disable.
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*/
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void _ISR_SMP_Flash(ISR_Level level);
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/**
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* @brief Enter SMP interrupt code.
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*
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@@ -214,68 +124,7 @@ int _ISR_SMP_Enter(void);
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*/
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int _ISR_SMP_Exit(void);
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#endif
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/**
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* @brief Enter interrupt disable critical section.
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*
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* This routine enters an interrupt disable critical section. When
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* in an SMP configuration, this involves obtaining a spinlock to ensure
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* that only one core is inside an interrupt disable critical section.
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* When on a single core system, this only involves disabling local
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* CPU interrupts.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#if defined(RTEMS_SMP)
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#define _ISR_Disable( _level ) \
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_level = _ISR_SMP_Disable();
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#else
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#define _ISR_Disable( _level ) \
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_ISR_Disable_on_this_core( _level );
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#endif
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/**
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* @brief Exits interrupt disable critical section.
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*
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* This routine exits an interrupt disable critical section. When
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* in an SMP configuration, this involves releasing a spinlock.
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* When on a single core system, this only involves disabling local
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* CPU interrupts.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#if defined(RTEMS_SMP)
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#define _ISR_Enable( _level ) \
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_ISR_SMP_Enable( _level );
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#else
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#define _ISR_Enable( _level ) \
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_ISR_Enable_on_this_core( _level );
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#endif
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/**
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* @brief Temporarily exit interrupt disable critical section.
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*
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* This routine is used to temporarily enable interrupts
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* during a long critical section. It is used in long sections of
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* critical code when a point is reached at which interrupts can
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* be temporarily enabled. Deciding where to flash interrupts
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* in a long critical section is often difficult and the point
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* must be selected with care to ensure that the critical section
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* properly protects itself.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#if defined(RTEMS_SMP)
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#define _ISR_Flash( _level ) \
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_ISR_SMP_Flash( _level );
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#else
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#define _ISR_Flash( _level ) \
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_ISR_Flash_on_this_core( _level );
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#endif
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#endif /* defined( RTEMS_SMP ) */
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/**
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* @brief Install interrupt handler vector.
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@@ -297,35 +146,6 @@ int _ISR_SMP_Exit(void);
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#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
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_CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
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/**
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* @brief Return current interrupt level.
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*
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* This routine returns the current interrupt level.
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*
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* LM32 Specific Information:
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* XXX document implementation including references if appropriate
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*
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* @retval This method returns the current level.
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*/
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#define _ISR_Get_level() \
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_CPU_ISR_Get_level()
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/**
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* @brief Set current interrupt level.
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*
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* This routine sets the current interrupt level to that specified
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* by @a _new_level. The new interrupt level is effective when the
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* routine exits.
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*
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* @param[in] _new_level contains the desired interrupt level.
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*/
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#define _ISR_Set_level( _new_level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Set_level( _new_level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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/**
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* @brief ISR interrupt dispatcher.
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*
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@@ -19,6 +19,8 @@
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#ifndef _RTEMS_SCORE_ISR_LEVEL_h
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#define _RTEMS_SCORE_ISR_LEVEL_h
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#include <rtems/score/cpu.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@@ -38,6 +40,189 @@ extern "C" {
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*/
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typedef uint32_t ISR_Level;
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/**
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* @brief Disable interrupts on this core.
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*
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* This routine disables all interrupts so that a critical section
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* of code can be executing without being interrupted.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#define _ISR_Disable_on_this_core( _level ) \
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do { \
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_CPU_ISR_Disable( _level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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/**
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* @brief Enable interrupts on this core.
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*
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* This routine enables interrupts to the previous interrupt mask
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* LEVEL. It is used at the end of a critical section of code to
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* enable interrupts so they can be processed again.
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*
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* @param[in] _level contains the interrupt level mask level
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* previously returned by @ref _ISR_Disable_on_this_core.
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*/
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#define _ISR_Enable_on_this_core( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Enable( _level ); \
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} while (0)
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/**
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* @brief Temporarily enable interrupts on this core.
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*
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* This routine temporarily enables interrupts to the previous
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* interrupt mask level and then disables all interrupts so that
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* the caller can continue into the second part of a critical
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* section.
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*
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* This routine is used to temporarily enable interrupts
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* during a long critical section. It is used in long sections of
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* critical code when a point is reached at which interrupts can
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* be temporarily enabled. Deciding where to flash interrupts
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* in a long critical section is often difficult and the point
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* must be selected with care to ensure that the critical section
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* properly protects itself.
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*
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* @param[in] _level contains the interrupt level mask level
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* previously returned by @ref _ISR_Disable_on_this_core.
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*/
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#define _ISR_Flash_on_this_core( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Flash( _level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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#if defined( RTEMS_SMP )
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/**
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* @brief Enter interrupt critical section on SMP system.
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*
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* This method is used to enter an interrupt critical section that
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* is honored across all cores in an SMP system.
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*
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* @retval This method returns the previous interrupt mask level.
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*/
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ISR_Level _ISR_SMP_Disable(void);
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/**
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* @brief Exit interrupt critical section on SMP system.
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*
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* This method is used to exit an interrupt critical section that
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* is honored across all cores in an SMP system.
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*
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* @param[in] level contains the interrupt level mask level
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* previously returned by @ref _ISR_SMP_Disable.
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*/
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void _ISR_SMP_Enable(ISR_Level level);
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/**
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* @brief Temporarily exit interrupt critical section on SMP system.
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*
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* This method is used to temporarily exit an interrupt critical section
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* that is honored across all cores in an SMP system.
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*
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* @param[in] level contains the interrupt level mask level
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* previously returned by @ref _ISR_SMP_Disable.
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*/
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void _ISR_SMP_Flash(ISR_Level level);
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#endif /* defined( RTEMS_SMP ) */
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/**
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* @brief Enter interrupt disable critical section.
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*
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* This routine enters an interrupt disable critical section. When
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* in an SMP configuration, this involves obtaining a spinlock to ensure
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* that only one core is inside an interrupt disable critical section.
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* When on a single core system, this only involves disabling local
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* CPU interrupts.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#if defined( RTEMS_SMP )
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#define _ISR_Disable( _level ) \
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_level = _ISR_SMP_Disable();
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#else
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#define _ISR_Disable( _level ) \
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_ISR_Disable_on_this_core( _level );
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#endif
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/**
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* @brief Exits interrupt disable critical section.
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*
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* This routine exits an interrupt disable critical section. When
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* in an SMP configuration, this involves releasing a spinlock.
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* When on a single core system, this only involves disabling local
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* CPU interrupts.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#if defined( RTEMS_SMP )
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#define _ISR_Enable( _level ) \
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_ISR_SMP_Enable( _level );
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#else
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#define _ISR_Enable( _level ) \
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_ISR_Enable_on_this_core( _level );
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#endif
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/**
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* @brief Temporarily exit interrupt disable critical section.
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*
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* This routine is used to temporarily enable interrupts
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* during a long critical section. It is used in long sections of
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* critical code when a point is reached at which interrupts can
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* be temporarily enabled. Deciding where to flash interrupts
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* in a long critical section is often difficult and the point
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* must be selected with care to ensure that the critical section
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* properly protects itself.
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*
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* @retval The argument @a _level will contain the previous interrupt
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* mask level.
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*/
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#if defined( RTEMS_SMP )
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#define _ISR_Flash( _level ) \
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_ISR_SMP_Flash( _level );
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#else
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#define _ISR_Flash( _level ) \
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_ISR_Flash_on_this_core( _level );
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#endif
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/**
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* @brief Return current interrupt level.
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*
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* This routine returns the current interrupt level.
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*
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* LM32 Specific Information:
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* XXX document implementation including references if appropriate
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*
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* @retval This method returns the current level.
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*/
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#define _ISR_Get_level() \
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_CPU_ISR_Get_level()
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/**
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* @brief Set current interrupt level.
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*
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* This routine sets the current interrupt level to that specified
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* by @a _new_level. The new interrupt level is effective when the
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* routine exits.
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*
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* @param[in] _new_level contains the desired interrupt level.
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*/
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#define _ISR_Set_level( _new_level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Set_level( _new_level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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/**@}*/
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#ifdef __cplusplus
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@@ -25,7 +25,7 @@
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#if defined( RTEMS_SMP )
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#include <rtems/score/cpusmplock.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/isrlevel.h>
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#ifdef __cplusplus
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extern "C" {
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