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score: Doxygen Clean Up Task #9

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This commit is contained in:
Alex Ivanov
2013-01-04 08:49:56 -06:00
committed by Jennifer Averett
parent 2305f97117
commit 455bd4eae2
20 changed files with 1746 additions and 974 deletions
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23
cpukit/score/cpu/avr/avr/io2333.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/**
* @name I/O Registers
*
* @{
*/
/* UART Baud Rate Register high */
#define UBRRH _SFR_IO8(0x03)
@@ -171,9 +174,13 @@
/* General Interrupt MaSK register */
#define GIMSK _SFR_IO8(0x3B)
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* External Interrupt 0 */
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
@@ -227,6 +234,7 @@
#define SIG_COMPARATOR _VECTOR(13)
#define _VECTORS_SIZE 28
/** @} */
/*
The Register Bit names are represented by their bit number (0-7).
@@ -434,10 +442,15 @@
#define EEWE 1
#define EERE 0
/* Constants */
/**
* @name Constants
*
* @{
*/
#define RAMEND 0xDF /*Last On-Chip SRAM location*/
#define XRAMEND RAMEND
#define E2END 0x7F
#define FLASHEND 0x7FF
/** @} */
#endif /* _AVR_IO2333_H_ */

27
cpukit/score/cpu/avr/avr/io43u35x.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/**
* @name I/O Registers
*
* @{
*/
/* ADC Data Register */
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16(0x02)
@@ -179,9 +182,13 @@
/* General Interrupt Mask register */
#define GIMSK _SFR_IO8(0x3B)
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */
#define SIG_INTERRUPT1 _VECTOR(2)
#define SIG_TIMER1_CAPT1 _VECTOR(3)
@@ -196,10 +203,11 @@
#define SIG_USB_INT _VECTOR(12)
#define _VECTORS_SIZE 52
/** @} */
/*
The Register Bit names are represented by their bit number (0-7).
*/
* The Register Bit names are represented by their bit number (0-7).
*/
/* Timer/Counter Interrupt MaSK register */
#define TICIE1 3
@@ -418,10 +426,15 @@
#define ADPS1 1
#define ADPS0 0
/* Constants */
/**
* @name Constants
*
* @{
*/
#define RAMEND 0x045F /*Last On-Chip SRAM Location*/
#define XRAMEND RAMEND
#define E2END 0x0000
#define FLASHEND 0x5FFF
/** @} */
#endif /* _AVR_43USB355_H_ */

74
cpukit/score/cpu/avr/avr/iom16a.h
View File

@@ -47,9 +47,11 @@
#ifndef _AVR_ATmega16A_H_
#define _AVR_ATmega16A_H_ 1
/* Registers and associated bit numbers. */
/**
* @name Registers and Associated Bit Numbers
*
* @{
*/
#define TWBR _SFR_IO8(0x00)
#define TWBR0 0
#define TWBR1 1
@@ -654,8 +656,13 @@
#define OCR0_6 6
#define OCR0_7 7
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Vector 0 is the reset vector */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
@@ -668,9 +675,11 @@
#define TIMER1_CAPT_vect_num 5
#define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect_num 6
#define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(6)
#define TIMER1_COMPB_vect_num 7
#define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(7)
#define TIMER1_OVF_vect_num 8
#define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */
#define TIMER0_OVF_vect_num 9
@@ -700,9 +709,13 @@
#define _VECTOR_SIZE 4 /* Size of individual vector. */
#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
/** @} */
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE (128)
#define RAMSTART (0x60)
#define RAMSIZE (1024)
@@ -713,9 +726,13 @@
#define E2END (0x1FF)
#define E2PAGESIZE (4)
#define FLASHEND (0x3FFF)
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
@@ -726,34 +743,50 @@
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */
#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */
#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
/* Brown out detector trigger level */
#define FUSE_BODLEVEL (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
FUSE_CKSEL2 & FUSE_CKSEL1)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
/* EEPROM memory is preserved through chip erase */
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
/* Enable Serial programming and Data Downloading */
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x03
/** @} */
/* Device Pin Definitions */
/**
* @name Device Pin Definitions
*
* @{
*/
#define MOSI_DDR DDRB
#define MOSI_PORT PORTB
#define MOSI_PIN PINB
@@ -898,6 +931,7 @@
#define SS_PORT PORTB
#define SS_PIN PINB
#define SS_BIT 4
/** @} */
#endif /* _AVR_ATmega16A_H_ */

36
cpukit/score/cpu/avr/avr/iom2560.h
View File

@@ -36,17 +36,24 @@
#include <avr/iomxx0_1.h>
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 256
#define RAMEND 0x21FF
#define XRAMEND 0xFFFF
#define E2END 0xFFF
#define E2PAGESIZE 8
#define FLASHEND 0x3FFFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -58,7 +65,8 @@
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
@@ -76,18 +84,26 @@
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x98
#define SIGNATURE_2 0x01
/** @} */
#endif /* _AVR_IOM2560_H_ */

68
cpukit/score/cpu/avr/avr/iom3250.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
/**
* @name Registers and Associated Bit Numbers
*
* @{
*/
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
@@ -295,12 +298,15 @@
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0X22)
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
subroutines.
First two letters: EECR address.
Second two letters: EEDR address.
Last two letters: EEAR address. */
/*
* 6-char sequence denoting where to find the EEPROM registers in
* memory space.
* Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
* subroutines.
* First two letters: EECR address.
* Second two letters: EEDR address.
* Last two letters: EEAR address.
*/
#define __EEPROM_REG_LOCATIONS__ 1F2021
#define GTCCR _SFR_IO8(0x23)
@@ -751,9 +757,13 @@
#define PJ0 0
/* Reserved [0xDE..0xFF] */
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
@@ -851,19 +861,26 @@
#define SIG_PIN_CHANGE3 _VECTOR(24)
#define _VECTORS_SIZE 100
/** @} */
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 128
#define RAMEND 0x8FF
#define XRAMEND RAMEND
#define E2END 0x3FF
#define E2PAGESIZE 4
#define FLASHEND 0x7FFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -875,7 +892,8 @@
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
@@ -893,18 +911,26 @@
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x95
#define SIGNATURE_2 0x06
/** @} */
#endif /* _AVR_IOM3250_H_ */

70
cpukit/score/cpu/avr/avr/iom329.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* Registers and associated bit numbers */
/**
* @name Registers and Associated Bit Numbers
*
* @{
*/
#define PINA _SFR_IO8(0x00)
#define PINA7 7
#define PINA6 6
@@ -291,12 +294,15 @@
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0X22)
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
subroutines.
First two letters: EECR address.
Second two letters: EEDR address.
Last two letters: EEAR address. */
/*
* 6-char sequence denoting where to find the EEPROM registers in
* memory space.
* Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
* subroutines.
* First two letters: EECR address.
* Second two letters: EEDR address.
* Last two letters: EEAR address.
*/
#define __EEPROM_REG_LOCATIONS__ 1F2021
#define GTCCR _SFR_IO8(0x23)
@@ -852,8 +858,13 @@
#define SEG324 0
/* Reserved [0xFF] */
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Vector 0 is the reset vector */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
@@ -944,19 +955,26 @@
#define SIG_LCD _VECTOR(22)
#define _VECTORS_SIZE 92
/** @} */
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 128
#define RAMEND 0x8FF
#define XRAMEND RAMEND
#define E2END 0x3FF
#define E2PAGESIZE 4
#define FLASHEND 0x7FFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -968,7 +986,8 @@
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
@@ -979,25 +998,34 @@
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_JTAGEN (unsigned char)~_BV(6)
#define FUSE_OCDEN (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & \
FUSE_SPIEN & FUSE_JTAGEN)
/* Extended Fuse Byte */
#define FUSE_RSTDISBL (unsigned char)~_BV(0)
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x95
#define SIGNATURE_2 0x03
/** @} */
#endif /* _AVR_IOM329_H_ */

80
cpukit/score/cpu/avr/avr/iom32u2.h
View File

@@ -47,9 +47,11 @@
#ifndef _AVR_ATmega32U2_H_
#define _AVR_ATmega32U2_H_ 1
/* Registers and associated bit numbers. */
/**
* @name Registers and Associated Bit Numbers
*
* @{
*/
#define PINB _SFR_IO8(0x03)
#define PINB0 0
#define PINB1 1
@@ -851,9 +853,13 @@
#define UPDRV1 5
#define UPWE0 6
#define UPWE1 7
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Vector 0 is the reset vector */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
@@ -878,17 +884,21 @@
#define USB_GEN_vect_num 11
#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */
#define USB_COM_vect_num 12
#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */
/* USB Endpoint/Pipe Interrupt Communication Request */
#define USB_COM_vect _VECTOR(12)
#define WDT_vect_num 13
#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */
#define TIMER1_CAPT_vect_num 14
#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */
#define TIMER1_COMPA_vect_num 15
#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */
/* Timer/Counter2 Compare Match B */
#define TIMER1_COMPA_vect _VECTOR(15)
#define TIMER0_COMPA_vect_num 19
#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */
/* Timer/Counter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(19)
#define TIMER0_COMPB_vect_num 20
#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */
/* Timer/Counter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(20)
#define TIMER0_OVF_vect_num 21
#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */
#define SPI_STC_vect_num 22
@@ -906,15 +916,17 @@
#define SPM_READY_vect_num 28
#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */
#define TIMER1_COMPB_vect_num 16
#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */
/* Timer/Counter2 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(16)
#define TIMER1_COMPC_vect_num 17
#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */
/* Timer/Counter2 Compare Match C */
#define TIMER1_COMPC_vect _VECTOR(17)
#define TIMER1_OVF_vect_num 18
#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */
#define _VECTOR_SIZE 4 /* Size of individual vector. */
#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
/** @} */
/* Constants */
#define SPM_PAGESIZE (128)
@@ -927,9 +939,13 @@
#define E2END (0x3FF)
#define E2PAGESIZE (4)
#define FLASHEND (0x7FFF)
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -941,38 +957,52 @@
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
FUSE_CKSEL2 & FUSE_CKSEL1)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
/* EEPROM memory is preserved through chip erase */
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
/* Enable Serial programming and Data Downloading */
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */
#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */
#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
/* Brown-out Detector trigger level */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
/* Brown-out Detector trigger level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
/* Brown-out Detector trigger level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */
#define EFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x95
#define SIGNATURE_2 0x8A
/** @} */
/* Device Pin Definitions */
#endif /* _AVR_ATmega32U2_H_ */

36
cpukit/score/cpu/avr/avr/iom644p.h
View File

@@ -36,17 +36,24 @@
#include <avr/iomxx4.h>
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 256
#define RAMEND 0x10FF
#define XRAMEND RAMEND
#define E2END 0x7FF
#define E2PAGESIZE 8
#define FLASHEND 0xFFFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -58,7 +65,8 @@
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
@@ -76,18 +84,26 @@
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x96
#define SIGNATURE_2 0x0A
/** @} */
#endif /* _AVR_IOM644P_H_ */

79
cpukit/score/cpu/avr/avr/iom64m1.h
View File

@@ -48,8 +48,11 @@
#define _AVR_ATmega64M1_H_ 1
/* Registers and associated bit numbers. */
/**
* @name Registers and Associated Bit Numbers
*
* @{
*/
#define PINB _SFR_IO8(0x03)
#define PINB0 0
#define PINB1 1
@@ -1415,9 +1418,13 @@
#define MSG5 5
#define MSG6 6
#define MSG7 7
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Vector 0 is the reset vector */
#define ANACOMP0_vect_num 1
#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */
@@ -1442,15 +1449,19 @@
#define TIMER1_CAPT_vect_num 11
#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect_num 12
#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(12)
#define TIMER1_COMPB_vect_num 13
#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */
/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(13)
#define TIMER1_OVF_vect_num 14
#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */
#define TIMER0_COMPA_vect_num 15
#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */
/* Timer/Counter0 Compare Match A */
#define TIMER0_COMPA_vect _VECTOR(15)
#define TIMER0_COMPB_vect_num 16
#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */
/* Timer/Counter0 Compare Match B */
#define TIMER0_COMPB_vect _VECTOR(16)
#define TIMER0_OVF_vect_num 17
#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */
#define CAN_INT_vect_num 18
@@ -1482,9 +1493,13 @@
#define _VECTOR_SIZE 4 /* Size of individual vector. */
#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
/** @} */
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE (256)
#define RAMSTART (0x0100)
#define RAMSIZE (4096)
@@ -1495,9 +1510,13 @@
#define E2END (0x7FF)
#define E2PAGESIZE (8)
#define FLASHEND (0xFFFF)
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -1509,40 +1528,54 @@
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */
#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & \
FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
/* EEPROM memory is preserved through chip erase */
#define FUSE_EESAVE (unsigned char)~_BV(3)
#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
/* Enable Serial programming and Data Downloading */
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */
#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
/* Extended Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */
/* Brown-out Detector Trigger Level */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
/* Brown-out Detector Trigger Level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
/* Brown-out Detector Trigger Level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */
#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */
#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */
#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x96
#define SIGNATURE_2 0x84
/** @} */
#endif /* _AVR_ATmega64M1_H_ */

65
cpukit/score/cpu/avr/avr/iom8535.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/**
* @name I/O Registers
*
* @{
*/
/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
#define TWBR _SFR_IO8(0x00)
#define TWSR _SFR_IO8(0x01)
@@ -227,9 +230,13 @@
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* External Interrupt 0 */
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
@@ -311,10 +318,10 @@
#define SIG_SPM_READY _VECTOR(20)
#define _VECTORS_SIZE 42
/** @} */
/*
The Register Bit names are represented by their bit number (0-7).
*/
* The Register Bit names are represented by their bit number (0-7).
*/
/* General Interrupt Control Register */
#define INT1 7
@@ -394,10 +401,10 @@
#define CS00 0
/*
The ADHSM bit has been removed from all documentation,
as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
* The ADHSM bit has been removed from all documentation,
* as being not needed at all since the comparator has proven
* to be fast enough even without feeding it more power.
*/
/* Special Function IO Register */
#define ADTS2 7
@@ -663,17 +670,24 @@
#define EEWE 1
#define EERE 0
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 64
#define RAMEND 0x25F /* Last On-Chip SRAM Location */
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x1FFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
@@ -685,7 +699,8 @@
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_BODEN (unsigned char)~_BV(6)
#define FUSE_BODLEVEL (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1)
#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
FUSE_SUT0 & FUSE_SUT1)
/* High Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
@@ -697,18 +712,26 @@
#define FUSE_WDTON (unsigned char)~_BV(6)
#define FUSE_S8535C (unsigned char)~_BV(7)
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x08
/** @} */
#endif /* _AVR_IOM8535_H_ */

47
cpukit/score/cpu/avr/avr/iomx8.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/**
* @name I/O Registers
*
* @{
*/
/* Port B */
#define PINB _SFR_IO8 (0x03)
@@ -203,16 +206,19 @@
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0X22)
/*
Even though EEARH is not used by the mega48, the EEAR8 bit in the register
must be written to 0, according to the datasheet, hence the EEARH register
must be defined for the mega48.
*/
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
subroutines.
First two letters: EECR address.
Second two letters: EEDR address.
Last two letters: EEAR address. */
* Even though EEARH is not used by the mega48, the EEAR8 bit in the register
* must be written to 0, according to the datasheet, hence the EEARH register
* must be defined for the mega48.
*/
/*
* 6-char sequence denoting where to find the EEPROM registers in
* memory space.
* Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
* subroutines.
* First two letters: EECR address.
* Second two letters: EEDR address.
* Last two letters: EEAR address.
*/
#define __EEPROM_REG_LOCATIONS__ 1F2021
@@ -617,9 +623,13 @@ must be defined for the mega48.
#define UBRR0L _SFR_MEM8 (0xC4)
#define UBRR0H _SFR_MEM8 (0xC5)
#define UDR0 _SFR_MEM8 (0xC6)
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
@@ -721,14 +731,17 @@ must be defined for the mega48.
#define SPM_READY_vect _VECTOR(25)
#define SIG_SPM_READY _VECTOR(25)
/* The mega48 and mega88 vector tables are single instruction entries (16 bits
per entry for an RJMP) while the mega168 table has double instruction
entries (32 bits per entry for a JMP). */
/*
* The mega48 and mega88 vector tables are single instruction entries (16 bits
* per entry for an RJMP) while the mega168 table has double instruction
* entries (32 bits per entry for a JMP).
*/
#if defined (__AVR_ATmega168__)
# define _VECTORS_SIZE 104
#else
# define _VECTORS_SIZE 52
#endif
/** @} */
#endif /* _AVR_IOM8_H_ */

62
cpukit/score/cpu/avr/avr/iotn13a.h
View File

@@ -47,9 +47,11 @@
#ifndef _AVR_ATTINY13A_H_
#define _AVR_ATTINY13A_H_ 1
/* Registers and associated bit numbers. */
/**
* @name Registers and Associated Bit Numbers
*
* @{
*/
#define ADCSRB _SFR_IO8(0x03)
#define ADTS0 0
#define ADTS1 1
@@ -306,9 +308,13 @@
#define GIMSK _SFR_IO8(0x3B)
#define PCIE 5
#define INT0 6
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Vector 0 is the reset vector */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
@@ -331,9 +337,13 @@
#define _VECTOR_SIZE 2 /* Size of individual vector. */
#define _VECTORS_SIZE (10 * _VECTOR_SIZE)
/** @} */
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE (32)
#define RAMSTART (0x60)
#define RAMSIZE (64)
@@ -344,9 +354,13 @@
#define E2END (64 - 1)
#define E2PAGESIZE (4)
#define FLASHEND (1024 - 1)
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
@@ -354,30 +368,42 @@
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */
#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */
#define FUSE_CKDIV8 (unsigned char)~_BV(4) /* Start up with system clock divided by 8 */
/* Start up with system clock divided by 8 */
#define FUSE_CKDIV8 (unsigned char)~_BV(4)
#define FUSE_WDTON (unsigned char)~_BV(5) /* Watch dog timer always on */
#define FUSE_EESAVE (unsigned char)~_BV(6) /* Keep EEprom contents during chip erase */
/* Keep EEprom contents during chip erase */
#define FUSE_EESAVE (unsigned char)~_BV(6)
#define FUSE_SPIEN (unsigned char)~_BV(7) /* SPI programming enable */
#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0)
/* High Fuse Byte */
#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Enable BOD and select level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Enable BOD and select level */
/* Enable BOD and select level */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
/* Enable BOD and select level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
#define FUSE_DWEN (unsigned char)~_BV(3) /* DebugWire Enable */
#define FUSE_SELFPRGEN (unsigned char)~_BV(4) /* Self Programming Enable */
#define HFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x90
#define SIGNATURE_2 0x07
/** @} */
#endif /* _AVR_ATTINY13A_H_ */

35
cpukit/score/cpu/avr/avr/iotn861.h
View File

@@ -36,16 +36,24 @@
#include <avr/iotnx61.h>
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 64
#define RAMEND 0x25F
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x1FFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -57,7 +65,8 @@
#define FUSE_SUT1 (unsigned char)~_BV(5)
#define FUSE_CKOUT (unsigned char)~_BV(6)
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
@@ -73,16 +82,24 @@
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
#define EFUSE_DEFAULT (0xFF)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x93
#define SIGNATURE_2 0x0D
/** @} */
#endif /* _AVR_IOTN861_H_ */

17
cpukit/score/cpu/avr/avr/iotnx4.h
View File

@@ -46,8 +46,11 @@
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers */
/**
* @name I/O Registers
*
* @{
*/
#define PRR _SFR_IO8 (0x00)
#define PRTIM1 3
#define PRTIM0 2
@@ -378,9 +381,13 @@
/* 0x3D..0x3E SP [defined in <avr/io.h>] */
/* 0x3F SREG [defined in <avr/io.h>] */
///---
/** @} */
/* Interrupt vectors */
/**
* @name Interrupt Vectors
*
* @{
*/
/* Interrupt vector 0 is the reset vector. */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
@@ -452,4 +459,6 @@
#define _VECTORS_SIZE 34
/** @} */
#endif /* _AVR_IOTNX4_H_ */

32
cpukit/score/cpu/avr/avr/iousb162.h
View File

@@ -36,16 +36,24 @@
#include <avr/iousbxx2.h>
/* Constants */
/**
* @name Constants
*
* @{
*/
#define SPM_PAGESIZE 128
#define RAMEND 0x2FF
#define XRAMEND RAMEND
#define E2END 0x1FF
#define E2PAGESIZE 4
#define FLASHEND 0x3FFF
/** @} */
/* Fuses */
/**
* @name Fuses
*
* @{
*/
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
@@ -76,18 +84,26 @@
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
#define FUSE_HWBE (unsigned char)~_BV(3)
#define EFUSE_DEFAULT (BODLEVEL0 & BODLEVEL1 & HWBE)
/** @} */
/* Lock Bits */
/**
* @name Lock Bits
*
* @{
*/
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/** @} */
/* Signature */
/**
* @name Signature
*
* @{
*/
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x94
#define SIGNATURE_2 0x82
/** @} */
#endif /* _AVR_AT90USB162_H_ */

1354
cpukit/score/cpu/avr/avr/iox128a1.h
View File

File diff suppressed because it is too large Load Diff

12
cpukit/score/cpu/avr/avr/portpins.h
View File

@@ -1,3 +1,9 @@
/**
* @file
*
* @brief Define Generic PORTn, DDn, and PINn Values
*/
/* Copyright (c) 2003 Theodore A. Roth
All rights reserved.
@@ -38,8 +44,6 @@
# error "Include <avr/io.h> instead of this file."
#endif
/* Define Generic PORTn, DDn, and PINn values. */
/* Port Data Register (generic) */
#define PORT7 7
#define PORT6 6
@@ -70,7 +74,9 @@
#define PIN1 1
#define PIN0 0
/* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */
/* Define PORTxn an Pxn values for all possible port pins
* if not defined already by io.h.
*/
/* PORT A */

73
cpukit/score/cpu/avr/avr/signature.h
View File

@@ -1,3 +1,9 @@
/**
* @file
*
* @brief Signature Support
*/
/* Copyright (c) 2009, Atmel Corporation
All rights reserved.
@@ -34,38 +40,38 @@
#ifndef _AVR_SIGNATURE_H_
#define _AVR_SIGNATURE_H_ 1
/** \file */
/** \defgroup avr_signature <avr/signature.h>: Signature Support
\par Introduction
The <avr/signature.h> header file allows the user to automatically
and easily include the device's signature data in a special section of
the final linked ELF file.
This value can then be used by programming software to compare the on-device
signature with the signature recorded in the ELF file to look for a match
before programming the device.
\par API Usage Example
Usage is very simple; just include the header file:
\code
#include <avr/signature.h>
\endcode
This will declare a constant unsigned char array and it is initialized with
the three signature bytes, MSB first, that are defined in the device I/O
header file. This array is then placed in the .signature section in the
resulting linked ELF file.
The three signature bytes that are used to initialize the array are
these defined macros in the device I/O header file, from MSB to LSB:
SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
This header file should only be included once in an application.
*/
/**
* @defgroup avr_signature Signature Support
*
* @par Introduction
*
* The <avr/signature.h> header file allows the user to automatically
* and easily include the device's signature data in a special section of
* the final linked ELF file.
*
* This value can then be used by programming software to compare the
* on-device signature with the signature recorded in the ELF file
* to look for a match before programming the device.
*
* @par API Usage Example
*
* Usage is very simple; just include the header file:
*
* @code{.c}
* #include <avr/signature.h>
* @endcode
*
* This will declare a constant unsigned char array and it is initialized with
* the three signature bytes, MSB first, that are defined in the device I/O
* header file. This array is then placed in the .signature section in the
* resulting linked ELF file.
*
* The three signature bytes that are used to initialize the array are
* these defined macros in the device I/O header file, from MSB to LSB:
* SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
*
* This header file should only be included once in an application.
*/
#ifndef __ASSEMBLER__
@@ -76,7 +82,8 @@
const unsigned char __signature[3] __attribute__((section (".signature"))) =
{ SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 };
#endif /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
/* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
#endif
#endif /* __ASSEMBLER__ */

280
cpukit/score/cpu/avr/avr/sleep.h
View File

@@ -1,3 +1,10 @@
/**
* @file
*
* @brief Power Management and Sleep Modes
*
*/
/* Copyright (c) 2002, 2004 Theodore A. Roth
Copyright (c) 2004, 2007, 2008 Eric B. Weddington
Copyright (c) 2005, 2006, 2007 Joerg Wunsch
@@ -37,103 +44,104 @@
#include <avr/io.h>
#include <stdint.h>
/** \file */
/** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
\code #include <avr/sleep.h>\endcode
Use of the \c SLEEP instruction can allow an application to reduce its
power comsumption considerably. AVR devices can be put into different
sleep modes. Refer to the datasheet for the details relating to the device
you are using.
There are several macros provided in this header file to actually
put the device into sleep mode. The simplest way is to optionally
set the desired sleep mode using \c set_sleep_mode() (it usually
defaults to idle mode where the CPU is put on sleep but all
peripheral clocks are still running), and then call
\c sleep_mode(). This macro automatically sets the sleep enable bit, goes
to sleep, and clears the sleep enable bit.
Example:
\code
#include <avr/sleep.h>
...
set_sleep_mode(<mode>);
sleep_mode();
\endcode
Note that unless your purpose is to completely lock the CPU (until a
hardware reset), interrupts need to be enabled before going to sleep.
As the \c sleep_mode() macro might cause race conditions in some
situations, the individual steps of manipulating the sleep enable
(SE) bit, and actually issuing the \c SLEEP instruction, are provided
in the macros \c sleep_enable(), \c sleep_disable(), and
\c sleep_cpu(). This also allows for test-and-sleep scenarios that
take care of not missing the interrupt that will awake the device
from sleep.
Example:
\code
#include <avr/interrupt.h>
#include <avr/sleep.h>
...
set_sleep_mode(<mode>);
cli();
if (some_condition)
{
sleep_enable();
sei();
sleep_cpu();
sleep_disable();
}
sei();
\endcode
This sequence ensures an atomic test of \c some_condition with
interrupts being disabled. If the condition is met, sleep mode
will be prepared, and the \c SLEEP instruction will be scheduled
immediately after an \c SEI instruction. As the intruction right
after the \c SEI is guaranteed to be executed before an interrupt
could trigger, it is sure the device will really be put to sleep.
Some devices have the ability to disable the Brown Out Detector (BOD) before
going to sleep. This will also reduce power while sleeping. If the
specific AVR device has this ability then an additional macro is defined:
\c sleep_bod_disable(). This macro generates inlined assembly code
that will correctly implement the timed sequence for disabling the BOD
before sleeping. However, there is a limited number of cycles after the
BOD has been disabled that the device can be put into sleep mode, otherwise
the BOD will not truly be disabled. Recommended practice is to disable
the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
put the device to sleep (\c sleep_cpu()), like so:
\code
#include <avr/interrupt.h>
#include <avr/sleep.h>
...
set_sleep_mode(<mode>);
cli();
if (some_condition)
{
sleep_enable();
sleep_bod_disable();
sei();
sleep_cpu();
sleep_disable();
}
sei();
\endcode
*/
/**
* @defgroup avr_sleep Power Management and Sleep Modes
*
* Use of the @c SLEEP instruction can allow an application to reduce its
* power comsumption considerably. AVR devices can be put into different
* sleep modes. Refer to the datasheet for the details relating to the device
* you are using.
*
* There are several macros provided in this header file to actually
* put the device into sleep mode. The simplest way is to optionally
* set the desired sleep mode using @c set_sleep_mode() (it usually
* defaults to idle mode where the CPU is put on sleep but all
* peripheral clocks are still running), and then call
* @c sleep_mode(). This macro automatically sets the sleep enable bit, goes
* to sleep, and clears the sleep enable bit.
*
* Example:
* @code{.c}
* #include <avr/sleep.h>
*
* ...
* set_sleep_mode(<mode>);
* sleep_mode();
* @endcode
*
* Note that unless your purpose is to completely lock the CPU (until a
* hardware reset), interrupts need to be enabled before going to sleep.
*
* As the @c sleep_mode() macro might cause race conditions in some
* situations, the individual steps of manipulating the sleep enable
* (SE) bit, and actually issuing the @c SLEEP instruction, are provided
* in the macros @c sleep_enable(), @c sleep_disable(), and
* @c sleep_cpu(). This also allows for test-and-sleep scenarios that
* take care of not missing the interrupt that will awake the device
* from sleep.
*
* Example:
* @code{.c}
* #include <avr/interrupt.h>
* #include <avr/sleep.h>*
*
* ...
* set_sleep_mode(<mode>);
* cli();
* if (some_condition)
* {
* sleep_enable();
* sei();
* sleep_cpu();
* sleep_disable();
* }
* sei();
* @endcode
*
* This sequence ensures an atomic test of @c some_condition with
* interrupts being disabled. If the condition is met, sleep mode
* will be prepared, and the @c SLEEP instruction will be scheduled
* immediately after an @c SEI instruction. As the intruction right
* after the @c SEI is guaranteed to be executed before an interrupt
* could trigger, it is sure the device will really be put to sleep.
*
* Some devices have the ability to disable the Brown Out Detector (BOD)
* before going to sleep. This will also reduce power while sleeping. If the
* specific AVR device has this ability then an additional macro is defined:
* @c sleep_bod_disable(). This macro generates inlined assembly code
* that will correctly implement the timed sequence for disabling the BOD
* before sleeping. However, there is a limited number of cycles after the
* BOD has been disabled that the device can be put into sleep mode, otherwise
* the BOD will not truly be disabled. Recommended practice is to disable
* the BOD (@c sleep_bod_disable()), set the interrupts (@c sei()), and then
* put the device to sleep (@c sleep_cpu()), like so:
*
* @code{.c}
* #include <avr/interrupt.h>
* #include <avr/sleep.h>*
*
* ...
* set_sleep_mode(<mode>);
* cli();
* if (some_condition)
* {
* sleep_enable();
* sleep_bod_disable();
* sei();
* sleep_cpu();
* sleep_disable();
* }
* sei();
* @endcode
*
* @{
*/
/* Define an internal sleep control register and an internal sleep enable bit mask. */
/*
* Define an internal sleep control register and
* an internal sleep enable bit mask.
*/
#if defined(SLEEP_CTRL)
/* XMEGA devices */
@@ -167,8 +175,11 @@
#define set_sleep_mode(mode) \
do { \
MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
MCUCR = ((MCUCR & ~_BV(SM1)) | \
((mode) == SLEEP_MODE_PWR_DOWN || \
(mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
EMCUCR = ((EMCUCR & ~_BV(SM0)) | \
((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
} while(0)
@@ -184,9 +195,12 @@
#define set_sleep_mode(mode) \
do { \
MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
MCUCR = ((MCUCR & ~_BV(SM1)) | \
((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || \
(mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || \
(mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
} while(0)
#elif defined(__AVR_AT90S2313__) \
@@ -217,7 +231,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1))) | (mode)); \
} while(0)
#elif defined(__AVR_AT90S4434__) \
@@ -253,7 +268,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1))) | (mode)); \
} while(0)
#elif defined(__AVR_ATtiny2313__) \
@@ -266,7 +282,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1))) | (mode)); \
} while(0)
#elif defined(__AVR_AT94K__)
@@ -277,7 +294,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1))) | (mode)); \
} while(0)
#elif defined(__AVR_ATtiny26__) \
@@ -290,7 +308,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1))) | (mode)); \
} while(0)
#elif defined(__AVR_AT90PWM216__) \
@@ -304,7 +323,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
} while(0)
#elif defined(__AVR_AT90CAN128__) \
@@ -415,7 +435,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
} while(0)
#elif defined(__AVR_ATxmega16A4__) \
@@ -438,11 +459,13 @@
#define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
#define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
#define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
#define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
#define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | \
SLEEP_SMODE0_bm)
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
} while(0)
#elif defined(__AVR_AT90SCR100__)
@@ -455,7 +478,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
} while(0)
#elif defined(__AVR_ATA6289__)
@@ -466,7 +490,8 @@
#define set_sleep_mode(mode) \
do { \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
} while(0)
#else
@@ -477,18 +502,17 @@
/** \ingroup avr_sleep
Put the device in sleep mode. How the device is brought out of sleep mode
depends on the specific mode selected with the set_sleep_mode() function.
See the data sheet for your device for more details. */
/**
* Put the device in sleep mode. How the device is brought out of sleep mode
* depends on the specific mode selected with the set_sleep_mode() function.
* See the data sheet for your device for more details.
*/
#if defined(__DOXYGEN__)
/** \ingroup avr_sleep
Set the SE (sleep enable) bit.
/**
* Set the SE (sleep enable) bit.
*/
extern void sleep_enable (void);
@@ -504,10 +528,9 @@ do { \
#if defined(__DOXYGEN__)
/** \ingroup avr_sleep
Clear the SE (sleep enable) bit.
*/
/**
* Clear the SE (sleep enable) bit.
*/
extern void sleep_disable (void);
#else
@@ -520,11 +543,10 @@ do { \
#endif
/** \ingroup avr_sleep
Put the device into sleep mode. The SE bit must be set
beforehand, and it is recommended to clear it afterwards.
*/
/**
* Put the device into sleep mode. The SE bit must be set
* beforehand, and it is recommended to clear it afterwards.
*/
#if defined(__DOXYGEN__)
extern void sleep_cpu (void);
@@ -582,6 +604,6 @@ do { \
#endif
/*@}*/
/** @} */
#endif /* _AVR_SLEEP_H_ */

248
cpukit/score/cpu/avr/avr/wdt.h
View File

@@ -1,3 +1,8 @@
/**
* @file
*
* @brief Watchdog Timer Handling
*/
/* Copyright (c) 2002, 2004 Marek Michalkiewicz
Copyright (c) 2005, 2006, 2007 Eric B. Weddington
All rights reserved.
@@ -40,59 +45,60 @@
#include <avr/io.h>
#include <stdint.h>
/** \file */
/** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
\code #include <avr/wdt.h> \endcode
This header file declares the interface to some inline macros
handling the watchdog timer present in many AVR devices. In order
to prevent the watchdog timer configuration from being
accidentally altered by a crashing application, a special timed
sequence is required in order to change it. The macros within
this header file handle the required sequence automatically
before changing any value. Interrupts will be disabled during
the manipulation.
\note Depending on the fuse configuration of the particular
device, further restrictions might apply, in particular it might
be disallowed to turn off the watchdog timer.
Note that for newer devices (ATmega88 and newer, effectively any
AVR that has the option to also generate interrupts), the watchdog
timer remains active even after a system reset (except a power-on
condition), using the fastest prescaler value (approximately 15
ms). It is therefore required to turn off the watchdog early
during program startup, the datasheet recommends a sequence like
the following:
\code
#include <stdint.h>
#include <avr/wdt.h>
uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
void get_mcusr(void) \
__attribute__((naked)) \
__attribute__((section(".init3")));
void get_mcusr(void)
{
mcusr_mirror = MCUSR;
MCUSR = 0;
wdt_disable();
}
\endcode
Saving the value of MCUSR in \c mcusr_mirror is only needed if the
application later wants to examine the reset source, but in particular,
clearing the watchdog reset flag before disabling the
watchdog is required, according to the datasheet.
/**
* @defgroup avr_watchdog Watchdog Timer Handling
*
* This header file declares the interface to some inline macros
* handling the watchdog timer present in many AVR devices. In order
* to prevent the watchdog timer configuration from being
* accidentally altered by a crashing application, a special timed
* equence is required in order to change it. The macros within
* this header file handle the required sequence automatically
* before changing any value. Interrupts will be disabled during
* the manipulation.
*
* Note: Depending on the fuse configuration of the particular
* device, further restrictions might apply, in particular it might
* be disallowed to turn off the watchdog timer.
*
* Note that for newer devices (ATmega88 and newer, effectively any
* AVR that has the option to also generate interrupts), the watchdog
* timer remains active even after a system reset (except a power-on
* condition), using the fastest prescaler value (approximately 15
* ms). It is therefore required to turn off the watchdog early
* during program startup, the datasheet recommends a sequence like
* the following:
*
* @code{.c}
* #include <stdint.h>
* #include <avr/wdt.h>
*
* uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
*
* void get_mcusr(void) \
* __attribute__((naked)) \
* __attribute__((section(".init3")));
* void get_mcusr(void)
* {
* mcusr_mirror = MCUSR;
* MCUSR = 0;
* wdt_disable();
* }
* @endcode
*
* Saving the value of MCUSR in @c mcusr_mirror is only needed if the
* application later wants to examine the reset source, but in particular,
* clearing the watchdog reset flag before disabling the
* watchdog is required, according to the datasheet.
* @{
*/
/**
\ingroup avr_watchdog
Reset the watchdog timer. When the watchdog timer is enabled,
a call to this instruction is required before the timer expires,
otherwise a watchdog-initiated device reset will occur.
* @brief Watchdog Timer Reset
*
* Reset the watchdog timer. When the watchdog timer is enabled,
* a call to this instruction is required before the timer expires,
* otherwise a watchdog-initiated device reset will occur.
*/
#define wdt_reset() __asm__ __volatile__ ("wdr")
@@ -118,14 +124,13 @@
/**
\ingroup avr_watchdog
Enable the watchdog timer, configuring it for expiry after
\c timeout (which is a combination of the \c WDP0 through
\c WDP2 bits to write into the \c WDTCR register; For those devices
that have a \c WDTCSR register, it uses the combination of the \c WDP0
through \c WDP3 bits).
See also the symbolic constants \c WDTO_15MS et al.
* Enable the watchdog timer, configuring it for expiry after
* @c timeout (which is a combination of the @c WDP0 through
* @c WDP2 bits to write into the @c WDTCR register; For those devices
* that have a @c WDTCSR register, it uses the combination of the @c WDP0
* through @c WDP3 bits).
*
* See also the symbolic constants @c WDTO_15MS et al.
*/
@@ -317,10 +322,9 @@ __asm__ __volatile__ ( \
)
/**
\ingroup avr_watchdog
Disable the watchdog timer, if possible. This attempts to turn off the
Enable bit in the watchdog control register. See the datasheet for
details.
* Disable the watchdog timer, if possible. This attempts to turn off the
* Enable bit in the watchdog control register. See the datasheet for
* details.
*/
#define wdt_disable() \
__asm__ __volatile__ ( \
@@ -340,101 +344,77 @@ __asm__ __volatile__ ( \
/**
\ingroup avr_watchdog
Symbolic constants for the watchdog timeout. Since the watchdog
timer is based on a free-running RC oscillator, the times are
approximate only and apply to a supply voltage of 5 V. At lower
supply voltages, the times will increase. For older devices, the
times will be as large as three times when operating at Vcc = 3 V,
while the newer devices (e. g. ATmega128, ATmega8) only experience
a negligible change.
Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
Symbolic constants are formed by the prefix
\c WDTO_, followed by the time.
Example that would select a watchdog timer expiry of approximately
500 ms:
\code
wdt_enable(WDTO_500MS);
\endcode
* Symbolic constants for the watchdog timeout. Since the watchdog
* timer is based on a free-running RC oscillator, the times are
* approximate only and apply to a supply voltage of 5 V. At lower
* supply voltages, the times will increase. For older devices, the
* times will be as large as three times when operating at Vcc = 3 V,
* while the newer devices (e. g. ATmega128, ATmega8) only experience
* a negligible change.
*
* Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
* 500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
* Symbolic constants are formed by the prefix
* @c WDTO_, followed by the time.
*
* Example that would select a watchdog timer expiry of approximately
* 500 ms:
*
* @code{.c}
* wdt_enable(WDTO_500MS);
* @endcode
*/
#define WDTO_15MS 0
/** \ingroup avr_watchdog
See \c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_30MS 1
/** \ingroup avr_watchdog See
\c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_60MS 2
/** \ingroup avr_watchdog
See \c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_120MS 3
/** \ingroup avr_watchdog
See \c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_250MS 4
/** \ingroup avr_watchdog
See \c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_500MS 5
/** \ingroup avr_watchdog
See \c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_1S 6
/** \ingroup avr_watchdog
See \c WDT0_15MS */
/** @see WDT0_15MS */
#define WDTO_2S 7
#if defined(__DOXYGEN__) || defined(WDP3)
/** \ingroup avr_watchdog
See \c WDT0_15MS
Note: This is only available on the
ATtiny2313,
ATtiny24, ATtiny44, ATtiny84,
ATtiny25, ATtiny45, ATtiny85,
ATtiny261, ATtiny461, ATtiny861,
ATmega48, ATmega88, ATmega168,
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
ATmega164P, ATmega324P, ATmega644P, ATmega644,
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
ATmega8HVA, ATmega16HVA, ATmega32HVB,
ATmega406, ATmega1284P,
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
AT90PWM81,
AT90USB82, AT90USB162,
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
ATtiny48, ATtiny88.
*/
/**
* @see WDT0_15MS
*
* Note: This is only available on:
* ATtiny2313,
* ATtiny24, ATtiny44, ATtiny84,
* ATtiny25, ATtiny45, ATtiny85,
* ATtiny261, ATtiny461, ATtiny861,
* ATmega48, ATmega88, ATmega168,
* ATmega48P, ATmega88P, ATmega168P, ATmega328P,
* ATmega164P, ATmega324P, ATmega644P, ATmega644,
* ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
* ATmega8HVA, ATmega16HVA, ATmega32HVB,
* ATmega406, ATmega1284P,
* AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
* AT90PWM81,
* AT90USB82, AT90USB162,
* AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
* ATtiny48, ATtiny88.
*/
#define WDTO_4S 8
/** \ingroup avr_watchdog
See \c WDT0_15MS
Note: This is only available on the
ATtiny2313,
ATtiny24, ATtiny44, ATtiny84,
ATtiny25, ATtiny45, ATtiny85,
ATtiny261, ATtiny461, ATtiny861,
ATmega48, ATmega88, ATmega168,
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
ATmega164P, ATmega324P, ATmega644P, ATmega644,
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
ATmega8HVA, ATmega16HVA, ATmega32HVB,
ATmega406, ATmega1284P,
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
AT90PWM81,
AT90USB82, AT90USB162,
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
ATtiny48, ATtiny88.
*/
/** @see WDTO_4S */
#define WDTO_8S 9
#endif /* defined(__DOXYGEN__) || defined(WDP3) */
/** @} */
#endif /* _AVR_WDT_H_ */