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adapted gen83xx to new board

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This commit is contained in:
Thomas Doerfler
2008-05-15 15:10:38 +00:00
parent 8ac748c1bf
commit 42bf1b9f13
44 changed files with 1633 additions and 619 deletions
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4
c/src/lib/libbsp/arm/edb7312/preinstall.am
View File

@@ -68,3 +68,7 @@ $(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h

190
c/src/lib/libbsp/arm/nds/preinstall.am
View File

@@ -1,6 +1,4 @@
##
## $Id$
##
## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
@@ -38,6 +36,10 @@ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
@@ -46,10 +48,6 @@ $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
@@ -58,6 +56,184 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
$(PROJECT_INCLUDE)/rtems/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/fb.h: fb/fb.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/fb.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/fb.h
$(PROJECT_INCLUDE)/rtems/touchscreen.h: touchscreen/touchscreen.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/touchscreen.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/touchscreen.h
$(PROJECT_INCLUDE)/rtems/sound.h: sound/sound.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/sound.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/sound.h
$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
$(PROJECT_INCLUDE)/libnds/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds
@: > $(PROJECT_INCLUDE)/libnds/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/$(dirstamp)
$(PROJECT_INCLUDE)/libnds/gbfs.h: libnds/include/gbfs.h $(PROJECT_INCLUDE)/libnds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/gbfs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/gbfs.h
$(PROJECT_INCLUDE)/libnds/nds.h: libnds/include/nds.h $(PROJECT_INCLUDE)/libnds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds.h
$(PROJECT_INCLUDE)/libnds/nds/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds
@: > $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(PROJECT_INCLUDE)/libnds/nds/memory.h: libnds/include/nds/memory.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/memory.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/memory.h
$(PROJECT_INCLUDE)/libnds/nds/system.h: libnds/include/nds/system.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/system.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/system.h
$(PROJECT_INCLUDE)/libnds/nds/bios.h: libnds/include/nds/bios.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/bios.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/bios.h
$(PROJECT_INCLUDE)/libnds/nds/registers_alt.h: libnds/include/nds/registers_alt.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h
$(PROJECT_INCLUDE)/libnds/nds/interrupts.h: libnds/include/nds/interrupts.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/interrupts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/interrupts.h
$(PROJECT_INCLUDE)/libnds/nds/card.h: libnds/include/nds/card.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/card.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/card.h
$(PROJECT_INCLUDE)/libnds/nds/ipc.h: libnds/include/nds/ipc.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/ipc.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/ipc.h
$(PROJECT_INCLUDE)/libnds/nds/timers.h: libnds/include/nds/timers.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/timers.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/timers.h
$(PROJECT_INCLUDE)/libnds/nds/dma.h: libnds/include/nds/dma.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/dma.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/dma.h
$(PROJECT_INCLUDE)/libnds/nds/reload.h: libnds/include/nds/reload.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/reload.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/reload.h
$(PROJECT_INCLUDE)/libnds/nds/jtypes.h: libnds/include/nds/jtypes.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/jtypes.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/jtypes.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm9
@: > $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h: libnds/include/nds/arm9/ndsmotion.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h: libnds/include/nds/arm9/pcx.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/input.h: libnds/include/nds/arm9/input.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/math.h: libnds/include/nds/arm9/math.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/console.h: libnds/include/nds/arm9/console.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h: libnds/include/nds/arm9/sprite.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h: libnds/include/nds/arm9/videoGL.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h: libnds/include/nds/arm9/cache.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/image.h: libnds/include/nds/arm9/image.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h: libnds/include/nds/arm9/trig_lut.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/video.h: libnds/include/nds/arm9/video.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h: libnds/include/nds/arm9/exceptions.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h: libnds/include/nds/arm9/rumble.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/background.h: libnds/include/nds/arm9/background.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h: libnds/include/nds/arm9/boxtest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h: libnds/include/nds/arm9/postest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h
$(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h: libnds/include/nds/arm9/sound.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h
$(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm7
@: > $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
$(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h: libnds/include/nds/arm7/serial.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h
$(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h: libnds/include/nds/arm7/audio.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h
$(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h: libnds/include/nds/arm7/clock.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h
$(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h: libnds/include/nds/arm7/touch.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h
$(PROJECT_LIB)/coproc.bin: coproc.bin $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/coproc.bin
TMPINSTALL_FILES += $(PROJECT_LIB)/coproc.bin

4
c/src/lib/libbsp/bfin/eZKit533/preinstall.am
View File

@@ -36,10 +36,6 @@ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h

33
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
View File

@@ -1,3 +1,36 @@
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* network/network.c, start/start.S:
add support for different board
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* irq/ipic.c:
make sure, that the masking operations in
ICTL and MSR are executed in order
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* include/bsp.h, startup/bspstart.c,
* console/console.c, console/config.c:
derived module input frequencies from internal bus clock during
start time
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* spi/spi_init.c:
added base frequency into softc structure, added fm25l256 driver
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* i2c/i2c_init.c:
added base frequency into softc structure
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* include/bsp.h, include/hwreg_vals.h, ./Makefile.am:
moved HW register settings from bsp.h to hwreg_vals.h
2008-05-14 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am: Rework to avoid .rel files.

2
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
View File

@@ -45,7 +45,9 @@ startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \
pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
include_bsp_HEADERS = ./irq/irq.h \
./include/hwreg_vals.h \
../../powerpc/shared/vectors/vectors.h
vectors_SOURCES = ../../powerpc/shared/vectors/vectors.h \
../../powerpc/shared/vectors/vectors_init.c \
../../powerpc/shared/vectors/vectors.S

10
c/src/lib/libbsp/powerpc/gen83xx/console/config.c
View File

@@ -105,10 +105,11 @@ console_tbl Console_Port_Tbl[] = {
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
BSP_CSB_CLK_FRQ, /* ulClock */
0, /* ulClock (filled in init) */
0 /* ulIntVector */
},
{
}
#if BSP_USE_UART2
,{
"/dev/ttyS1", /* sDeviceName */
SERIAL_NS16550, /* deviceType */
NS16550_FUNCTIONS, /* pDeviceFns */
@@ -124,8 +125,9 @@ console_tbl Console_Port_Tbl[] = {
Write_ns16550_register, /* setRegister */
NULL, /* getData */
NULL, /* setData */
BSP_CSB_CLK_FRQ, /* ulClock */
0, /* ulClock (filled in init) */
0 /* ulIntVector */
}
#endif
};

5
c/src/lib/libbsp/powerpc/gen83xx/console/console.c
View File

@@ -172,6 +172,11 @@ rtems_device_driver console_initialize(
minor<Console_Port_Count;
minor++)
{
/*
* transfer the real internal bus frequency into the
* console port table
*/
Console_Port_Tbl[minor].ulClock = BSP_bus_frequency;
/*
* First perform the configuration dependant probe, then the
* device dependant probe

21
c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c
View File

@@ -31,7 +31,8 @@ static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
{ /* our private fields */
reg_ptr: &mpc83xx.i2c[0],
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_I2C1
irq_number : BSP_IPIC_IRQ_I2C1,
base_frq : 0 /* will be set during initiailization */
}
},
/* second channel */
@@ -43,7 +44,8 @@ static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = {
{ /* our private fields */
reg_ptr: &mpc83xx.i2c[1],
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_I2C2
irq_number : BSP_IPIC_IRQ_I2C2,
base_frq : 0 /* will be set during initiailization */
}
}
};
@@ -80,6 +82,19 @@ rtems_status_code bsp_register_i2c
*/
rtems_libi2c_initialize ();
/*
* update input frequency of I2c modules into descriptor
*/
/*
* I2C1 is clocked with TSEC 1
*/
if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) {
mpc83xx_i2c_bus_tbl[0].softc.base_frq =
(BSP_bus_frequency
/((mpc83xx.clk.sccr >> (31-1)) & 0x03));
}
mpc83xx_i2c_bus_tbl[1].softc.base_frq = BSP_bus_frequency;
/*
* register first I2C bus
*/
@@ -98,6 +113,7 @@ rtems_status_code bsp_register_i2c
return -ret_code;
}
i2c2_busno = ret_code;
/*
* register EEPROM to bus 1, Address 0x50
*/
@@ -107,6 +123,7 @@ rtems_status_code bsp_register_i2c
if (ret_code < 0) {
return -ret_code;
}
/*
* FIXME: register RTC driver, when available
*/

188
c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
View File

@@ -20,166 +20,7 @@
#ifndef __GEN83xx_BSP_h
#define __GEN83xx_BSP_h
/*
* distinguish board characteristics
*/
/*
* for Freescale MPC8349 EAMDS
*/
#if defined(MPC8349EAMDS)
/*
* two DUART channels supported
*/
#define GEN83xx_DUART_AVAIL_MASK 0x03
/* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT
/*
* clocking infos
*/
#define BSP_CLKIN_FRQ 66000000L
#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(4) | \
RCWLR_COREPLL(4))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_GMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
/*
* for JPK HSC_CM01
*/
#elif defined(HSC_CM01)
/*
* one DUART channel (UART1) supported
*/
#define GEN83xx_DUART_AVAIL_MASK 0x01
/* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT
/*
* clocking infos
*/
#define BSP_CLKIN_FRQ 66000000L
#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(4) | \
RCWLR_COREPLL(4))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_RGMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
#else
#error "board type not defined"
#endif
/*
* for JPK HSC_CM01 and freescale MPC8349EAMDS
*/
#if defined(MPC8349EAMDS) || defined(HSC_CM01)
/*
* address range definitions
*/
/* ROM definitions (8 MB, mirrored multiple times) */
#define ROM_START 0xFE000000
#define ROM_SIZE 0x02000000
#define ROM_END (ROM_START+ROM_SIZE-1)
#define BOOT_START ROM_START
#define BOOT_END ROM_END
/* SDRAM definitions (256 MB) */
#define RAM_START 0x00000000
#define RAM_SIZE 0x10000000
#define RAM_END (RAM_START+RAM_SIZE-1)
/* working internal memory map base address */
#define IMMRBAR 0xE0000000
/*
* working values for various registers, used in start/start.S
*/
/*
* Local Access Windows
* FIXME: decode bit settings
*/
#define LBLAWBAR0_VAL 0xFE000000
#define LBLAWAR0_VAL 0x80000016
#define LBLAWBAR1_VAL 0xF8000000
#define LBLAWAR1_VAL 0x8000000E
#define LBLAWBAR2_VAL 0xF0000000
#define LBLAWAR2_VAL 0x80000019
#define DDRLAWBAR0_VAL 0x00000000
#define DDRLAWAR0_VAL 0x8000001B
/*
* Local Bus (Memory) Controller
* FIXME: decode bit settings
*/
#define BR0_VAL 0xFE001001
#define OR0_VAL 0xFF806FF7
#define BR1_VAL 0xF8000801
#define OR1_VAL 0xFFFFE8F0
#define BR2_VAL 0xF0001861
#define OR2_VAL 0xFC006901
/*
* SDRAM registers
* FIXME: decode bit settings
*/
#define MRPTR_VAL 0x20000000
#define LSRT_VAL 0x32000000
#define LSDMR_VAL 0x4062D733
#define LCRR_VAL 0x80000004
/*
* DDR-SDRAM registers
* FIXME: decode bit settings
*/
#define CS2_BNDS_VAL 0x00000007
#define CS3_BNDS_VAL 0x0008000F
#define CS2_CONFIG_VAL 0x80000101
#define CS3_CONFIG_VAL 0x80000101
#define TIMING_CFG_1_VAL 0x36333321
#define TIMING_CFG_2_VAL 0x00000800
#define DDR_SDRAM_CFG_VAL 0xC2000000
#define DDR_SDRAM_MODE_VAL 0x00000022
#define DDR_SDRAM_INTTVL_VAL 0x045B0100
#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000
#else
#error "board type not defined"
#endif
#include <bsp/hwreg_vals.h>
#ifndef ASM
@@ -246,6 +87,12 @@ rtems_status_code bsp_register_spi(void);
#endif
#define PRINTK_MINOR BSP_UART1_MINOR
#if defined(MPC8249EAMDS)
#define BSP_USE_UART2 TRUE
#else
#define BSP_USE_UART2 FALSE
#endif
#define SINGLE_CHAR_MODE
#define UARTS_USE_TERMIOS_INT 1
@@ -260,9 +107,10 @@ rtems_status_code bsp_register_spi(void);
* floating point math.
* (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
*/
#define BSP_CSB_CLK_FRQ (BSP_CLKIN_FRQ * BSP_SYSPLL_MF)
extern unsigned int BSP_bus_frequency;
#define BSP_Convert_decrementer( _value ) \
(int) (((_value) * 4000) / (BSP_CSB_CLK_FRQ/10000))
(int) (((_value) * 4000) / (BSP_bus_frequency/10000))
/*
* Network driver configuration
@@ -274,6 +122,7 @@ extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2"
#if defined(MPC8349EAMDS)
/*
* i2c EEPROM device name
*/
@@ -285,6 +134,21 @@ extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching);
*/
#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash"
#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash"
#endif /* defined(MPC8349EAMDS) */
#if defined(HSC_CM01)
/*
* i2c EEPROM device name
*/
#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
/*
* SPI FRAM device name
*/
#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram"
#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram"
#endif /* defined(HSC_CM01) */
#ifdef __cplusplus
}

268
c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h Normal file
View File

@@ -0,0 +1,268 @@
/*===============================================================*\
| Project: RTEMS generic MPC83xx BSP |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| this file contains board specific definitions |
\*===============================================================*/
#ifndef __GEN83xx_HWREG_VALS_h
#define __GEN83xx_HWREG_VALS_h
#include <mpc83xx/mpc83xx.h>
/*
* distinguish board characteristics
*/
#if defined(MPC8349EAMDS)
/*
* for Freescale MPC8349 EAMDS
*/
/*
* two DUART channels supported
*/
#define GEN83xx_DUART_AVAIL_MASK 0x03
/* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT
/*
* clocking infos
*/
#define BSP_CLKIN_FRQ 66000000L
#define RCFG_SYSPLL_MF 4
#define RCFG_COREPLL_MF 4
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(RCFG_SYSPLL_MF) | \
RCWLR_COREPLL(RCFG_COREPLL_MF))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_GMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
#elif defined(HSC_CM01)
/*
* for JPK HSC_CM01
*/
/*
* one DUART channel (UART1) supported
*/
#define GEN83xx_DUART_AVAIL_MASK 0x01
/* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT
/*
* clocking infos
*/
#define BSP_CLKIN_FRQ 30000000L
#define RCFG_SYSPLL_MF 11
#define RCFG_COREPLL_MF 4
/*
* Reset configuration words
*/
#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
RCWLR_DDRCM_1_1 | \
RCWLR_SPMF(RCFG_SYSPLL_MF) | \
RCWLR_COREPLL(RCFG_COREPLL_MF))
#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
RCWHR_PCI_32 | \
RCWHR_PCI1ARB_EN | \
RCWHR_PCI2ARB_EN | \
RCWHR_CORE_EN | \
RCWHR_BMS_LOW | \
RCWHR_BOOTSEQ_NONE | \
RCWHR_SW_DIS | \
RCWHR_ROMLOC_LB16 | \
RCWHR_TSEC1M_RGMII | \
RCWHR_TSEC2M_GMII | \
RCWHR_ENDIAN_BIG | \
RCWHR_LALE_NORM | \
RCWHR_LDP_PAR)
#else
#error "board type not defined"
#endif
#if defined(MPC8349EAMDS)
/**************************
* for Freescale MPC8349EAMDS
*/
/*
* address range definitions
*/
/* ROM definitions (8 MB, mirrored multiple times) */
#define ROM_START 0xFE000000
#define ROM_SIZE 0x02000000
#define ROM_END (ROM_START+ROM_SIZE-1)
#define BOOT_START ROM_START
#define BOOT_END ROM_END
/* SDRAM definitions (256 MB) */
#define RAM_START 0x00000000
#define RAM_SIZE 0x10000000
#define RAM_END (RAM_START+RAM_SIZE-1)
/* working internal memory map base address */
#define IMMRBAR 0xE0000000
/*
* working values for various registers, used in start/start.S
*/
/*
* Local Access Windows
* FIXME: decode bit settings
*/
#define LBLAWBAR0_VAL 0xFE000000
#define LBLAWAR0_VAL 0x80000016
#define LBLAWBAR1_VAL 0xF8000000
#define LBLAWAR1_VAL 0x8000000E
#define LBLAWBAR2_VAL 0xF0000000
#define LBLAWAR2_VAL 0x80000019
#define DDRLAWBAR0_VAL 0x00000000
#define DDRLAWAR0_VAL 0x8000001B
/*
* Local Bus (Memory) Controller
* FIXME: decode bit settings
*/
#define BR0_VAL 0xFE001001
#define OR0_VAL 0xFF806FF7
#define BR1_VAL 0xF8000801
#define OR1_VAL 0xFFFFE8F0
#define BR2_VAL 0xF0001861
#define OR2_VAL 0xFC006901
/*
* SDRAM registers
* FIXME: decode bit settings
*/
#define MRPTR_VAL 0x20000000
#define LSRT_VAL 0x32000000
#define LSDMR_VAL 0x4062D733
#define LCRR_VAL 0x80000004
/*
* DDR-SDRAM registers
* FIXME: decode bit settings
*/
#define CS2_BNDS_VAL 0x00000007
#define CS3_BNDS_VAL 0x0008000F
#define CS2_CONFIG_VAL 0x80000101
#define CS3_CONFIG_VAL 0x80000101
#define TIMING_CFG_1_VAL 0x36333321
#define TIMING_CFG_2_VAL 0x00000800
#define DDR_SDRAM_CFG_VAL 0xC2000000
#define DDR_SDRAM_MODE_VAL 0x00000022
#define DDR_SDRAM_INTTVL_VAL 0x045B0100
#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000
#elif defined(HSC_CM01)
/**************************
* for JPK HSC_CM01
*/
/*
* address range definitions
*/
/* ROM definitions (8 MB, mirrored multiple times) */
#define ROM_START 0xFE000000
#define ROM_SIZE 0x02000000
#define ROM_END (ROM_START+ROM_SIZE-1)
#define BOOT_START ROM_START
#define BOOT_END ROM_END
/* SDRAM definitions (256 MB) */
#define RAM_START 0x00000000
#define RAM_SIZE 0x10000000
#define RAM_END (RAM_START+RAM_SIZE-1)
/* working internal memory map base address */
#define IMMRBAR 0xE0000000
/*
* working values for various registers, used in start/start.S
*/
/*
* Local Access Windows
* FIXME: decode bit settings
*/
#define LBLAWBAR0_VAL ROM_START
#define LBLAWAR0_VAL 0x80000018
#define LBLAWBAR1_VAL 0xF8000000
#define LBLAWAR1_VAL 0x80000015
#define DDRLAWBAR0_VAL RAM_START
#define DDRLAWAR0_VAL 0x8000001B
/*
* Local Bus (Memory) Controller
* FIXME: decode bit settings
*/
#define BR0_VAL 0xFE001001
#define OR0_VAL 0xFE000E54
#define BR3_VAL 0xF8001881
#define OR3_VAL 0xFFC01100
/*
* Local (memory) bus divider
* FIXME: decode bit settings
*/
#define LCRR_VAL 0x00010004
/*
* DDR-SDRAM registers
* FIXME: decode bit settings
*/
#define DDRCDR_VAL 0x00000001
#define CS0_BNDS_VAL 0x0000000F
#define CS0_CONFIG_VAL 0x80810102
#define TIMING_CFG_0_VAL 0x00420802
#define TIMING_CFG_1_VAL 0x3735A322
#define TIMING_CFG_2_VAL 0x2F9044C7
#define DDR_SDRAM_CFG_2_VAL 0x00401000
#define DDR_SDRAM_MODE_VAL 0x44521632
#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000
#define DDR_SDRAM_CFG_VAL 0x43000008
#define DDR_ERR_DISABLE_VAL 0x0000008D
#define DDR_ERR_DISABLE_VAL2 0x00000089
#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE
#define DDR_SDRAM_INIT_ADDR_VAL 0
#define DDR_SDRAM_INTERVAL_VAL 0x05080000
#else
#error "board type not defined"
#endif
/**************************
* derived values for all boards
*/
/* value of input clock divider (derived from pll mode reg) */
#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
/* value of system pll (derived from pll mode reg) */
#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f)
/* value of system pll (derived from pll mode reg) */
#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f)
#endif /* __GEN83xx_HWREG_VALS_h */

14
c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c
View File

@@ -272,6 +272,13 @@ rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum)
mpc83xx.ipic.simsr[1] &= mask_ptr->simsr_mask[1];
mpc83xx.ipic.semsr &= mask_ptr->semsr_mask ;
mpc83xx.ipic.sermr &= mask_ptr->sermr_mask ;
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
/*
* reenable msr_ee
*/
@@ -293,6 +300,13 @@ rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum)
* disable msr_enable
*/
_CPU_MSR_SET(msr_save);
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
/*
* restore initial masks
*/

26
c/src/lib/libbsp/powerpc/gen83xx/network/network.c
View File

@@ -26,10 +26,16 @@
#include <mpc83xx/mpc83xx.h>
#include <stdio.h>
#define TSEC_BITRATE 1000
#define TSEC_IFMODE_RGMII 0
#define TSEC_IFMODE_GMII 1
#if defined(MPC8349EAMDS)
#define TSEC_IFMODE TSEC_IFMODE_GMII
#endif
#if defined(HSC_CM01)
#define TSEC_IFMODE TSEC_IFMODE_RGMII
#endif
/*=========================================================================*\
| Function: |
@@ -61,6 +67,7 @@ int BSP_tsec_attach
return 0;
}
if (attaching) {
#if (TSEC_IFMODE==TSEC_IFMODE_GMII)
if (unitNumber == 1) {
/*
* init system I/O configuration registers
@@ -73,13 +80,20 @@ int BSP_tsec_attach
mpc83xx.gpio[1].gpdir = ((mpc83xx.gpio[1].gpdir & ~0x00000FFF)
| 0x0000001f);
}
}
if (unitNumber == 2) {
if (unitNumber == 2) {
/*
* init port registers (GPIO2DIR) for TSEC2
*/
mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
| 0x00087881);
}
#endif
#if (TSEC_IFMODE==TSEC_IFMODE_RGMII)
/*
* init port registers (GPIO2DIR) for TSEC2
* Nothing special needed for TSEC1 operation
*/
mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
| 0x00087881);
#endif
}
/*
* add MAC address into config->hardware_adderss

4
c/src/lib/libbsp/powerpc/gen83xx/preinstall.am
View File

@@ -81,6 +81,10 @@ $(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: ./include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
$(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h

29
c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c
View File

@@ -21,9 +21,11 @@
#include <bsp/irq.h>
#include <bsp.h>
#if defined(MPC8349EAMDS)
#include <libchip/i2c-2b-eeprom.h>
#include <libchip/spi-flash-m25p40.h>
#endif
#if defined(HSC_CM01)
#include <libchip/spi-fram-fm25l256.h>
#endif
/*=========================================================================*\
| Board-specific adaptation functions |
@@ -189,7 +191,8 @@ static mpc83xx_spi_desc_t bsp_spi_bus_desc = {
{ /* our private fields */
reg_ptr: &mpc83xx.spi,
initialized: FALSE,
irq_number: BSP_IPIC_IRQ_SPI
irq_number: BSP_IPIC_IRQ_SPI,
base_frq : 0 /* filled in during init */
}
};
@@ -247,6 +250,11 @@ rtems_status_code bsp_register_spi
mpc83xx.gpio[0].gpdir |= (0xf << (31-27));
mpc83xx.gpio[0].gpdr &= ~(0xf << (31-27));
#endif
/*
* update base frequency in spi descriptor
*/
bsp_spi_bus_desc.softc.base_frq = BSP_bus_frequency;
/*
* register SPI bus
*/
@@ -256,16 +264,27 @@ rtems_status_code bsp_register_spi
return -ret_code;
}
spi_busno = ret_code;
/*
* register M25P40 Flash, when available
*/
#if defined(MPC8349EAMDS)
/*
* register M25P40 Flash
*/
ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FLASH_DEVICE_NAME,
spi_flash_m25p40_rw_driver_descriptor,
spi_busno,0x00);
if (ret_code < 0) {
return -ret_code;
}
#endif
#if defined(HSC_CM01)
/*
* register FM25L256 FRAM
*/
ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FRAM_DEVICE_NAME,
spi_fram_fm25l256_rw_driver_descriptor,
spi_busno,0x02);
if (ret_code < 0) {
return -ret_code;
}
#endif
/*
* FIXME: further drivers, when available

139
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
View File

@@ -85,6 +85,7 @@
.extern boot_card
.extern MBAR
#if defined(RESET_CONF_WRD_L)
.section ".resconf","ax"
PUBLIC_VAR (reset_conf_words)
reset_conf_words:
@@ -97,6 +98,7 @@ reset_conf_words:
REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff))
REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff))
#endif
.section ".vectors","ax"
PUBLIC_VAR (reset_vec)
@@ -145,7 +147,6 @@ rom_entry:
* NOTE: now r31 points to onchip registers
*/
/*
* FIXME:
* we start from 0x100, so ROM is currently mapped to
* 0x00000000..
* in the next step, ROM will be remapped to its final location
@@ -223,6 +224,7 @@ start_code_in_rom:
#ifdef OR3_VAL
SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
#endif
/*
* ROM startup: init SDRAM access window
*/
@@ -238,9 +240,21 @@ start_code_in_rom:
#ifdef DDRLAWAR1_VAL
SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL
#endif
/*
* ROM startup: init refresh interval
*/
#ifdef MRPTR_VAL
SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL
#endif
/*
* ROM startup: init SDRAM
*/
#ifdef LSRT_VAL
SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL
#endif
#ifdef LSDMR_VAL
SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL
#endif
#ifdef CS0_BNDS_VAL
SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL
#endif
@@ -277,8 +291,8 @@ start_code_in_rom:
#ifdef TIMING_CFG_2_VAL
SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL
#endif
#ifdef DDR_SDRAM_CFG_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL
#ifdef DDRCDR_VAL
SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL
#endif
#ifdef DDR_SDRAM_CFG_2_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL
@@ -298,39 +312,123 @@ start_code_in_rom:
#ifdef DDR_SDRAM_CLK_CNTL_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL
#endif
#ifdef DDR_SDRAM_CFG_2_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT
#endif
#ifdef DDR_ERR_DISABLE_VAL
/*
* disable detect of RAM errors
*/
SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL
#endif
#ifdef DDR_SDRAM_DATA_INIT_VAL
/*
* set this value to initialize memory
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL
#endif
#ifdef DDR_SDRAM_INIT_ADDR_VAL
SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL
#endif
#ifdef DDR_SDRAM_CFG_VAL
/*
* FIXME: ROM startup: perform mode set commands etc for SDRAM
* config DDR SDRAM
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN
/*
* FIXME: wait 200us
*/
/*
* ROM startup: copy code to SDRAM
* enable DDR SDRAM
*/
LA r30, _text_start /* get start address of text section in RAM */
add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
LA r29, _text_start /* get start address of text section in RAM */
LA r28, _text_size /* get size of RAM image */
bl copy_image /* copy text section from ROM to RAM location */
SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN
/*
* wait, until DDR_SDRAM_CFG_2_D_INIT is cleared
*/
1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31)
andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT
bne 1b
#endif
#ifdef DDR_ERR_DISABLE_VAL2
/*
* enable detect of some RAM errors
*/
SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2
#endif
#ifdef DDR_SDRAM_INTERVAL_VAL
/*
* set the refresh interval
*/
SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL
#endif
start_rom_skip:
/*
* determine current execution address offset
*/
bl start_rom_skip1
start_rom_skip1:
mflr r20
LA r30,start_rom_skip1
sub. r20,r20,r30
/*
* execution address offset == 0?
* then do not relocate code and data
*/
beq start_code_in_ram
/*
* ROM or relocatable startup: copy startup code to SDRAM
*/
/* get start address of text section in RAM */
LA r29, _text_start
/* get start address of text section in ROM (add reloc offset) */
add r30, r20, r29
/* get size of startup code */
LA r28, end_reloc_startup
LA r31, _text_start
sub 28,r28,r31
/* copy startup code from ROM to RAM location */
bl copy_image
/*
* FIXME: ROM startup: copy data to SDRAM
*/
LA r30, _data_start /* get start address of data section in RAM */
add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
LA r29, _data_start /* get start address of data section in RAM */
LA r28, _data_size /* get size of RAM image */
bl copy_image /* copy initialized data section from ROM to RAM location */
/*
* ROM startup: jump to code copy in SDRAM
*/
LA r29, start_code_in_ram /* get compile time address of label */
/* get compile time address of label */
LA r29, copy_rest_of_text
mtlr r29
blr /* now further execution RAM */
copy_rest_of_text:
#ifdef LCRR_VAL
SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
#endif
/*
* ROM or relocatable startup: copy rest of code to SDRAM
*/
/* get start address of rest of code in RAM */
LA r29, end_reloc_startup
/* get start address of text section in ROM (add reloc offset) */
add r30, r20, r29
/* get size of rest of code */
LA r28, _text_start
LA r31, _text_size
add r28,r28,r31
sub r28,r28,r29
bl copy_image /* copy text section from ROM to RAM location */
/*
* ROM or relocatable startup: copy data to SDRAM
*/
/* get start address of data section in RAM */
LA r29, _data_start
/* get start address of data section in ROM (add reloc offset) */
add r30, r20, r29
/* get size of RAM image */
LA r28, _data_size
/* copy initialized data section from ROM to RAM location */
bl copy_image
start_code_in_ram:
start_rom_skip:
/*
* ROM/RAM startup: clear bss in SDRAM
*/
@@ -417,3 +515,4 @@ clr_mem_byte:
clr_mem_end:
blr /* return */
end_reloc_startup:

9
c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c
View File

@@ -48,7 +48,7 @@ static char *BSP_heap_start, *BSP_heap_end;
* Time base divisior: scaling value:
* BSP_time_base_divisor = TB ticks per millisecond/BSP_bus_frequency
*/
unsigned int BSP_bus_frequency = BSP_CSB_CLK_FRQ;
unsigned int BSP_bus_frequency;
unsigned int BSP_time_base_divisor = 4000; /* 4 bus clicks per TB click */
/*
@@ -187,10 +187,15 @@ void bsp_start(void)
*/
_write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
* this is evaluated during runtime, so it should be ok to set it
* before we initialize the drivers
*/
BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
/*
* initialize the device driver parameters
*/
bsp_clicks_per_usec = (BSP_CSB_CLK_FRQ/1000000);
bsp_clicks_per_usec = (BSP_bus_frequency/1000000);
/*
* Install our own set of exception vectors

5
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds
View File

@@ -43,7 +43,10 @@ SECTIONS
mpc83xx_regs (NOLOAD) :
{
IMMRBAR = .;
*mpc83xx_regs*(*)
mpc83xx_regs*(.text)
mpc83xx_regs*(.data)
mpc83xx_regs*(.bss)
mpc83xx_regs*(*COM*)
} > mpc83xx_regs
.resconf 0x000 :

7
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
View File

@@ -37,10 +37,13 @@ MEMORY
SECTIONS
{
mpc83xx_regs (NOLOAD) :
.mpc83xx_regs (NOLOAD) :
{
IMMRBAR = .;
*mpc83xx_regs*(*)
mpc83xx_regs*(.text)
mpc83xx_regs*(.data)
mpc83xx_regs*(.bss)
mpc83xx_regs*(*COM*)
} > mpc83xx_regs
.resconf 0x000 :

5
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds
View File

@@ -40,7 +40,10 @@ SECTIONS
mpc83xx_regs (NOLOAD) :
{
IMMRBAR = .;
*mpc83xx_regs*(*)
mpc83xx_regs*(.text)
mpc83xx_regs*(.data)
mpc83xx_regs*(.bss)
mpc83xx_regs*(*COM*)
} > mpc83xx_regs
.resconf 0x000 :

6
c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
View File

@@ -1,3 +1,9 @@
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* irq/irq.c:
make sure, that the masking operations in
ICTL and MSR are executed in order
2008-05-14 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am: Rework to avoid .rel files.

12
c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c
View File

@@ -472,6 +472,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT));
((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask;
}
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
@@ -480,6 +486,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
_CPU_MSR_SET(msr);
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
if (cpmIntr) {
irq -= BSP_CPM_IRQ_LOWEST_OFFSET;
((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq);

6
c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog
View File

@@ -1,3 +1,9 @@
2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* irq/irq.c:
make sure, that the masking operations in
ICTL and MSR are executed in order
2008-05-14 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am: Rework to avoid .rel files.

12
c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c
View File

@@ -483,6 +483,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
/* re-enable external exceptions */
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
@@ -494,6 +500,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
/* disable exceptions again */
_CPU_MSR_SET(msr);
/*
* make sure, that the masking operations in
* ICTL and MSR are executed in order
*/
asm volatile("sync":::"memory");
/* restore interrupt masks */
m8260.simr_h = old_simr_h;
m8260.simr_l = old_simr_l;

3
c/src/lib/libbsp/powerpc/mvme3100/preinstall.am
View File

@@ -137,7 +137,8 @@ $(PROJECT_INCLUDE)/bsp/vpd.h: ../shared/motorola/vpd.h $(PROJECT_INCLUDE)/bsp/$(
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vpd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vpd.h
if HAS_NETWORKING
$(PROJECT_INCLUDE)/bsp/if_tsec_pub.h: network/if_tsec_pub.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h
endif

34
c/src/lib/libbsp/powerpc/mvme5500/preinstall.am
View File

@@ -113,23 +113,6 @@ $(PROJECT_INCLUDE)/bsp/VPD.h: GT64260/VPD.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VPD.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VPD.h
if HAS_NETWORKING
$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
endif
$(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VME.h
@@ -158,6 +141,23 @@ $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(P
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
if HAS_NETWORKING
$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
endif
$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)