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Set up IRQ1* handling properly.

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This commit is contained in:
Eric Norum
2005-04-10 21:10:32 +00:00
parent edbd3df670
commit 402f4df9a2
2 changed files with 15 additions and 10 deletions
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4
c/src/lib/libbsp/m68k/uC5282/ChangeLog
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@@ -1,3 +1,7 @@
2005-04-10 Eric Norum <norume@aps.anl.gov>
* startup/bspstart.c: Set up IRQ1* handling properly.
2005-04-08 Eric Norum <norume@aps.anl.gov> 2005-04-08 Eric Norum <norume@aps.anl.gov>
* startup/bspstart.c: FPGA interrupt status register is now 16-bit. * startup/bspstart.c: FPGA interrupt status register is now 16-bit.

21
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
View File

@@ -363,17 +363,17 @@ int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
/* /*
* 'VME' interrupt support * 'VME' interrupt support
* Interrupt vectors 192-255 are set aside for use by external logic * Interrupt vectors 192-255 are set aside for use by external logic which
* which drives IRQ1*. The actual interrupt source is read from the * drives IRQ1*. The actual interrupt source is read from the external
* external logic at FPGA_IRQ_INFO. The most-significant bit of the * logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant
* value read from this location is set as long as the external logic * byte read from this location is set as long as the external logic has
* has interrupts to be serviced. The least-significant six bits * interrupts to be serviced. The least-significant six bits indicate the
* indicate the interrupt source within the external logic and are used * interrupt source within the external logic and are used to select the
* to select the specified interupt handler. * specified interupt handler.
*/ */
#define NVECTOR 256 #define NVECTOR 256
#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */ #define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
#define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_BOTHEDGE #define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL
#define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1 #define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1
#define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1 #define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1
#define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1 #define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1
@@ -401,8 +401,7 @@ trampoline (rtems_vector_number v)
* Handle FPGA interrupts until all have been consumed * Handle FPGA interrupts until all have been consumed
*/ */
if (v == FPGA_VECTOR) { if (v == FPGA_VECTOR) {
while (((MCF5282_EPORT_EPPDR & FPGA_EPPDR) == 0) while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
&& ((v = FPGA_IRQ_INFO) & 0x80)) {
v = 192 + (v & 0x3f); v = 192 + (v & 0x3f);
if (handlerTab[v].func) if (handlerTab[v].func)
(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
@@ -442,6 +441,8 @@ BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR; MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR; MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
MCF5282_EPORT_EPIER |= FPGA_EPIER; MCF5282_EPORT_EPIER |= FPGA_EPIER;
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
MCF5282_INTC_IMRL_MASKALL);
setupDone = 1; setupDone = 1;
i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL); i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
rtems_interrupt_enable(level); rtems_interrupt_enable(level);