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dev/serial: Optimize Zynq UART control reg writes

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Just disable RX/TX to start the initialization sequence.  Do not double
disable RX/TX.  Enable RX/TX after the mode is set.
This commit is contained in:
Sebastian Huber
2024-08-30 09:29:00 +02:00
parent ff9b19ad7c
commit 3fe69b03a3
1 changed files with 1 additions and 3 deletions
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4
bsps/shared/dev/serial/zynq-uart-polled.c
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@@ -135,20 +135,18 @@ void zynq_uart_initialize(volatile zynq_uart *regs)
&bdiv
);
regs->control = 0;
regs->control = ZYNQ_UART_CONTROL_RXDIS | ZYNQ_UART_CONTROL_TXDIS;
regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(cd);
regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bdiv);
/* A Tx/Rx logic reset must be issued after baud rate manipulation */
regs->control = ZYNQ_UART_CONTROL_RXDIS | ZYNQ_UART_CONTROL_TXDIS;
regs->control = ZYNQ_UART_CONTROL_RXRES | ZYNQ_UART_CONTROL_TXRES;
regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0);
regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0);
regs->control = ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL)
| ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE)
| ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8)
| mode_clks;
regs->control = ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
}
int zynq_uart_read_char_polled(volatile zynq_uart *regs)