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gumstix: added new doxygen

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This commit is contained in:
Daniel Ramirez
2013-12-21 15:36:05 -06:00
committed by Gedare Bloom
parent 2bafb96037
commit 3d6e1740ae
3 changed files with 312 additions and 107 deletions
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21
c/src/lib/libbsp/arm/gumstix/include/bsp.h
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@@ -1,3 +1,9 @@
/**
* @file
* @ingroup arm_gumstix
* @brief Global BSP definitions.
*/
/* /*
* By Yang Xi <hiyangxi@gmail.com>. * By Yang Xi <hiyangxi@gmail.com>.
* *
@@ -21,21 +27,28 @@ extern "C" {
#include <rtems/clockdrv.h> #include <rtems/clockdrv.h>
#include <libchip/serial.h> #include <libchip/serial.h>
/**
* @defgroup arm_gumstix Gumstix Support
* @ingroup bsp_arm
* @brief Gumstix support package
* @{
*/
#define BSP_FEATURE_IRQ_EXTENSION #define BSP_FEATURE_IRQ_EXTENSION
#define BSP_HAS_FRAME_BUFFER 1 #define BSP_HAS_FRAME_BUFFER 1
/* What is the input clock freq in hertz */ /** @brief What is the input clock freq in hertz */
#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ #define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */
#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ #define BSP_SLCK_FREQ 32768 /* 32.768 KHz */
/* What is the last interrupt */ /** @brief What is the last interrupt */
#define BSP_MAX_INT AT91RM9200_MAX_INT #define BSP_MAX_INT AT91RM9200_MAX_INT
console_tbl *BSP_get_uart_from_minor(int minor); console_tbl *BSP_get_uart_from_minor(int minor);
static inline int32_t BSP_get_baud(void) {return 115200;} static inline int32_t BSP_get_baud(void) {return 115200;}
/* How big should the interrupt stack be? */ /** @brief How big should the interrupt stack be? */
#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) #define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024)
#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ #define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */
@@ -58,6 +71,8 @@ extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int);
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_NE2000_NETWORK_DRIVER_ATTACH #define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_NE2000_NETWORK_DRIVER_ATTACH
#endif #endif
/** @} */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

22
c/src/lib/libbsp/arm/gumstix/include/tm27.h
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@@ -1,3 +1,9 @@
/**
* @file
* @ingroup gumstix_tm27
* @brief tm27 timing test support
*/
/* /*
* tm27.h * tm27.h
* *
@@ -13,8 +19,16 @@
#ifndef __tm27_h #ifndef __tm27_h
#define __tm27_h #define __tm27_h
/* /**
* Define the interrupt mechanism for Time Test 27 * @defgroup gumstix_tm27 tm27 Support
* @ingroup arm_gumstix
* @brief tm27 Timing Test Support
* @{
*/
/**
* @name Interrupt mechanisms for Time Test 27
* @{
*/ */
#define MUST_WAIT_FOR_INTERRUPT 0 #define MUST_WAIT_FOR_INTERRUPT 0
@@ -27,4 +41,8 @@
#define Lower_tm27_intr() /* empty */ #define Lower_tm27_intr() /* empty */
/** @} */
/** @} */
#endif #endif

376
c/src/lib/libbsp/arm/gumstix/rtl8019/wd80x3.h
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@@ -1,3 +1,9 @@
/**
* @file
* @ingroup gumstix_dp8390
* @brief DP8390 Ethernet Controller Support
*/
/* /*
* Information about the DP8390 Ethernet controller. * Information about the DP8390 Ethernet controller.
*/ */
@@ -6,126 +12,292 @@
#define __BSP_WD80x3_h #define __BSP_WD80x3_h
/* Register descriptions */ /* Register descriptions */
/* Controller DP8390. */
#define DATAPORT 0x10 /* Port Window. */ /**
#define RESET 0x1f /* Issue a read for reset */ * @defgroup gumstix_dp8390 DP8390 Support
#define W83CREG 0x00 /* I/O port definition */ * @ingroup arm_gumstix
* @brief DP8390 Ethernet Controller Support
* @{
*/
/**
* @name Controller DP8390.
* @{
*/
/** @brief Port Window. */
#define DATAPORT 0x10
/** @brief Issue a read for reset */
#define RESET 0x1f
/** @brief I/O port definition */
#define W83CREG 0x00
#define ADDROM 0x08 #define ADDROM 0x08
/* page 0 read or read/write registers */ /** @} */
/**
* @name page 0 read or read/write registers
* @{
*/
#define CMDR 0x00+RO #define CMDR 0x00+RO
#define CLDA0 0x01+RO /* current local dma addr 0 for read */ /** @brief current local dma addr 0 for read */
#define CLDA1 0x02+RO /* current local dma addr 1 for read */ #define CLDA0 0x01+RO
#define BNRY 0x03+RO /* boundary reg for rd and wr */ /** @brief current local dma addr 1 for read */
#define TSR 0x04+RO /* tx status reg for rd */ #define CLDA1 0x02+RO
#define NCR 0x05+RO /* number of collision reg for rd */ /** @brief boundary reg for rd and wr */
#define FIFO 0x06+RO /* FIFO for rd */ #define BNRY 0x03+RO
#define ISR 0x07+RO /* interrupt status reg for rd and wr */ /** @brief tx status reg for rd */
#define CRDA0 0x08+RO /* current remote dma address 0 for rd */ #define TSR 0x04+RO
#define CRDA1 0x09+RO /* current remote dma address 1 for rd */ /** @brief number of collision reg for rd */
#define RSR 0x0C+RO /* rx status reg for rd */ #define NCR 0x05+RO
#define CNTR0 0x0D+RO /* tally cnt 0 for frm alg err for rd */ /** @breif FIFO for rd */
#define CNTR1 RO+0x0E /* tally cnt 1 for crc err for rd */ #define FIFO 0x06+RO
#define CNTR2 0x0F+RO /* tally cnt 2 for missed pkt for rd */ /** @brief interrupt status reg for rd and wr */
#define ISR 0x07+RO
/** @brief current remote dma address 0 for rd */
#define CRDA0 0x08+RO
/** @brief current remote dma address 1 for rd */
#define CRDA1 0x09+RO
/** @brief rx status reg for rd */
#define RSR 0x0C+RO
/** @brief tally cnt 0 for frm alg err for rd */
#define CNTR0 0x0D+RO
/** @brief tally cnt 1 for crc err for rd */
#define CNTR1 RO+0x0E
/** @brief tally cnt 2 for missed pkt for rd */
#define CNTR2 0x0F+RO
/* page 0 write registers */ /** @} */
#define PSTART 0x01+RO /* page start register */ /**
#define PSTOP 0x02+RO /* page stop register */ * @name page 0 write registers
#define TPSR 0x04+RO /* tx start page start reg */ * @{
#define TBCR0 0x05+RO /* tx byte count 0 reg */ */
#define TBCR1 0x06+RO /* tx byte count 1 reg */
#define RSAR0 0x08+RO /* remote start address reg 0 */
#define RSAR1 0x09+RO /* remote start address reg 1 */
#define RBCR0 0x0A+RO /* remote byte count reg 0 */
#define RBCR1 0x0B+RO /* remote byte count reg 1 */
#define RCR 0x0C+RO /* rx configuration reg */
#define TCR 0x0D+RO /* tx configuration reg */
#define DCR RO+0x0E /* data configuration reg */
#define IMR 0x0F+RO /* interrupt mask reg */
/* page 1 registers */ /** @brief page start register */
#define PSTART 0x01+RO
/** @brief page stop register */
#define PSTOP 0x02+RO
/** @breif tx start page start reg */
#define TPSR 0x04+RO
/** @brief tx byte count 0 reg */
#define TBCR0 0x05+RO
/** @brief tx byte count 1 reg */
#define TBCR1 0x06+RO
/** @brief remote start address reg 0 */
#define RSAR0 0x08+RO
/** @brief remote start address reg 1 */
#define RSAR1 0x09+RO
/** @brief remote byte count reg 0 */
#define RBCR0 0x0A+RO
/** @brief remote byte count reg 1 */
#define RBCR1 0x0B+RO
/** @brief rx configuration reg */
#define RCR 0x0C+RO
/** @brief tx configuration reg */
#define TCR 0x0D+RO
/** @brief data configuration reg */
#define DCR RO+0x0E
/** @brief interrupt mask reg */
#define IMR 0x0F+RO
#define PAR 0x01+RO /* physical addr reg base for rd and wr */ /** @} */
#define CURR 0x07+RO /* current page reg for rd and wr */
#define MAR 0x08+RO /* multicast addr reg base fro rd and WR */
#define MARsize 8 /* size of multicast addr space */
/*-----W83CREG command bits-----*/ /**
#define MSK_RESET 0x80 /* W83CREG masks */ * @name page 1 registers
* @{
*/
/** @brief physical addr reg base for rd and wr */
#define PAR 0x01+RO
/** @brief current page reg for rd and wr */
#define CURR 0x07+RO
/** @brief multicast addr reg base fro rd and WR */
#define MAR 0x08+RO
/** @brief size of multicast addr space */
#define MARsize 8
/** @} */
/**
* @name W83CREG command bits
* @{
*/
/** @brief W83CREG masks */
#define MSK_RESET 0x80
#define MSK_ENASH 0x40 #define MSK_ENASH 0x40
#define MSK_DECOD 0x3F /* memory decode bits, corresponding */ /** @brief memory decode bits, corresponding */
/* to SA 18-13. SA 19 assumed to be 1 */ #define MSK_DECOD 0x3F
/*-----CMDR command bits-----*/ /** @} */
#define MSK_STP 0x01 /* stop the chip */
#define MSK_STA 0x02 /* start the chip */
#define MSK_TXP 0x04 /* initial txing of a frm */
#define MSK_RRE 0x08 /* remote read */
#define MSK_RWR 0x10 /* remote write */
#define MSK_RD2 0x20 /* no DMA used */
#define MSK_PG0 0x00 /* select register page 0 */
#define MSK_PG1 0x40 /* select register page 1 */
#define MSK_PG2 0x80 /* select register page 2 */
/*-----ISR and TSR status bits-----*/ /**
#define MSK_PRX 0x01 /* rx with no error */ * @name CMDR command bits
#define MSK_PTX 0x02 /* tx with no error */ * @{
#define MSK_RXE 0x04 /* rx with error */ */
#define MSK_TXE 0x08 /* tx with error */
#define MSK_OVW 0x10 /* overwrite warning */
#define MSK_CNT 0x20 /* MSB of one of the tally counters is set */
#define MSK_RDC 0x40 /* remote dma completed */
#define MSK_RST 0x80 /* reset state indicator */
/*-----DCR command bits-----*/ /** @brief stop the chip */
#define MSK_WTS 0x01 /* word transfer mode selection */ #define MSK_STP 0x01
#define MSK_BOS 0x02 /* byte order selection */ /** @brief start the chip */
#define MSK_LAS 0x04 /* long addr selection */ #define MSK_STA 0x02
#define MSK_BMS 0x08 /* burst mode selection */ /** @brief initial txing of a frm */
#define MSK_ARM 0x10 /* autoinitialize remote */ #define MSK_TXP 0x04
#define MSK_FT00 0x00 /* burst lrngth selection */ /** @brief remote read */
#define MSK_FT01 0x20 /* burst lrngth selection */ #define MSK_RRE 0x08
#define MSK_FT10 0x40 /* burst lrngth selection */ /** @brief remote write */
#define MSK_FT11 0x60 /* burst lrngth selection */ #define MSK_RWR 0x10
/** @brief no DMA used */
#define MSK_RD2 0x20
/** @brief select register page 0 */
#define MSK_PG0 0x00
/** @brief select register page 1 */
#define MSK_PG1 0x40
/** @brief select register page 2 */
#define MSK_PG2 0x80
/*-----RCR command bits-----*/ /** @} */
#define MSK_SEP 0x01 /* save error pkts */
#define MSK_AR 0x02 /* accept runt pkt */
#define MSK_AB 0x04 /* 8390 RCR */
#define MSK_AM 0x08 /* accept multicast */
#define MSK_PRO 0x10 /* accept all pkt with physical adr */
#define MSK_MON 0x20 /* monitor mode */
/*-----TCR command bits-----*/ /**
#define MSK_CRC 0x01 /* inhibit CRC, do not append crc */ * @name ISR and TSR status bits
#define MSK_LOOP 0x02 /* set loopback mode */ * @{
#define MSK_BCST 0x04 /* Accept broadcasts */ */
#define MSK_LB01 0x06 /* encoded loopback control */
#define MSK_ATD 0x08 /* auto tx disable */
#define MSK_OFST 0x10 /* collision offset enable */
/*-----receive status bits-----*/ /* @brief rx with no error */
#define SMK_PRX 0x01 /* rx without error */ #define MSK_PRX 0x01
#define SMK_CRC 0x02 /* CRC error */ /* @brief tx with no error */
#define SMK_FAE 0x04 /* frame alignment error */ #define MSK_PTX 0x02
#define SMK_FO 0x08 /* FIFO overrun */ /* @brief rx with error */
#define SMK_MPA 0x10 /* missed pkt */ #define MSK_RXE 0x04
#define SMK_PHY 0x20 /* physical/multicase address */ /* @brief tx with error */
#define SMK_DIS 0x40 /* receiver disable. set in monitor mode */ #define MSK_TXE 0x08
#define SMK_DEF 0x80 /* deferring */ /* @brief overwrite warning */
#define MSK_OVW 0x10
/* @brief MSB of one of the tally counters is set */
#define MSK_CNT 0x20
/* @brief remote dma completed */
#define MSK_RDC 0x40
/* @brief reset state indicator */
#define MSK_RST 0x80
/*-----transmit status bits-----*/ /** @} */
#define SMK_PTX 0x01 /* tx without error */
#define SMK_DFR 0x02 /* non deferred tx */ /**
#define SMK_COL 0x04 /* tx collided */ * @name DCR command bits
#define SMK_ABT 0x08 /* tx abort because of excessive collisions */ * @{
#define SMK_CRS 0x10 /* carrier sense lost */ */
#define SMK_FU 0x20 /* FIFO underrun */
#define SMK_CDH 0x40 /* collision detect heartbeat */ /** @brief word transfer mode selection */
#define SMK_OWC 0x80 /* out of window collision */ #define MSK_WTS 0x01
/** @brief byte order selection */
#define MSK_BOS 0x02
/** @brief long addr selection */
#define MSK_LAS 0x04
/** @brief burst mode selection */
#define MSK_BMS 0x08
/** @brief autoinitialize remote */
#define MSK_ARM 0x10
/** @brief burst lrngth selection */
#define MSK_FT00 0x00
/** @brief burst lrngth selection */
#define MSK_FT01 0x20
/** @brief burst lrngth selection */
#define MSK_FT10 0x40
/** @brief burst lrngth selection */
#define MSK_FT11 0x60
/** @} */
/**
* @name RCR command bits
* @{
*/
/** @brief save error pkts */
#define MSK_SEP 0x01
/** @brief accept runt pkt */
#define MSK_AR 0x02
/** @brief 8390 RCR */
#define MSK_AB 0x04
/** @brief accept multicast */
#define MSK_AM 0x08
/** @brief accept all pkt with physical adr */
#define MSK_PRO 0x10
/** @brief monitor mode */
#define MSK_MON 0x20
/** @} */
/**
* @name TCR command bits
* @{
*/
/** @brief inhibit CRC, do not append crc */
#define MSK_CRC 0x01
/** @brief set loopback mode */
#define MSK_LOOP 0x02
/** @brief Accept broadcasts */
#define MSK_BCST 0x04
/** @brief encoded loopback control */
#define MSK_LB01 0x06
/** @brief auto tx disable */
#define MSK_ATD 0x08
/** @brief collision offset enable */
#define MSK_OFST 0x10
/** @} */
/**
* @name receive status bits
* @{
*/
/** @brief rx without error */
#define SMK_PRX 0x01
/** @brief CRC error */
#define SMK_CRC 0x02
/** @brief frame alignment error */
#define SMK_FAE 0x04
/** @brief FIFO overrun */
#define SMK_FO 0x08
/** @brief missed pkt */
#define SMK_MPA 0x10
/** @brief physical/multicase address */
#define SMK_PHY 0x20
/** @brief receiver disable. set in monitor mode */
#define SMK_DIS 0x40
/** @brief deferring */
#define SMK_DEF 0x80
/** @} */
/**
* @name transmit status bits
* @{
*/
/** @brief tx without error */
#define SMK_PTX 0x01
/** @brief non deferred tx */
#define SMK_DFR 0x02
/** @brief tx collided */
#define SMK_COL 0x04
/** @brief tx abort because of excessive collisions */
#define SMK_ABT 0x08
/** @brief carrier sense lost */
#define SMK_CRS 0x10
/** @brief FIFO underrun */
#define SMK_FU 0x20
/** @brief collision detect heartbeat */
#define SMK_CDH 0x40
/** @brief out of window collision */
#define SMK_OWC 0x80
/** @} */
/** @} */
#endif #endif
/* end of include */ /* end of include */