forked from Imagelibrary/rtems
Rename or1ksim BSP to generic_or1k
or1ksim BSP was initially named after or1ksim simulator, and it was intented to only run there. But now it can also run on QEMU, jor1k and real FPGA boards without modifications. It makes more sense to give it a new generic name like generic_or1k.
This commit is contained in:
Hesham ALMatary
committed by
Gedare Bloom
Gedare Bloom
parent
491434cd7c
commit
3d597c04ed
@@ -2,8 +2,8 @@
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AC_DEFUN([RTEMS_CHECK_BSPDIR],
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[
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case "$1" in
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or1ksim )
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AC_CONFIG_SUBDIRS([or1ksim]);;
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generic_or1k )
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AC_CONFIG_SUBDIRS([generic_or1k]);;
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*)
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AC_MSG_ERROR([Invalid BSP]);;
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esac
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@@ -2,7 +2,7 @@
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AC_PREREQ([2.69])
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AC_INIT([rtems-c-src-lib-libbsp-or1k],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
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AC_CONFIG_SRCDIR([or1ksim])
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AC_CONFIG_SRCDIR([generic_or1k])
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RTEMS_TOP(../../../../..)
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RTEMS_CANONICAL_TARGET_CPU
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@@ -1,7 +1,7 @@
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#
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# @file
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#
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# @brief Makefile of LibBSP for the or1ksim BSP.
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# @brief Makefile of LibBSP for the generic_or1k BSP.
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#
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ACLOCAL_AMFLAGS = -I ../../../../aclocal
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@@ -32,7 +32,7 @@ include_bsp_HEADERS += ../../shared/include/uart-output-char.h
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include_bsp_HEADERS += ../shared/include/cache_.h
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include_bsp_HEADERS += include/irq.h
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include_bsp_HEADERS += include/uart.h
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include_bsp_HEADERS += include/or1ksim.h
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include_bsp_HEADERS += include/generic_or1k.h
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nodist_include_HEADERS = ../../shared/include/coverhd.h \
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include/bspopts.h
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@@ -1,5 +1,4 @@
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This BSP should run on or1ksim: the main simulator for or1k architecture.
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or1ksim should be used for testing purposes. It also runs on QEMU.
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This BSP can run on or1ksim, QEMU, jor1k [1] and OpenRISC supported FPGA boards.
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$ git clone git@github.com:openrisc/or1ksim.git
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$ cd or1ksim
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@@ -20,10 +19,6 @@ rtems-tools/sim-scripts.
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From command line type:
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$ sim -f sim.cfg $PATH_TO_RTEMS_EXE (old or1ksim releases)
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or (if you use a stable/gitgub or1ksim release)
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$ or1k-elf-sim -f sim.cfg $PATH_TO_RTEMS_EXE
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From QEMU:
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@@ -35,3 +30,5 @@ from sim-scripts:
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$ or1ksim $PATH_TO_RTEMS_EXE
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$ qemu-or1k $PATH_TO_RTEMS_EXE
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[1] http://s-macke.github.io/jor1k/demos/rtems.html
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@@ -3,13 +3,13 @@
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*
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* @ingroup bsp_clock
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*
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* @brief or1ksim clock support.
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* @brief or1k clock support.
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*/
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/*
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* or1ksim Clock driver
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* generic_or1k Clock driver
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*
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* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
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* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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@@ -19,13 +19,13 @@
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#include <rtems.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/or1ksim.h>
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#include <bsp/generic_or1k.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/or1k-utility.h>
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/* The number of clock cycles before generating a tick timer interrupt. */
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#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 0x09ED9
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#define OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS 10
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#define OR1K_CLOCK_CYCLE_TIME_NANOSECONDS 10
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/* CPU counter */
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static CPU_Counter_ticks cpu_counter_ticks;
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@@ -33,7 +33,7 @@ static CPU_Counter_ticks cpu_counter_ticks;
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/* This prototype is added here to Avoid warnings */
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void Clock_isr(void *arg);
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static void or1ksim_clock_at_tick(void)
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static void generic_or1k_clock_at_tick(void)
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{
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uint32_t TTMR;
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@@ -53,7 +53,10 @@ static void or1ksim_clock_at_tick(void)
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cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT;
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}
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static void or1ksim_clock_handler_install(proc_ptr new_isr, proc_ptr old_isr)
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static void generic_or1k_clock_handler_install(
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proc_ptr new_isr,
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proc_ptr old_isr
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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old_isr = NULL;
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@@ -66,7 +69,7 @@ static void or1ksim_clock_handler_install(proc_ptr new_isr, proc_ptr old_isr)
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}
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}
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static void or1ksim_clock_initialize(void)
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static void generic_or1k_clock_initialize(void)
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{
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uint32_t TTMR;
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@@ -91,7 +94,7 @@ static void or1ksim_clock_initialize(void)
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cpu_counter_ticks = 0;
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}
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static void or1ksim_clock_cleanup(void)
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static void generic_or1k_clock_cleanup(void)
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{
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uint32_t sr;
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@@ -109,10 +112,10 @@ static void or1ksim_clock_initialize(void)
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/*
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* Return the nanoseconds since last tick
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*/
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static uint32_t or1ksim_clock_nanoseconds_since_last_tick(void)
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static uint32_t generic_or1k_clock_nanoseconds_since_last_tick(void)
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{
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return
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TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * OR1KSIM_CLOCK_CYCLE_TIME_NANOSECONDS;
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TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * OR1K_CLOCK_CYCLE_TIME_NANOSECONDS;
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}
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CPU_Counter_ticks _CPU_Counter_read(void)
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@@ -131,19 +134,19 @@ CPU_Counter_ticks _CPU_Counter_difference(
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{
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return second - first;
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}
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#define Clock_driver_support_at_tick() or1ksim_clock_at_tick()
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#define Clock_driver_support_at_tick() generic_or1k_clock_at_tick()
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#define Clock_driver_support_initialize_hardware() or1ksim_clock_initialize()
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#define Clock_driver_support_initialize_hardware() generic_or1k_clock_initialize()
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#define Clock_driver_support_install_isr(isr, old_isr) \
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do { \
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old_isr = NULL; \
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or1ksim_clock_handler_install(isr, old_isr); \
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generic_or1k_clock_handler_install(isr, old_isr); \
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} while (0)
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#define Clock_driver_support_shutdown_hardware() or1ksim_clock_cleanup()
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#define Clock_driver_support_shutdown_hardware() generic_or1k_clock_cleanup()
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#define Clock_driver_nanoseconds_since_last_tick \
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or1ksim_clock_nanoseconds_since_last_tick
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generic_or1k_clock_nanoseconds_since_last_tick
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#include "../../../shared/clockdrv_shell.h"
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@@ -1,11 +1,11 @@
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#
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# @file
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#
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# @brief Configure script of LibBSP for or1ksim BSP.
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# @brief Configure script of LibBSP for generic_or1k BSP.
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#
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AC_PREREQ(2.69)
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AC_INIT([rtems-c-src-lib-libbsp-or1k-or1ksim],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
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AC_INIT([rtems-c-src-lib-libbsp-or1k-generic],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
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AC_CONFIG_SRCDIR([bsp_specs])
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RTEMS_TOP(../../../../../..)
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@@ -16,8 +16,8 @@ RTEMS_BSP_CONFIGURE
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RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
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RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
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RTEMS_BSPOPTS_SET([BSP_OR1K_OR1KSIM_PERIPHCLK],[*],[50000000U])
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RTEMS_BSPOPTS_HELP([BSP_OR1K_OR1KSIM_PERIPHCLK],[or1ksim PERIPHCLK clock frequency in Hz])
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RTEMS_BSPOPTS_SET([BSP_GENERIC_OR1K_PERIPHCLK],[*],[50000000U])
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RTEMS_BSPOPTS_HELP([BSP_GENERIC_OR1K_PERIPHCLK],[or1k PERIPHCLK clock frequency in Hz])
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RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
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RTEMS_CANONICALIZE_TOOLS
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@@ -1,13 +1,13 @@
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/**
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* @file
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*
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* @ingroup or1ksim_uart
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* @ingroup generic_or1k_uart
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*
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* @brief Console Configuration.
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*/
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/*
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* Copyright (c) 2014 Hesham ALMatary
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* Copyright (c) 2014-2015 Hesham ALMatary
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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@@ -20,19 +20,19 @@
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#include <bspopts.h>
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#include <bsp/uart.h>
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#include <bsp/or1ksim.h>
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#include <bsp/generic_or1k.h>
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console_tbl Console_Configuration_Ports [] = {
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{
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.sDeviceName = "/dev/ttyS0",
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.deviceType = SERIAL_CUSTOM,
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.pDeviceFns = &or1ksim_uart_fns,
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.pDeviceFns = &generic_or1k_uart_fns,
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.deviceProbe = NULL,
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.pDeviceFlow = NULL,
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.ulCtrlPort1 = OR1KSIM_BSP_UART_BASE,
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.ulCtrlPort1 = OR1K_BSP_UART_BASE,
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.ulCtrlPort2 = 0,
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.ulClock = OR1KSIM_UART_DEFAULT_BAUD,
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.ulIntVector = OR1KSIM_BSP_UART_IRQ
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.ulClock = OR1K_UART_DEFAULT_BAUD,
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.ulIntVector = OR1K_BSP_UART_IRQ
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}
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};
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@@ -1,13 +1,13 @@
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/**
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* @file
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*
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* @ingroup or1ksim_uart
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* @ingroup generic_or1k_uart
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*
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* @brief UART support.
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*/
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/*
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* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
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* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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@@ -15,7 +15,7 @@
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*/
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#include <libchip/sersupp.h>
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#include <bsp/or1ksim.h>
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#include <bsp/generic_or1k.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/uart.h>
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@@ -46,33 +46,33 @@ static uint32_t uart_get_baud(const console_tbl *ct)
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static void uart_set_baud(int baud)
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{
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uint16_t divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud);
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) =
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OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB;
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uint16_t divisor = (OR1K_BSP_CLOCK_FREQ) / (16 * baud);
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OR1K_REG(OR1K_BSP_UART_REG_LINE_CTRL) =
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OR1K_BSP_UART_REG_LINE_CTRL_DLAB;
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff;
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OR1K_REG(OR1K_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff;
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH) =
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OR1K_REG(OR1K_BSP_UART_REG_DEV_LATCH_HIGH) =
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(divisor >> 8);
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}
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static void uart_initialize(int minor)
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{
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/* Set baud rate */
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uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD);
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uart_set_baud(OR1K_UART_DEFAULT_BAUD);
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/* Set data pattern configuration */
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) =
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OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8;
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OR1K_REG(OR1K_BSP_UART_REG_LINE_CTRL) =
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OR1K_BSP_UART_REG_LINE_CTRL_WLEN8;
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/* Reset receiver and transmitter */
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_FIFO_CTRL) =
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OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO |
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OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR |
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OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14;
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OR1K_REG(OR1K_BSP_UART_REG_FIFO_CTRL) =
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OR1K_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO |
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OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR |
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OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_14;
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/* Disable all interrupts */
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00;
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OR1K_REG(OR1K_BSP_UART_REG_INT_ENABLE) = 0x00;
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}
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@@ -100,11 +100,11 @@ static int uart_read_polled(int minor)
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/* Get a character when avaiable */
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do {
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lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS);
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} while ((lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_DR)
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!= OR1KSIM_BSP_UART_REG_LINE_STATUS_DR);
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lsr = OR1K_REG(OR1K_BSP_UART_REG_LINE_STATUS);
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} while ((lsr & OR1K_BSP_UART_REG_LINE_STATUS_DR)
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!= OR1K_BSP_UART_REG_LINE_STATUS_DR);
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return OR1KSIM_REG(OR1KSIM_BSP_UART_REG_RX);
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return OR1K_REG(OR1K_BSP_UART_REG_RX);
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}
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static void uart_write_polled(int minor, char c)
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@@ -113,10 +113,10 @@ static void uart_write_polled(int minor, char c)
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/* Wait until there is no pending data in the transmitter FIFO (empty) */
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do {
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lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS);
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} while (!(lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE));
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lsr = OR1K_REG(OR1K_BSP_UART_REG_LINE_STATUS);
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} while (!(lsr & OR1K_BSP_UART_REG_LINE_STATUS_THRE));
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OR1KSIM_REG(OR1KSIM_BSP_UART_REG_TX) = c;
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OR1K_REG(OR1K_BSP_UART_REG_TX) = c;
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}
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static ssize_t uart_write(
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@@ -139,7 +139,7 @@ static int uart_set_attributes(int minor, const struct termios *term)
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return -1;
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}
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const console_fns or1ksim_uart_fns = {
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const console_fns generic_or1k_uart_fns = {
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.deviceProbe = libchip_serial_default_probe,
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.deviceFirstOpen = uart_first_open,
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.deviceLastClose = uart_last_close,
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@@ -1,27 +1,27 @@
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/**
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* @file
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*
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* @ingroup or1k_or1ksim
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* @ingroup generic_or1k
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*
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* @brief Global BSP definitions.
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*/
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/*
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* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
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* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
|
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*
|
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* The license and distribution terms for this file may be
|
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE
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*/
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#ifndef LIBBSP_OR1K_OR1KSIM_H
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#define LIBBSP_OR1K_OR1KSIM_H
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#ifndef LIBBSP_GENERIC_OR1K_H
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#define LIBBSP_GENERIC_OR1K_H
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#include <bspopts.h>
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#include <rtems.h>
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#include <rtems/console.h>
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#include <rtems/clockdrv.h>
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#include <bsp/or1ksim.h>
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#include <bsp/generic_or1k.h>
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#include <bsp/default-initial-extension.h>
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@@ -35,13 +35,13 @@ extern "C" {
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_OR1K_OR1KSIM_H */
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#endif /* LIBBSP_GENERIC_OR1K_H */
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/**
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* @defgroup or1k_or1ksim support
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* @defgroup generic_or1k support
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*
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* @ingroup bsp_or1k
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*
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* @brief or1ksim support package
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* @brief generic_or1k support package
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*
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*/
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118
c/src/lib/libbsp/or1k/generic_or1k/include/generic_or1k.h
Normal file
118
c/src/lib/libbsp/or1k/generic_or1k/include/generic_or1k.h
Normal file
@@ -0,0 +1,118 @@
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/**
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* @file
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*
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* @ingroup generic_or1k_reg
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*
|
||||
* @brief Register definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_GENERIC_OR1K_H
|
||||
#define LIBBSP_GENERIC_OR1K_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @defgroup generic_or1k_reg Register Definitions
|
||||
*
|
||||
* @ingroup generic_or1k
|
||||
*
|
||||
* @brief Shared register definitions for or1k systems.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @name Register Macros
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OR1K_REG(x) (*((volatile unsigned char *) (x)))
|
||||
#define OR1K_BIT(n) (1 << (n))
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal OR1K UART Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define OR1K_BSP_CLOCK_FREQ 50000000UL
|
||||
#define OR1K_BSP_UART_BASE 0x90000000
|
||||
|
||||
#define OR1K_BSP_UART_REG_TX (OR1K_BSP_UART_BASE+0)
|
||||
#define OR1K_BSP_UART_REG_RX (OR1K_BSP_UART_BASE+0)
|
||||
#define OR1K_BSP_UART_REG_DEV_LATCH_LOW (OR1K_BSP_UART_BASE+0)
|
||||
#define OR1K_BSP_UART_REG_DEV_LATCH_HIGH (OR1K_BSP_UART_BASE+1)
|
||||
#define OR1K_BSP_UART_REG_INT_ENABLE (OR1K_BSP_UART_BASE+1)
|
||||
#define OR1K_BSP_UART_REG_INT_ID (OR1K_BSP_UART_BASE+2)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL (OR1K_BSP_UART_BASE+2)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL (OR1K_BSP_UART_BASE+3)
|
||||
#define OR1K_BSP_UART_REG_MODEM_CTRL (OR1K_BSP_UART_BASE+4)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS (OR1K_BSP_UART_BASE+5)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS (OR1K_BSP_UART_BASE+6)
|
||||
#define OR1K_BSP_UART_REG_SCRATCH (OR1K_BSP_UART_BASE+7)
|
||||
|
||||
/* FIFO Control Register */
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_1 (0x00)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO (0x01)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR (0x02)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT (0x03)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_DMA_SELECT (0x08)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_4 (0x40)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_8 (0x80)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_14 (0xC0)
|
||||
#define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_MASK (0xC0)
|
||||
|
||||
/* Line Control Register */
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN5 (0x00)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN6 (0x01)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN7 (0x02)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_WLEN8 (0x03)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_STOP (0x04)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_PARITY (0x08)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_EPAR (0x10)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_SPAR (0x20)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_SBC (0x40)
|
||||
#define OR1K_BSP_UART_REG_LINE_CTRL_DLAB (0x80)
|
||||
|
||||
/* Line Status Register */
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_DR (0x01)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_OE (0x02)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_PE (0x04)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_FE (0x08)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_BI (0x10)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_THRE (0x20)
|
||||
#define OR1K_BSP_UART_REG_LINE_STATUS_TEMT (0x40)
|
||||
|
||||
/* Modem Control Register */
|
||||
#define OR1K_BSP_UART_REG_MODEM_CTRL_DTR (0x01)
|
||||
#define OR1K_BSP_UART_REG_MODEM_CTRL_RTS (0x02)
|
||||
#define OR1K_BSP_UART_REG_MODEM_CTRL_OUT1 (0x04)
|
||||
#define OR1K_BSP_UART_REG_MODEM_CTRL_OUT2 (0x08)
|
||||
#define OR1K_BSP_UART_REG_MODEM_CTRL_LOOP (0x10)
|
||||
|
||||
/* Modem Status Register */
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_DCTS (0x01)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_DDSR (0x02)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_TERI (0x04)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_DDCD (0x08)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_CTS (0x10)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_DSR (0x20)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_RI (0x40)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_DCD (0x80)
|
||||
#define OR1K_BSP_UART_REG_MODEM_STATUS_ANY_DELTA (0x0F)
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_GENERIC_OR1K_H */
|
||||
45
c/src/lib/libbsp/or1k/generic_or1k/include/irq.h
Normal file
45
c/src/lib/libbsp/or1k/generic_or1k/include/irq.h
Normal file
@@ -0,0 +1,45 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup OR1K_IRQ
|
||||
*
|
||||
* @brief Interrupt definitions.
|
||||
*/
|
||||
|
||||
/**
|
||||
* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_GENERIC_OR1K_IRQ_H
|
||||
#define LIBBSP_GENERIC_OR1K_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_MIN 0x100
|
||||
#define BSP_INTERRUPT_VECTOR_MAX 0x1F00
|
||||
|
||||
/* Interrupt Identification Register */
|
||||
#define OR1K_BSP_UART_REG_INT_ID_MSI (0x00)
|
||||
#define OR1K_BSP_UART_REG_INT_ID_NO_INT (0x01)
|
||||
#define OR1K_BSP_UART_REG_INT_ID_THRI (0x02)
|
||||
#define OR1K_BSP_UART_REG_INT_ID_RDI (0x04)
|
||||
#define OR1K_BSP_UART_REG_INT_ID_ID (0x06)
|
||||
#define OR1K_BSP_UART_REG_INT_ID_RLSI (0x06)
|
||||
#define OR1K_BSP_UART_REG_INT_ID_TOI (0x0c)
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
#define OR1K_BSP_UART_REG_INT_ENABLE_RDI (0x01)
|
||||
#define OR1K_BSP_UART_REG_INT_ENABLE_THRI (0x02)
|
||||
#define OR1K_BSP_UART_REG_INT_ENABLE_RLSI (0x04)
|
||||
#define OR1K_BSP_UART_REG_INT_ENABLE_MSI (0x08)
|
||||
|
||||
#endif /* ASM */
|
||||
#endif /* LIBBSP_GENEIRC_OR1K_IRQ_H */
|
||||
@@ -1,13 +1,13 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup or1ksim_uart
|
||||
* @ingroup generic_or1k_uart
|
||||
*
|
||||
* @brief UART support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
* COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
@@ -15,15 +15,15 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup or1ksim_uart UART Support
|
||||
* @defgroup generic_or1k_uart UART Support
|
||||
*
|
||||
* @ingroup or1k_or1ksim
|
||||
* @ingroup generic_or1k
|
||||
*
|
||||
* @brief Universal Asynchronous Receiver/Transmitter (UART) Support
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_OR1K_OR1KSIM_UART_H
|
||||
#define LIBBSP_OR1K_OR1KSIM_UART_H
|
||||
#ifndef LIBBSP_GENERIC_OR1K_UART_H
|
||||
#define LIBBSP_GENERIC_OR1K_UART_H
|
||||
|
||||
#include <libchip/serial.h>
|
||||
|
||||
@@ -31,12 +31,12 @@
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define OR1KSIM_UART_DEFAULT_BAUD 115200
|
||||
#define OR1KSIM_BSP_UART_IRQ 13
|
||||
extern const console_fns or1ksim_uart_fns;
|
||||
#define OR1K_UART_DEFAULT_BAUD 115200
|
||||
#define OR1K_BSP_UART_IRQ 2
|
||||
extern const console_fns generic_or1k_uart_fns;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_OR1K_OR1KSIM_UART_H */
|
||||
#endif /* LIBBSP_GENERIC_OR1K_UART_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
#
|
||||
# or1ksim RTEMS Test Database.
|
||||
# generic_or1k RTEMS Test Database.
|
||||
#
|
||||
|
||||
include: testdata/disable-intrcritical-tests.tcfg
|
||||
@@ -94,9 +94,9 @@ $(PROJECT_INCLUDE)/bsp/uart.h: include/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/or1ksim.h: include/or1ksim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/or1ksim.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/or1ksim.h
|
||||
$(PROJECT_INCLUDE)/bsp/generic_or1k.h: include/generic_or1k.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/generic_or1k.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/generic_or1k.h
|
||||
|
||||
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
* Copyright (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
@@ -1,13 +1,13 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup or1ksim
|
||||
* @ingroup generic_or1k
|
||||
*
|
||||
* @brief Benchmark timer support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 by Hesham ALMatary
|
||||
* Copyright (c) 2014-2015 by Hesham ALMatary
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
@@ -1,13 +1,13 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup or1ksim
|
||||
* @ingroup generic_or1k
|
||||
*
|
||||
* @brief Benchmark timer support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 by Hesham ALMatary
|
||||
* Copyright (c) 2014-2015 by Hesham ALMatary
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
@@ -16,10 +16,10 @@
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/btimer.h>
|
||||
#include <bsp/or1ksim.h>
|
||||
#include <bsp/generic_or1k.h>
|
||||
#include <rtems/score/or1k-utility.h>
|
||||
|
||||
#define OR1KSIM_NANOSECONDS_PER_CLK_CYCLE 10
|
||||
#define OR1K_NANOSECONDS_PER_CLK_CYCLE 10
|
||||
|
||||
static bool benchmark_timer_find_average_overhead = false;
|
||||
static uint64_t benchmark_timer_base;
|
||||
@@ -46,7 +46,7 @@ benchmark_timer_t benchmark_timer_read( void )
|
||||
delta = clicks - benchmark_timer_base;
|
||||
|
||||
/* total in nanoseconds */
|
||||
total = OR1KSIM_NANOSECONDS_PER_CLK_CYCLE * (delta);
|
||||
total = OR1K_NANOSECONDS_PER_CLK_CYCLE * (delta);
|
||||
|
||||
if ( benchmark_timer_find_average_overhead == true )
|
||||
return total; /* in nanoseconds microsecond units */
|
||||
@@ -1,45 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup or1ksim_interrupt
|
||||
*
|
||||
* @brief Interrupt definitions.
|
||||
*/
|
||||
|
||||
/**
|
||||
* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_OR1K_OR1KSIM_IRQ_H
|
||||
#define LIBBSP_OR1K_OR1KSIM_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_MIN 0x100
|
||||
#define BSP_INTERRUPT_VECTOR_MAX 0x1F00
|
||||
|
||||
/* Interrupt Identification Register */
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_MSI (0x00)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_NO_INT (0x01)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_THRI (0x02)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_RDI (0x04)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_ID (0x06)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_RLSI (0x06)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID_TOI (0x0c)
|
||||
|
||||
/* Interrupt Enable Register */
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ENABLE_RDI (0x01)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ENABLE_THRI (0x02)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ENABLE_RLSI (0x04)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ENABLE_MSI (0x08)
|
||||
|
||||
#endif /* ASM */
|
||||
#endif /* LIBBSP_OR1K_OR1KSIM_IRQ_H */
|
||||
@@ -1,118 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup or1ksim_reg
|
||||
*
|
||||
* @brief Register definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_OR1K_OR1KSIM_H
|
||||
#define LIBBSP_OR1K_OR1KSIM_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @defgroup or1ksim_reg Register Definitions
|
||||
*
|
||||
* @ingroup or1k_or1ksim
|
||||
*
|
||||
* @brief Register Definitions
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @name Register Macros
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OR1KSIM_REG(x) (*((volatile unsigned char *) (x)))
|
||||
#define OR1KSIM_BIT(n) (1 << (n))
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal OR1K UART Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define OR1KSIM_BSP_CLOCK_FREQ 50000000UL
|
||||
#define OR1KSIM_BSP_UART_BASE 0x90000000
|
||||
|
||||
#define OR1KSIM_BSP_UART_REG_TX (OR1KSIM_BSP_UART_BASE+0)
|
||||
#define OR1KSIM_BSP_UART_REG_RX (OR1KSIM_BSP_UART_BASE+0)
|
||||
#define OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW (OR1KSIM_BSP_UART_BASE+0)
|
||||
#define OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH (OR1KSIM_BSP_UART_BASE+1)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ENABLE (OR1KSIM_BSP_UART_BASE+1)
|
||||
#define OR1KSIM_BSP_UART_REG_INT_ID (OR1KSIM_BSP_UART_BASE+2)
|
||||
#define OR1KSIM_BSP_UART_REG_FIFO_CTRL (OR1KSIM_BSP_UART_BASE+2)
|
||||
#define OR1KSIM_BSP_UART_REG_LINE_CTRL (OR1KSIM_BSP_UART_BASE+3)
|
||||
#define OR1KSIM_BSP_UART_REG_MODEM_CTRL (OR1KSIM_BSP_UART_BASE+4)
|
||||
#define OR1KSIM_BSP_UART_REG_LINE_STATUS (OR1KSIM_BSP_UART_BASE+5)
|
||||
#define OR1KSIM_BSP_UART_REG_MODEM_STATUS (OR1KSIM_BSP_UART_BASE+6)
|
||||
#define OR1KSIM_BSP_UART_REG_SCRATCH (OR1KSIM_BSP_UART_BASE+7)
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/* FIFO Control Register */
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_1 (0x00)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO (0x01)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR (0x02)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT (0x03)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_DMA_SELECT (0x08)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_4 (0x40)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_8 (0x80)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14 (0xC0)
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#define OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_MASK (0xC0)
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/* Line Control Register */
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN5 (0x00)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN6 (0x01)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN7 (0x02)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 (0x03)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP (0x04)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY (0x08)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_EPAR (0x10)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_SPAR (0x20)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_SBC (0x40)
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#define OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB (0x80)
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|
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/* Line Status Register */
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_DR (0x01)
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_OE (0x02)
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_PE (0x04)
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_FE (0x08)
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_BI (0x10)
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE (0x20)
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#define OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT (0x40)
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|
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/* Modem Control Register */
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#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_DTR (0x01)
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#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_RTS (0x02)
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#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_OUT1 (0x04)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_OUT2 (0x08)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_CTRL_LOOP (0x10)
|
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|
||||
/* Modem Status Register */
|
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#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DCTS (0x01)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DDSR (0x02)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_TERI (0x04)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DDCD (0x08)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_CTS (0x10)
|
||||
#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DSR (0x20)
|
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#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_RI (0x40)
|
||||
#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_DCD (0x80)
|
||||
#define OR1KSIM_BSP_UART_REG_MODEM_STATUS_ANY_DELTA (0x0F)
|
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|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_OR1K_OR1KSIM_H */
|
||||
Reference in New Issue
Block a user