forked from Imagelibrary/rtems
libcpu/powerpc/e500/mmu/mmu.c: Fix warnings
This commit is contained in:
Joel Sherrill
@@ -22,13 +22,13 @@
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* ----------
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* This software was created by
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* Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
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* Stanford Linear Accelerator Center, Stanford University.
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* Stanford Linear Accelerator Center, Stanford University.
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*
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* Acknowledgement of sponsorship
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* ------------------------------
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* This software was produced by
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* the Stanford Linear Accelerator Center, Stanford University,
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* under Contract DE-AC03-76SFO0515 with the Department of Energy.
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* under Contract DE-AC03-76SFO0515 with the Department of Energy.
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*
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* Government disclaimer of liability
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* ----------------------------------
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@@ -76,13 +76,13 @@
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#include "e500_mmu.h"
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#define TLBIVAX_TLBSEL (1<<(63-60))
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#define TLBIVAX_INV_ALL (1<<(63-61))
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#define TLBIVAX_TLBSEL (1<<(63-60))
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#define TLBIVAX_INV_ALL (1<<(63-61))
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#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */
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#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */
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#define E500_TLB_ATTR_WIMGE_GET(x) ((x)&0x7f)
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#define E500_TLB_ATTR_TS (1<<7)
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#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8)
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#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8)
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#define E500_TLB_ATTR_PERM_GET(x) (((x)>>8)&0x3ff)
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#define E500_TLB_ATTR_TID(x) (((x)&0xfff)<<20)
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#define E500_TLB_ATTR_TID_GET(x) (((x)>>20)&0xfff)
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@@ -95,11 +95,11 @@
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#endif
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/* Factory to generate inline macros for accessing the MAS registers */
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#define __RDWRMAS(mas,rmas) \
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static inline uint32_t _read_MAS##mas(void) \
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{ uint32_t x; __asm__ volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
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static inline void _write_MAS##mas(uint32_t x) \
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{ __asm__ volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
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#define __RDWRMAS(mas,rmas) \
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static inline uint32_t _read_MAS##mas(void) \
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{ uint32_t x; __asm__ volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
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static inline void _write_MAS##mas(uint32_t x) \
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{ __asm__ volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
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__RDWRMAS(0,FSL_EIS_MAS0)
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__RDWRMAS(1,FSL_EIS_MAS1)
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@@ -121,19 +121,19 @@ E500_tlb_va_cache_t rtems_e500_tlb_va_cache[16];
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static void
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myprintf(FILE *f, char *fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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va_list ap;
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va_start(ap, fmt);
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if (!f || !_impure_ptr->__sdidinit) {
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/*
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* Might be called at an early stage when
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* stdio is not yet initialized.
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*/
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vprintk(fmt,ap);
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} else {
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vfprintf(f,fmt,ap);
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}
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va_end(ap);
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if (!f || !_impure_ptr->__sdidinit) {
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/*
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* Might be called at an early stage when
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* stdio is not yet initialized.
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*/
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vprintk(fmt,ap);
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} else {
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vfprintf(f,fmt,ap);
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}
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va_end(ap);
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}
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@@ -141,38 +141,38 @@ void
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rtems_e500_dmptlbc(FILE *f)
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{
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int i;
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if ( !initialized ) {
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myprintf(stderr,"TLB cache not initialized\n");
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return;
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}
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for ( i=0; i<16; i++ ) {
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if ( !rtems_e500_tlb_va_cache[i].att.v )
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continue;
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myprintf(f,"#%2i: TID 0x%03x, TS %i, ea 0x%08x .. 0x%08x\n",
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i,
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rtems_e500_tlb_va_cache[i].va.va_tid,
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rtems_e500_tlb_va_cache[i].att.ts,
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rtems_e500_tlb_va_cache[i].va.va_epn<<12,
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(rtems_e500_tlb_va_cache[i].va.va_epn<<12) + (1024<<(2*rtems_e500_tlb_va_cache[i].att.sz))-1);
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myprintf(f,"PA 0x%08"PRIx32", PERM 0x%03x, WIMGE 0x%02x\n",
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rtems_e500_tlb_va_cache[i].rpn<<12,
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rtems_e500_tlb_va_cache[i].att.perm,
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rtems_e500_tlb_va_cache[i].att.wimge);
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}
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if ( !initialized ) {
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myprintf(stderr,"TLB cache not initialized\n");
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return;
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}
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for ( i=0; i<16; i++ ) {
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if ( !rtems_e500_tlb_va_cache[i].att.v )
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continue;
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myprintf(f,"#%2i: TID 0x%03x, TS %i, ea 0x%08x .. 0x%08x\n",
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i,
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rtems_e500_tlb_va_cache[i].va.va_tid,
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rtems_e500_tlb_va_cache[i].att.ts,
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rtems_e500_tlb_va_cache[i].va.va_epn<<12,
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(rtems_e500_tlb_va_cache[i].va.va_epn<<12) + (1024<<(2*rtems_e500_tlb_va_cache[i].att.sz))-1);
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myprintf(f,"PA 0x%08"PRIx32", PERM 0x%03x, WIMGE 0x%02x\n",
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rtems_e500_tlb_va_cache[i].rpn<<12,
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rtems_e500_tlb_va_cache[i].att.perm,
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rtems_e500_tlb_va_cache[i].att.wimge);
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}
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}
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#define E500_SELTLB_1 0x1000
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#define E500_SELTLB_1 0x1000
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static void seltlb(rtems_e500_tlb_idx key)
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{
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int idx = key & ~E500_SELTLB_1;
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if ( key & E500_SELTLB_1 ) {
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_write_MAS0( FSL_EIS_MAS0_TLBSEL | FSL_EIS_MAS0_ESEL(idx) );
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} else {
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_write_MAS0( (idx & 128) ? FSL_EIS_MAS0_ESEL(1) : FSL_EIS_MAS0_ESEL(0) );
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_write_MAS2( FSL_EIS_MAS2_EPN( idx & 127 ) );
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}
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if ( key & E500_SELTLB_1 ) {
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_write_MAS0( FSL_EIS_MAS0_TLBSEL | FSL_EIS_MAS0_ESEL(idx) );
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} else {
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_write_MAS0( (idx & 128) ? FSL_EIS_MAS0_ESEL(1) : FSL_EIS_MAS0_ESEL(0) );
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_write_MAS2( FSL_EIS_MAS2_EPN( idx & 127 ) );
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}
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}
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/*
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@@ -199,84 +199,84 @@ int idx = key & ~E500_SELTLB_1;
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int
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rtems_e500_prtlb(rtems_e500_tlb_idx key, int quiet, FILE *f)
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{
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uint32_t mas0, mas1, mas2, mas3;
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rtems_interrupt_level lvl;
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E500_tlb_va_cache_t *tlb;
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E500_tlb_va_cache_t buf;
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int sel, idx;
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uint32_t mas1, mas2, mas3;
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rtems_interrupt_level lvl;
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E500_tlb_va_cache_t *tlb;
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E500_tlb_va_cache_t buf;
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int sel, idx;
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sel = (key & E500_SELTLB_1) ? 1 : 0;
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idx = key & ~E500_SELTLB_1;
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sel = (key & E500_SELTLB_1) ? 1 : 0;
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idx = key & ~E500_SELTLB_1;
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if ( idx < 0 || idx > 255 || ( idx > 15 && sel ) )
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return -1;
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if ( idx < 0 || idx > 255 || ( idx > 15 && sel ) )
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return -1;
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rtems_interrupt_disable(lvl);
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rtems_interrupt_disable(lvl);
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seltlb( key );
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seltlb( key );
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asm volatile("tlbre");
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asm volatile("tlbre");
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mas0 = _read_MAS0();
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mas1 = _read_MAS1();
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mas2 = _read_MAS2();
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mas3 = _read_MAS3();
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/* not manipulating MAS0, skip reading it */
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mas1 = _read_MAS1();
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mas2 = _read_MAS2();
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mas3 = _read_MAS3();
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rtems_interrupt_enable(lvl);
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rtems_interrupt_enable(lvl);
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tlb = sel ? rtems_e500_tlb_va_cache + idx : &buf;
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tlb = sel ? rtems_e500_tlb_va_cache + idx : &buf;
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if ( (tlb->att.v = (FSL_EIS_MAS1_V & mas1) ? 1 : 0) ) {
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tlb->va.va_epn = FSL_EIS_MAS2_EPN_GET(mas2);
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tlb->rpn = FSL_EIS_MAS3_RPN_GET(mas3);
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tlb->va.va_tid = FSL_EIS_MAS1_TID_GET(mas1);
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tlb->att.ts = (FSL_EIS_MAS1_TS & mas1) ? 1 : 0;
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tlb->att.sz = sel ? FSL_EIS_MAS1_TSIZE_GET(mas1) : 1 /* 4k size */;
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tlb->att.wimge = FSL_EIS_MAS2_ATTR_GET(mas2);
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tlb->att.perm = FSL_EIS_MAS3_PERM_GET(mas3);
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}
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if ( (tlb->att.v = (FSL_EIS_MAS1_V & mas1) ? 1 : 0) ) {
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tlb->va.va_epn = FSL_EIS_MAS2_EPN_GET(mas2);
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tlb->rpn = FSL_EIS_MAS3_RPN_GET(mas3);
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tlb->va.va_tid = FSL_EIS_MAS1_TID_GET(mas1);
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tlb->att.ts = (FSL_EIS_MAS1_TS & mas1) ? 1 : 0;
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tlb->att.sz = sel ? FSL_EIS_MAS1_TSIZE_GET(mas1) : 1 /* 4k size */;
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tlb->att.wimge = FSL_EIS_MAS2_ATTR_GET(mas2);
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tlb->att.perm = FSL_EIS_MAS3_PERM_GET(mas3);
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}
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if ( tlb->att.v ) {
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if ( !quiet ) {
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if ( tlb->att.v ) {
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if ( !quiet ) {
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/*
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"TLB[1] Entry # 0 spans EA range 0x00000000 .. 0x00000000
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"Mapping: VA [TS 0/TID 0x00/EPN 0x00000] -> RPN 0x00000"
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"Size: TSIZE 0x0 ( 4^ts KiB = 000000 KiB = 0x00000000 B)
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"Attributes: PERM 0x000 (ux/sx/uw/sw/ur/sr) WIMGE 0x00 IPROT 0"
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"TLB[1] Entry # 0 spans EA range 0x00000000 .. 0x00000000
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"Mapping: VA [TS 0/TID 0x00/EPN 0x00000] -> RPN 0x00000"
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"Size: TSIZE 0x0 ( 4^ts KiB = 000000 KiB = 0x00000000 B)
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"Attributes: PERM 0x000 (ux/sx/uw/sw/ur/sr) WIMGE 0x00 IPROT 0"
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*/
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myprintf(f,
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"TLB[%i] Entry # %d spans EA range 0x%08x .. 0x%08x\r\n",
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sel,
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idx,
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(tlb->va.va_epn << 12),
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(tlb->va.va_epn << 12) + (1024<<(2*tlb->att.sz)) - 1
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);
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myprintf(f,
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"TLB[%i] Entry # %d spans EA range 0x%08x .. 0x%08x\r\n",
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sel,
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idx,
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(tlb->va.va_epn << 12),
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(tlb->va.va_epn << 12) + (1024<<(2*tlb->att.sz)) - 1
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);
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myprintf(f,
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"Mapping: VA [TS %d/TID 0x%02x/EPN 0x%05x] -> RPN 0x%05"PRIx32"\r\n",
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tlb->att.ts, tlb->va.va_tid, tlb->va.va_epn, tlb->rpn
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);
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myprintf(f,
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"Size: TSIZE 0x%x ( 4^ts KiB = %6d KiB = 0x%08x B)\r\n",
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tlb->att.sz, (1<<(2*tlb->att.sz)), (1024<<(2*tlb->att.sz))
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);
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myprintf(f,
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"Attributes: PERM 0x%03x (ux/sx/uw/sw/ur/sr) WIMGE 0x%02x IPROT %i\r\n",
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tlb->att.perm, tlb->att.wimge, (sel && (mas1 & FSL_EIS_MAS1_IPROT) ? 1 : 0)
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);
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myprintf(f,
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"EA range 0x%08x .. 0x%08x\r\n",
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(tlb->va.va_epn << 12),
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(tlb->va.va_epn << 12) + (1024<<(2*tlb->att.sz)) - 1
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);
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}
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} else {
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if ( !quiet ) {
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myprintf(f, "TLB[%i] Entry #%i <OFF> (size 0x%x = 0x%xb)\n", sel, idx, tlb->att.sz, (1024<<(2*tlb->att.sz)));
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}
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return 1;
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}
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return 0;
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myprintf(f,
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"Mapping: VA [TS %d/TID 0x%02x/EPN 0x%05x] -> RPN 0x%05"PRIx32"\r\n",
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tlb->att.ts, tlb->va.va_tid, tlb->va.va_epn, tlb->rpn
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);
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myprintf(f,
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"Size: TSIZE 0x%x ( 4^ts KiB = %6d KiB = 0x%08x B)\r\n",
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tlb->att.sz, (1<<(2*tlb->att.sz)), (1024<<(2*tlb->att.sz))
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);
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myprintf(f,
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"Attributes: PERM 0x%03x (ux/sx/uw/sw/ur/sr) WIMGE 0x%02x IPROT %i\r\n",
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tlb->att.perm, tlb->att.wimge, (sel && (mas1 & FSL_EIS_MAS1_IPROT) ? 1 : 0)
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);
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myprintf(f,
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"EA range 0x%08x .. 0x%08x\r\n",
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(tlb->va.va_epn << 12),
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(tlb->va.va_epn << 12) + (1024<<(2*tlb->att.sz)) - 1
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);
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}
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} else {
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if ( !quiet ) {
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myprintf(f, "TLB[%i] Entry #%i <OFF> (size 0x%x = 0x%xb)\n", sel, idx, tlb->att.sz, (1024<<(2*tlb->att.sz)));
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}
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return 1;
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}
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return 0;
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}
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/* Initialize cache; verify that TLB0 is unused;
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@@ -290,22 +290,22 @@ int rtems_e500_initlb()
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{
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int i;
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int rval = 0;
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for (i=0; i<16; i++)
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rtems_e500_prtlb(E500_SELTLB_1 | i, 1, 0);
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for (i=0; i<256; i++) {
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/* refuse to enable operations that change TLB entries
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for (i=0; i<16; i++)
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rtems_e500_prtlb(E500_SELTLB_1 | i, 1, 0);
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for (i=0; i<256; i++) {
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/* refuse to enable operations that change TLB entries
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* if anything in TLB[0] is valid (because we currently
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* don't check against overlap with TLB[0] when we
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* write a new entry).
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*/
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if ( rtems_e500_prtlb(E500_SELTLB_0 | i, 1, 0) <=0 ) {
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myprintf(stderr,"WARNING: 4k TLB #%i seems to be valid; UNSUPPORTED configuration\n", i);
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rval = -1;
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}
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}
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if ( !rval )
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initialized = 1;
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return rval;
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* don't check against overlap with TLB[0] when we
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* write a new entry).
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*/
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if ( rtems_e500_prtlb(E500_SELTLB_0 | i, 1, 0) <=0 ) {
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myprintf(stderr,"WARNING: 4k TLB #%i seems to be valid; UNSUPPORTED configuration\n", i);
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rval = -1;
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}
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}
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if ( !rval )
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initialized = 1;
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return rval;
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}
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/*
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@@ -343,10 +343,10 @@ int rval = 0;
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* <0: other error
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*
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*/
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#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */
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#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */
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#define E500_TLB_ATTR_WIMGE_GET(x) ((x)&0x7f)
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#define E500_TLB_ATTR_TS (1<<7)
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#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8)
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#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8)
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#define E500_TLB_ATTR_PERM_GET(x) (((x)>>8)&0x3ff)
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#define E500_TLB_ATTR_TID(x) (((x)&0xfff)<<20)
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#define E500_TLB_ATTR_TID_GET(x) (((x)>>20)&0xfff)
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@@ -359,94 +359,94 @@ uint32_t tid, msk;
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int lkup;
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rtems_interrupt_level lvl;
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if ( sz >= 1024 ) {
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/* Assume they literally specify a size */
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msk = sz;
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sz = 0;
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while ( msk != (1024<<(2*sz)) ) {
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if ( ++sz > 15 ) {
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return -1;
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}
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}
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/* OK, acceptable */
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}
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if ( sz >= 1024 ) {
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/* Assume they literally specify a size */
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msk = sz;
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sz = 0;
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||||
while ( msk != (1024<<(2*sz)) ) {
|
||||
if ( ++sz > 15 ) {
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return -1;
|
||||
}
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||||
}
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||||
/* OK, acceptable */
|
||||
}
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||||
|
||||
msk = sz > 0 ? (1024<<(2*sz)) - 1 : 0;
|
||||
msk = sz > 0 ? (1024<<(2*sz)) - 1 : 0;
|
||||
|
||||
if ( !initialized && sz > 0 ) {
|
||||
myprintf(stderr,"TLB driver not initialized; refuse to enable any entry\n");
|
||||
return -3;
|
||||
}
|
||||
if ( !initialized && sz > 0 ) {
|
||||
myprintf(stderr,"TLB driver not initialized; refuse to enable any entry\n");
|
||||
return -3;
|
||||
}
|
||||
|
||||
if ( (ea & msk) || (pa & msk) ) {
|
||||
myprintf(stderr,"Misaligned ea or pa\n");
|
||||
return -1;
|
||||
}
|
||||
if ( (ea & msk) || (pa & msk) ) {
|
||||
myprintf(stderr,"Misaligned ea or pa\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ( idx < 0 || idx > 15 )
|
||||
return -1;
|
||||
if ( idx < 0 || idx > 15 )
|
||||
return -1;
|
||||
|
||||
if ( sz > 15 ) {
|
||||
/* but e500v1 doesn't support all 16 sizes!! */
|
||||
/* FIXME: we should inquire about this CPU's
|
||||
* capabilities...
|
||||
*/
|
||||
return -1;
|
||||
}
|
||||
if ( sz > 15 ) {
|
||||
/* but e500v1 doesn't support all 16 sizes!! */
|
||||
/* FIXME: we should inquire about this CPU's
|
||||
* capabilities...
|
||||
*/
|
||||
return -1;
|
||||
}
|
||||
|
||||
tid = E500_TLB_ATTR_TID_GET(attr);
|
||||
tid = E500_TLB_ATTR_TID_GET(attr);
|
||||
|
||||
mas1 = (attr & E500_TLB_ATTR_TS) ? FSL_EIS_MAS1_TS : 0;
|
||||
mas1 = (attr & E500_TLB_ATTR_TS) ? FSL_EIS_MAS1_TS : 0;
|
||||
|
||||
if ( sz >=0 ) {
|
||||
lkup = rtems_e500_matchtlb(ea, tid, mas1, sz);
|
||||
if ( sz >=0 ) {
|
||||
lkup = rtems_e500_matchtlb(ea, tid, mas1, sz);
|
||||
|
||||
if ( lkup < -1 ) {
|
||||
/* some error */
|
||||
return lkup;
|
||||
}
|
||||
if ( lkup < -1 ) {
|
||||
/* some error */
|
||||
return lkup;
|
||||
}
|
||||
|
||||
if ( lkup >= 0 && lkup != idx ) {
|
||||
myprintf(stderr,"TLB[1] #%i overlaps with requested mapping\n", lkup);
|
||||
rtems_e500_prtlb( E500_SELTLB_1 | lkup, 0, stderr);
|
||||
return lkup+1;
|
||||
}
|
||||
}
|
||||
if ( lkup >= 0 && lkup != idx ) {
|
||||
myprintf(stderr,"TLB[1] #%i overlaps with requested mapping\n", lkup);
|
||||
rtems_e500_prtlb( E500_SELTLB_1 | lkup, 0, stderr);
|
||||
return lkup+1;
|
||||
}
|
||||
}
|
||||
|
||||
/* OK to proceed */
|
||||
mas1 |= FSL_EIS_MAS1_IPROT | FSL_EIS_MAS1_TID(tid);
|
||||
/* OK to proceed */
|
||||
mas1 |= FSL_EIS_MAS1_IPROT | FSL_EIS_MAS1_TID(tid);
|
||||
|
||||
if ( sz >= 0 )
|
||||
mas1 |= FSL_EIS_MAS1_V | FSL_EIS_MAS1_TSIZE(sz);
|
||||
if ( sz >= 0 )
|
||||
mas1 |= FSL_EIS_MAS1_V | FSL_EIS_MAS1_TSIZE(sz);
|
||||
|
||||
mas2 = FSL_EIS_MAS2_EPN( ea>>12 ) | E500_TLB_ATTR_WIMGE(attr);
|
||||
mas3 = FSL_EIS_MAS3_RPN( pa>>12 ) | E500_TLB_ATTR_PERM_GET(attr);
|
||||
/* mas4 is not really relevant; we don't use TLB replacement */
|
||||
mas4 = FSL_EIS_MAS4_TLBSELD | FSL_EIS_MAS4_TIDSELD(0) | FSL_EIS_MAS4_TSIZED(9) | FSL_EIS_MAS4_ID | FSL_EIS_MAS4_GD;
|
||||
mas2 = FSL_EIS_MAS2_EPN( ea>>12 ) | E500_TLB_ATTR_WIMGE(attr);
|
||||
mas3 = FSL_EIS_MAS3_RPN( pa>>12 ) | E500_TLB_ATTR_PERM_GET(attr);
|
||||
/* mas4 is not really relevant; we don't use TLB replacement */
|
||||
mas4 = FSL_EIS_MAS4_TLBSELD | FSL_EIS_MAS4_TIDSELD(0) | FSL_EIS_MAS4_TSIZED(9) | FSL_EIS_MAS4_ID | FSL_EIS_MAS4_GD;
|
||||
|
||||
rtems_interrupt_disable(lvl);
|
||||
rtems_interrupt_disable(lvl);
|
||||
|
||||
seltlb(idx | E500_SELTLB_1);
|
||||
seltlb(idx | E500_SELTLB_1);
|
||||
|
||||
_write_MAS1(mas1);
|
||||
_write_MAS2(mas2);
|
||||
_write_MAS3(mas3);
|
||||
_write_MAS4(mas4);
|
||||
_write_MAS1(mas1);
|
||||
_write_MAS2(mas2);
|
||||
_write_MAS3(mas3);
|
||||
_write_MAS4(mas4);
|
||||
|
||||
asm volatile(
|
||||
" sync \n"
|
||||
" isync \n"
|
||||
" tlbwe \n"
|
||||
" sync \n"
|
||||
" isync \n"
|
||||
);
|
||||
asm volatile(
|
||||
" sync\n"
|
||||
" isync\n"
|
||||
" tlbwe\n"
|
||||
" sync\n"
|
||||
" isync\n"
|
||||
);
|
||||
|
||||
rtems_interrupt_enable(lvl);
|
||||
rtems_interrupt_enable(lvl);
|
||||
|
||||
/* update cache */
|
||||
rtems_e500_prtlb( E500_SELTLB_1 | idx, 1, 0);
|
||||
/* update cache */
|
||||
rtems_e500_prtlb( E500_SELTLB_1 | idx, 1, 0);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -470,41 +470,41 @@ int i;
|
||||
uint32_t m,a;
|
||||
E500_tlb_va_cache_t *tlb;
|
||||
|
||||
if ( sz < 0 || sz > 15 )
|
||||
return -4;
|
||||
if ( sz < 0 || sz > 15 )
|
||||
return -4;
|
||||
|
||||
sz = (1024<<(2*sz));
|
||||
sz = (1024<<(2*sz));
|
||||
|
||||
if ( !initialized ) {
|
||||
/* cache not initialized */
|
||||
return -3;
|
||||
}
|
||||
if ( !initialized ) {
|
||||
/* cache not initialized */
|
||||
return -3;
|
||||
}
|
||||
|
||||
if ( ea & (sz-1) ) {
|
||||
/* misaligned ea */
|
||||
return -2;
|
||||
}
|
||||
if ( ea & (sz-1) ) {
|
||||
/* misaligned ea */
|
||||
return -2;
|
||||
}
|
||||
|
||||
if ( ts )
|
||||
ts = 1;
|
||||
if ( ts )
|
||||
ts = 1;
|
||||
|
||||
for ( i=0, tlb=rtems_e500_tlb_va_cache; i<16; i++, tlb++ ) {
|
||||
if ( ! tlb->att.v )
|
||||
continue;
|
||||
if ( tlb->att.ts != ts )
|
||||
continue;
|
||||
if ( tlb->va.va_tid && tlb->va.va_tid != tid )
|
||||
continue;
|
||||
/* TID and TS match a valid entry */
|
||||
m = (1024<<(2*tlb->att.sz)) - 1;
|
||||
/* calculate starting address of this entry */
|
||||
a = tlb->va.va_epn<<12;
|
||||
if ( ea <= a + m && ea + sz -1 >= a ) {
|
||||
/* overlap */
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
for ( i=0, tlb=rtems_e500_tlb_va_cache; i<16; i++, tlb++ ) {
|
||||
if ( ! tlb->att.v )
|
||||
continue;
|
||||
if ( tlb->att.ts != ts )
|
||||
continue;
|
||||
if ( tlb->va.va_tid && tlb->va.va_tid != tid )
|
||||
continue;
|
||||
/* TID and TS match a valid entry */
|
||||
m = (1024<<(2*tlb->att.sz)) - 1;
|
||||
/* calculate starting address of this entry */
|
||||
a = tlb->va.va_epn<<12;
|
||||
if ( ea <= a + m && ea + sz -1 >= a ) {
|
||||
/* overlap */
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Find TLB index that maps 'ea/as' combination
|
||||
@@ -523,38 +523,38 @@ uint32_t pid, mas0, mas1;
|
||||
int i, rval = -1;
|
||||
rtems_interrupt_level lvl;
|
||||
|
||||
rtems_interrupt_disable(lvl);
|
||||
rtems_interrupt_disable(lvl);
|
||||
|
||||
for ( i=0; i<3; i++ ) {
|
||||
switch (i) {
|
||||
case 0: asm volatile("mfspr %0, %1":"=r"(pid):"i"(FSL_EIS_PID0)); break;
|
||||
case 1: asm volatile("mfspr %0, %1":"=r"(pid):"i"(FSL_EIS_PID1)); break;
|
||||
case 2: asm volatile("mfspr %0, %1":"=r"(pid):"i"(FSL_EIS_PID2)); break;
|
||||
default:
|
||||
goto bail;
|
||||
}
|
||||
for ( i=0; i<3; i++ ) {
|
||||
switch (i) {
|
||||
case 0: asm volatile("mfspr %0, %1":"=r"(pid):"i"(FSL_EIS_PID0)); break;
|
||||
case 1: asm volatile("mfspr %0, %1":"=r"(pid):"i"(FSL_EIS_PID1)); break;
|
||||
case 2: asm volatile("mfspr %0, %1":"=r"(pid):"i"(FSL_EIS_PID2)); break;
|
||||
default:
|
||||
goto bail;
|
||||
}
|
||||
|
||||
_write_MAS6( FSL_EIS_MAS6_SPID0(pid) | (as ? FSL_EIS_MAS6_SAS : 0 ) );
|
||||
_write_MAS6( FSL_EIS_MAS6_SPID0(pid) | (as ? FSL_EIS_MAS6_SAS : 0 ) );
|
||||
|
||||
asm volatile("tlbsx 0, %0"::"r"(ea));
|
||||
asm volatile("tlbsx 0, %0"::"r"(ea));
|
||||
|
||||
mas1 = _read_MAS1();
|
||||
mas1 = _read_MAS1();
|
||||
|
||||
if ( (FSL_EIS_MAS1_V & mas1) ) {
|
||||
mas0 = _read_MAS0();
|
||||
if ( FSL_EIS_MAS0_TLBSEL & mas0 ) {
|
||||
/* TLB1 */
|
||||
rval = FSL_EIS_MAS0_ESEL_GET(mas0) | E500_SELTLB_1;
|
||||
} else {
|
||||
rval = (ea >> (63-51)) | (( FSL_EIS_MAS0_NV & mas0 ) ? 180 : 0 ) ;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ( (FSL_EIS_MAS1_V & mas1) ) {
|
||||
mas0 = _read_MAS0();
|
||||
if ( FSL_EIS_MAS0_TLBSEL & mas0 ) {
|
||||
/* TLB1 */
|
||||
rval = FSL_EIS_MAS0_ESEL_GET(mas0) | E500_SELTLB_1;
|
||||
} else {
|
||||
rval = (ea >> (63-51)) | (( FSL_EIS_MAS0_NV & mas0 ) ? 180 : 0 ) ;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
bail:
|
||||
rtems_interrupt_enable(lvl);
|
||||
return rval;
|
||||
rtems_interrupt_enable(lvl);
|
||||
return rval;
|
||||
}
|
||||
|
||||
/* Mark TLB entry as invalid ('disabled'). Unlike
|
||||
@@ -577,55 +577,55 @@ rtems_e500_clrtlb(rtems_e500_tlb_idx key)
|
||||
rtems_e500_tlb_idx k0;
|
||||
rtems_interrupt_level lvl;
|
||||
|
||||
/* minimal guard against bad key */
|
||||
if ( key < 0 )
|
||||
return -1;
|
||||
/* minimal guard against bad key */
|
||||
if ( key < 0 )
|
||||
return -1;
|
||||
|
||||
if ( (key & E500_SELTLB_1) ) {
|
||||
if ( (key & ~E500_SELTLB_1) > 15 ) {
|
||||
myprintf(stderr,"Invalid TLB index; TLB1 index must be < 16\n");
|
||||
return -1;
|
||||
}
|
||||
} else if ( key > 255 ) {
|
||||
myprintf(stderr,"Invalid TLB index; TLB0 index must be < 256\n");
|
||||
return -1;
|
||||
}
|
||||
if ( (key & E500_SELTLB_1) ) {
|
||||
if ( (key & ~E500_SELTLB_1) > 15 ) {
|
||||
myprintf(stderr,"Invalid TLB index; TLB1 index must be < 16\n");
|
||||
return -1;
|
||||
}
|
||||
} else if ( key > 255 ) {
|
||||
myprintf(stderr,"Invalid TLB index; TLB0 index must be < 256\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Must not invalidate page 0 which holds vectors, text etc... */
|
||||
k0 = rtems_e500_ftlb(0, 0);
|
||||
if ( -1 == k0 ) {
|
||||
myprintf(stderr,"tlbivax; something's fishy - I don't find mapping for addr. 0\n");
|
||||
return -1;
|
||||
}
|
||||
/* Must not invalidate page 0 which holds vectors, text etc... */
|
||||
k0 = rtems_e500_ftlb(0, 0);
|
||||
if ( -1 == k0 ) {
|
||||
myprintf(stderr,"tlbivax; something's fishy - I don't find mapping for addr. 0\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* NOTE: we assume PID is ignored, and AS is 0 */
|
||||
if ( k0 == key ) {
|
||||
myprintf(stderr,"Refuse to invalidate page holding addr 0 (always needed)\n");
|
||||
return -1;
|
||||
}
|
||||
/* NOTE: we assume PID is ignored, and AS is 0 */
|
||||
if ( k0 == key ) {
|
||||
myprintf(stderr,"Refuse to invalidate page holding addr 0 (always needed)\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
rtems_interrupt_disable(lvl);
|
||||
rtems_interrupt_disable(lvl);
|
||||
|
||||
seltlb(key);
|
||||
seltlb(key);
|
||||
|
||||
asm volatile("tlbre");
|
||||
asm volatile("tlbre");
|
||||
|
||||
/* read old entries */
|
||||
_write_MAS1( _read_MAS1() & ~FSL_EIS_MAS1_V );
|
||||
/* read old entries */
|
||||
_write_MAS1( _read_MAS1() & ~FSL_EIS_MAS1_V );
|
||||
|
||||
asm volatile(
|
||||
" sync \n"
|
||||
" isync \n"
|
||||
" tlbwe \n"
|
||||
" sync \n"
|
||||
" isync \n"
|
||||
);
|
||||
asm volatile(
|
||||
" sync\n"
|
||||
" isync\n"
|
||||
" tlbwe\n"
|
||||
" sync\n"
|
||||
" isync\n"
|
||||
);
|
||||
|
||||
/* update cache */
|
||||
if ( E500_SELTLB_1 & key )
|
||||
rtems_e500_tlb_va_cache[ (~E500_SELTLB_1 & key) ].att.v = 0;
|
||||
/* update cache */
|
||||
if ( E500_SELTLB_1 & key )
|
||||
rtems_e500_tlb_va_cache[ (~E500_SELTLB_1 & key) ].att.v = 0;
|
||||
|
||||
rtems_interrupt_enable(lvl);
|
||||
rtems_interrupt_enable(lvl);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user