From 3a7dd0be374ee487c2ccc32224c2e33f2b4cf924 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Wed, 28 Aug 2024 04:19:39 +0200
Subject: [PATCH] dev/irq: Do not enable FIQ by default

The default FIQ handler terminates the system.  Delegate the FIQ
enabling to the place which installs a proper FIQ handler.
---
 bsps/shared/dev/irq/arm-gicv2.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index f9ed26d6e8..fa1ac48ab3 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -200,17 +200,6 @@ static inline uint32_t get_id_count(volatile gic_dist *dist)
   return id_count;
 }
 
-static void enable_fiq(void)
-{
-#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
-  rtems_interrupt_level level;
-
-  rtems_interrupt_local_disable(level);
-  level &= ~ARM_PSR_F;
-  rtems_interrupt_local_enable(level);
-#endif
-}
-
 void bsp_interrupt_facility_initialize(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
@@ -240,8 +229,6 @@ void bsp_interrupt_facility_initialize(void)
   cpuif->iccicr = CPUIF_ICCICR;
 
   dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE;
-
-  enable_fiq();
 }
 
 #ifdef RTEMS_SMP
@@ -267,8 +254,6 @@ BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
   cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
   cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
   cpuif->iccicr = CPUIF_ICCICR;
-
-  enable_fiq();
 }
 #endif