forked from Imagelibrary/rtems
New (Submission by Bruce Robinson <brucer@pmccorp.com>).
This commit is contained in:
Ralf Corsepius
12
c/src/lib/libcpu/mips/rm52xx/include/rm5231.h
Normal file
12
c/src/lib/libcpu/mips/rm52xx/include/rm5231.h
Normal file
@@ -0,0 +1,12 @@
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||||
/*
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||||
* MIPS RM5231 specific information
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||||
*
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||||
* rm5231.h,v 1.0 2004/06/23 19:54:22
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||||
*/
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||||
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||||
#ifndef __RM5231_h
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#define __RM5231_h
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#define RM5231_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+8
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#endif
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||||
24
c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c
Normal file
24
c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c
Normal file
@@ -0,0 +1,24 @@
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||||
/*
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* This file contains the maximum number of vectors. This can not
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* be determined without knowing the RTEMS CPU model.
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*
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* COPYRIGHT (c) 1989-2000.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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||||
* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp
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*/
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/*
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* Reserve first 32 for exceptions.
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*/
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#include <rtems.h>
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#include <libcpu/rm5231.h>
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unsigned int mips_interrupt_number_of_vectors = RM5231_MAXIMUM_VECTORS;
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54
c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c
Normal file
54
c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c
Normal file
@@ -0,0 +1,54 @@
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/*
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* RM5231 Interrupt Vectoring
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*
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* vectorisrs.c,v 1.6 2004/06/23 18:16:36
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*/
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#include <rtems.h>
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#include <stdlib.h>
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#include <libcpu/rm5231.h>
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void mips_default_isr( int vector );
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#define CALL_ISR(_vector,_frame) \
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do { \
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if ( _ISR_Vector_table[_vector] ) \
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(_ISR_Vector_table[_vector])(_vector,_frame); \
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else \
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mips_default_isr(_vector); \
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} while (0)
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#include <rtems/bspIo.h> /* for printk */
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void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
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{
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unsigned int sr;
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unsigned int cause;
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unsigned int i;
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unsigned int mask;
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mips_get_sr( sr );
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mips_get_cause( cause );
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cause &= (sr & SR_IMASK);
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cause >>= CAUSE_IPSHIFT;
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for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
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if ( cause & mask )
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CALL_ISR( MIPS_INTERRUPT_BASE + 8 - i, frame );
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}
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}
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void mips_default_isr( int vector )
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{
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unsigned int sr;
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unsigned int cause;
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mips_get_sr( sr );
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mips_get_cause( cause );
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printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
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vector, cause, sr );
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rtems_fatal_error_occurred(1);
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}
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139
c/src/lib/libcpu/mips/tx49/include/tx4925.h
Normal file
139
c/src/lib/libcpu/mips/tx49/include/tx4925.h
Normal file
@@ -0,0 +1,139 @@
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/*
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* MIPS Tx4925 specific information
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*
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* tx4925.h,v 1.0 2004/06/23 19:54:22
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*/
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#ifndef __TX4925_h
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#define __TX4925_h
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#define TX4925_REG_BASE 0xFF1F0000
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/*
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* Configuration Registers
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*/
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#define TX4925_CFG_CCFG 0xE000 /* Chip Configuration Register */
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#define TX4925_CFG_REVID 0xE004 /* Chip Revision ID Register */
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#define TX4925_CFG_PCFG 0xE008 /* Pin Configuration Register */
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#define TX4925_CFG_TOEA 0xE00C /* TimeOut Error Access Address Register */
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#define TX4925_CFG_PDNCTR 0xE010 /* Power Down Control Register */
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#define TX4925_CFG_GARBP 0xE018 /* GBUS Arbiter Priority Register */
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#define TX4925_CFG_TOCNT 0xE020 /* Timeout Count Register */
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#define TX4925_CFG_DRQCTR 0xE024 /* DMA Request Control Register */
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#define TX4925_CFG_CLKCTR 0xE028 /* Clock Control Register */
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#define TX4925_CFG_GARBC 0xE02C /* GBUS Arbiter Control Register */
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#define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */
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/* Pin Configuration register bits */
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#define SELCHI 0x00100000
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#define SELTMR0 0x00000200
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/*
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* Timer Registers
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*/
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#define TX4925_TIMER0_BASE 0xF000
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#define TX4925_TIMER1_BASE 0xF100
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#define TX4925_TIMER2_BASE 0xF200
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#define TX4925_TIMER_TCR 0x00 /* Timer Control Register */
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#define TX4925_TIMER_TISR 0x04 /* Timer Interrupt Status Register */
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#define TX4925_TIMER_CPRA 0x08 /* Compare Register A */
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#define TX4925_TIMER_CPRB 0x0C /* Compare Register B */
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#define TX4925_TIMER_ITMR 0x10 /* Interval Timer Mode Register */
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#define TX4925_TIMER_CCDR 0x20 /* Divide Cycle Register */
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#define TX4925_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */
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#define TX4925_TIMER_WTMR 0x40 /* Reserved Register */
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#define TX4925_TIMER_TRR 0xF0 /* Timer Read Register */
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/* ITMR register bits */
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#define TIMER_CLEAR_ENABLE_MASK 0x1
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#define TIMER_INT_ENABLE_MASK 0x8000
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|
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/* PGMR register bits */
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#define FFI 0x1
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#define TPIAE 0x4000
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#define TPIBE 0x8000
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/* TISR register bits */
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#define TIIS 0x1
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#define TPIAS 0x2
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#define TPIBS 0x4
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||||
#define TWIS 0x8
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||||
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||||
|
||||
/*
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||||
* Interrupt Controller Registers
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||||
*/
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#define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */
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#define TX4925_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */
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||||
#define TX4925_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */
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||||
#define TX4925_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */
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#define TX4925_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */
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#define TX4925_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */
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#define TX4925_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */
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#define TX4925_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */
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#define TX4925_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */
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#define TX4925_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */
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||||
#define TX4925_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */
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#define TX4925_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */
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#define TX4925_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */
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#define TX4925_IRQCTL_PND 0xF680 /* Interrupt Pending Register */
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#define TX4925_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */
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#define TX4925_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */
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#define TX4925_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */
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#define TX4925_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */
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#define TX4925_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */
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#define TX4925_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */
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#define TX4925_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */
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#define TX4925_REG_READ( _base, _register ) \
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*((volatile uint32_t *)((_base) + (_register)))
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#define TX4925_REG_WRITE( _base, _register, _value ) \
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*((volatile uint32_t *)((_base) + (_register))) = (_value)
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/*
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* Interrupt Vector Numbers
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*
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*/
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#define TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0
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#define TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1
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#define TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2
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#define TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3
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#define TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4
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#define TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5
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#define TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6
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#define TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7
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#define TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8
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#define TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9
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#define TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10
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#define TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11
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#define TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12
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#define TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13
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#define TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14
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#define TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15
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#define TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16
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#define TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17
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#define TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18
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#define TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19
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#define TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20
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#define TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21
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#define TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22
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#define TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23
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#define TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24
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#define TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25
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#define TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26
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#define TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27
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#define TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28
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#define TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29
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#define TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30
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#define TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31
|
||||
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#define TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32
|
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#define TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33
|
||||
#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
|
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||||
#endif
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||||
223
c/src/lib/libcpu/mips/tx49/include/tx4938.h
Normal file
223
c/src/lib/libcpu/mips/tx49/include/tx4938.h
Normal file
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* MIPS Tx4938 specific information
|
||||
*
|
||||
* tx4938.h,v 1.0 2004/06/23 19:54:22
|
||||
*/
|
||||
|
||||
#ifndef __TX4938_h
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#define __TX4938_h
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||||
|
||||
#define TX4938_REG_BASE 0xFF1F0000
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||||
|
||||
/* PCI1 Registers */
|
||||
#define TX4938_PCI1_PCIID 0x7000
|
||||
#define TX4938_PCI1_PCISTATUS 0x7004
|
||||
#define TX4938_PCI1_PCICFG1 0x700c
|
||||
#define TX4938_PCI1_P2GM1PLBASE 0x7018
|
||||
#define TX4938_PCI1_P2GCFG 0x7090
|
||||
#define TX4938_PCI1_PBAREQPORT 0x7100
|
||||
#define TX4938_PCI1_PBACFG 0x7104
|
||||
#define TX4938_PCI1_G2PM0GBASE 0x7120
|
||||
#define TX4938_PCI1_G2PIOGBASE 0x7138
|
||||
#define TX4938_PCI1_G2PM0MASK 0x7140
|
||||
#define TX4938_PCI1_G2PIOMASK 0x714c
|
||||
#define TX4938_PCI1_G2PM0PBASE 0x7150
|
||||
#define TX4938_PCI1_G2PIOPBASE 0x7168
|
||||
#define TX4938_PCI1_PCICCFG 0x7170
|
||||
#define TX4938_PCI1_PCICSTATUS 0x7174
|
||||
#define TX4938_PCI1_P2GM1GBASE 0x7188
|
||||
#define TX4938_PCI1_G2PCFGADRS 0x71a0
|
||||
#define TX4938_PCI1_G2PCFGDATA 0x71a4
|
||||
|
||||
/*
|
||||
* Configuration Registers
|
||||
*/
|
||||
#define TX4938_CFG_CCFG 0xE000 /* Chip Configuration Register */
|
||||
#define TX4938_CFG_REVID 0xE008 /* Chip Revision ID Register */
|
||||
#define TX4938_CFG_PCFG 0xE010 /* Pin Configuration Register */
|
||||
#define TX4938_CFG_TOEA 0xE018 /* TimeOut Error Access Address Register */
|
||||
#define TX4938_CFG_CLKCTR 0xE020 /* Clock Control Register */
|
||||
#define TX4938_CFG_GARBC 0xE030 /* GBUS Arbiter Control Register */
|
||||
#define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */
|
||||
|
||||
/* Pin Configuration register bits */
|
||||
#define SELCHI 0x00100000
|
||||
#define SELTMR0 0x00000200
|
||||
|
||||
|
||||
/*
|
||||
* Timer Registers
|
||||
*/
|
||||
|
||||
#define TX4938_TIMER0_BASE 0xF000
|
||||
#define TX4938_TIMER1_BASE 0xF100
|
||||
#define TX4938_TIMER2_BASE 0xF200
|
||||
|
||||
#define TX4938_TIMER_TCR 0x00 /* Timer Control Register */
|
||||
#define TX4938_TIMER_TISR 0x04 /* Timer Interrupt Status Register */
|
||||
#define TX4938_TIMER_CPRA 0x08 /* Compare Register A */
|
||||
#define TX4938_TIMER_CPRB 0x0C /* Compare Register B */
|
||||
#define TX4938_TIMER_ITMR 0x10 /* Interval Timer Mode Register */
|
||||
#define TX4938_TIMER_CCDR 0x20 /* Divide Cycle Register */
|
||||
#define TX4938_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */
|
||||
#define TX4938_TIMER_WTMR 0x40 /* Reserved Register */
|
||||
#define TX4938_TIMER_TRR 0xF0 /* Timer Read Register */
|
||||
|
||||
/* ITMR register bits */
|
||||
#define TIMER_CLEAR_ENABLE_MASK 0x1
|
||||
#define TIMER_INT_ENABLE_MASK 0x8000
|
||||
|
||||
/* PGMR register bits */
|
||||
#define FFI 0x1
|
||||
#define TPIAE 0x4000
|
||||
#define TPIBE 0x8000
|
||||
|
||||
/* TISR register bits */
|
||||
#define TIIS 0x1
|
||||
#define TPIAS 0x2
|
||||
#define TPIBS 0x4
|
||||
#define TWIS 0x8
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Controller Registers
|
||||
*/
|
||||
#define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */
|
||||
#define TX4938_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */
|
||||
#define TX4938_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */
|
||||
#define TX4938_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */
|
||||
#define TX4938_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */
|
||||
#define TX4938_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */
|
||||
#define TX4938_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */
|
||||
#define TX4938_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */
|
||||
#define TX4938_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */
|
||||
#define TX4938_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */
|
||||
#define TX4938_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */
|
||||
#define TX4938_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */
|
||||
#define TX4938_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */
|
||||
#define TX4938_IRQCTL_PND 0xF680 /* Interrupt Pending Register */
|
||||
#define TX4938_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */
|
||||
#define TX4938_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */
|
||||
#define TX4938_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */
|
||||
#define TX4938_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */
|
||||
#define TX4938_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */
|
||||
#define TX4938_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */
|
||||
#define TX4938_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */
|
||||
|
||||
#define TX4938_REG_READ( _base, _register ) \
|
||||
*((volatile uint32_t *)((_base) + (_register)))
|
||||
|
||||
#define TX4938_REG_WRITE( _base, _register, _value ) \
|
||||
*((volatile uint32_t *)((_base) + (_register))) = (_value)
|
||||
|
||||
/*
|
||||
* Interrupt Vector Numbers
|
||||
*
|
||||
*/
|
||||
#define TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0
|
||||
#define TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1
|
||||
#define TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2
|
||||
#define TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3
|
||||
#define TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4
|
||||
#define TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5
|
||||
#define TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6
|
||||
#define TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7
|
||||
#define TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8
|
||||
#define TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9
|
||||
#define TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10
|
||||
#define TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11
|
||||
#define TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12
|
||||
#define TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13
|
||||
#define TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14
|
||||
#define TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15
|
||||
#define TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16
|
||||
#define TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17
|
||||
#define TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18
|
||||
#define TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19
|
||||
#define TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20
|
||||
#define TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21
|
||||
#define TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22
|
||||
#define TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23
|
||||
#define TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24
|
||||
#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25
|
||||
#define TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26
|
||||
#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27
|
||||
#define TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28
|
||||
#define TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29
|
||||
#define TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30
|
||||
#define TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31
|
||||
|
||||
#define TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32
|
||||
#define TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33
|
||||
#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
|
||||
|
||||
/************************************************************************
|
||||
* TX49 Register field encodings
|
||||
*************************************************************************/
|
||||
/******** reg: CCFG ********/
|
||||
/* field: PCIDIVMODE */
|
||||
#define TX4938_CCFG_SYSSP_SHF 6
|
||||
#define TX4938_CCFG_SYSSP_MSK (MSK(2) << TX4938_CCFG_SYSSP_SHF)
|
||||
|
||||
/* field: PCI1DMD */
|
||||
#define TX4938_CCFG_PCI1DMD_SHF 8
|
||||
#define TX4938_CCFG_PCI1DMD_MSK (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
|
||||
|
||||
/* field: PCIDIVMODE */
|
||||
#define TX4938_CCFG_PCIDIVMODE_SHF 10
|
||||
#define TX4938_CCFG_PCIDIVMODE_MSK (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
|
||||
|
||||
/* field: PCI1-66 */
|
||||
#define TX4938_CCFG_PCI166_SHF 21
|
||||
#define TX4938_CCFG_PCI166_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
|
||||
|
||||
/* field: PCIMODE */
|
||||
#define TX4938_CCFG_PCIMODE_SHF 22
|
||||
#define TX4938_CCFG_PCIMODE_MSK ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
|
||||
|
||||
/* field: BRDTY */
|
||||
#define TX4938_CCFG_BRDTY_SHF 36
|
||||
#define TX4938_CCFG_RRDTY_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
|
||||
|
||||
/* field: BRDRV */
|
||||
#define TX4938_CCFG_BRDRV_SHF 32
|
||||
#define TX4938_CCFG_BRDRV_MSK ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
|
||||
|
||||
/******** reg: CLKCTR ********/
|
||||
/* field: PCIC1RST */
|
||||
#define TX4938_CLKCTR_PCIC1RST_SHF 11
|
||||
#define TX4938_CLKCTR_PCIC1RST_MSK (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
|
||||
|
||||
/******** reg: PCISTATUS ********/
|
||||
/* field: MEMSP */
|
||||
#define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
|
||||
#define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
|
||||
|
||||
/* field: BM */
|
||||
#define TX4938_PCI_PCISTATUS_BM_SHF 2
|
||||
#define TX4938_PCI_PCISTATUS_BM_MSK (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
|
||||
|
||||
/******** reg: PBACFG ********/
|
||||
/* field: RPBA */
|
||||
#define TX4938_PCI_PBACFG_RPBA_SHF 2
|
||||
#define TX4938_PCI_PBACFG_RPBA_MSK (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
|
||||
|
||||
/* field: PBAEN */
|
||||
#define TX4938_PCI_PBACFG_PBAEN_SHF 1
|
||||
#define TX4938_PCI_PBACFG_PBAEN_MSK (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
|
||||
|
||||
/******** reg: PCICFG ********/
|
||||
/* field: G2PM0EN */
|
||||
#define TX4938_PCI_PCICFG_G2PM0EN_SHF 6
|
||||
#define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
|
||||
|
||||
/* field: G2PIOEN */
|
||||
#define TX4938_PCI_PCICFG_G2PIOEN_SHF 5
|
||||
#define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
|
||||
|
||||
/* field: TCAR */
|
||||
#define TX4938_PCI_PCICFG_TCAR_SHF 4
|
||||
#define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
|
||||
|
||||
|
||||
#endif
|
||||
30
c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c
Normal file
30
c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c
Normal file
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* This file contains the maximum number of vectors. This can not
|
||||
* be determined without knowing the RTEMS CPU model.
|
||||
*
|
||||
* COPYRIGHT (c) 1989-2000.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp
|
||||
*/
|
||||
|
||||
/*
|
||||
* Reserve first 32 for exceptions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Toshiba TX4925 attaches 5 of the eight interrupt bits to an
|
||||
* on-CPU interrupt controller so that these five bits map to 32
|
||||
* unique interrupts. So you have: 2 software interrupts, an NMI,
|
||||
* and 32 others.
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <libcpu/tx4925.h>
|
||||
|
||||
unsigned int mips_interrupt_number_of_vectors = TX4925_MAXIMUM_VECTORS;
|
||||
|
||||
61
c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c
Normal file
61
c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c
Normal file
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* TX4925 Interrupt Vectoring
|
||||
*
|
||||
* vectorisrs.c,v 1.6 2004/06/23 18:16:36
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <stdlib.h>
|
||||
#include <libcpu/tx4925.h>
|
||||
|
||||
void mips_default_isr( int vector );
|
||||
|
||||
#define CALL_ISR(_vector,_frame) \
|
||||
do { \
|
||||
if ( _ISR_Vector_table[_vector] ) \
|
||||
(_ISR_Vector_table[_vector])(_vector,_frame); \
|
||||
else \
|
||||
mips_default_isr(_vector); \
|
||||
} while (0)
|
||||
|
||||
#include <rtems/bspIo.h> /* for printk */
|
||||
|
||||
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
|
||||
{
|
||||
unsigned int sr;
|
||||
unsigned int cause;
|
||||
unsigned int pending;
|
||||
|
||||
mips_get_sr( sr );
|
||||
mips_get_cause( cause );
|
||||
|
||||
pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
|
||||
|
||||
if ( pending & 0x4 ) { /* (IP[2] == 1) ==> IP[3-7] are valid */
|
||||
unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
|
||||
CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
|
||||
}
|
||||
|
||||
if ( pending & 0x01 ) /* IP[0] */
|
||||
CALL_ISR( TX4925_IRQ_SOFTWARE_1, frame );
|
||||
|
||||
if ( pending & 0x02 ) /* IP[1] */
|
||||
CALL_ISR( TX4925_IRQ_SOFTWARE_2, frame );
|
||||
}
|
||||
|
||||
void mips_default_isr( int vector )
|
||||
{
|
||||
unsigned int sr;
|
||||
unsigned int cause;
|
||||
|
||||
mips_get_sr( sr );
|
||||
mips_get_cause( cause );
|
||||
|
||||
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
|
||||
vector, cause, sr );
|
||||
|
||||
while(1); /* Lock it up */
|
||||
|
||||
rtems_fatal_error_occurred(1);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user