diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h
index 7f1eb87812..92eb16ca2b 100644
--- a/bsps/arm/shared/cache/cache-cp15.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -369,18 +369,6 @@ static inline void arm_cache_l1_disable_data( void )
   arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
 }
 
-static inline void arm_cache_l1_disable_instruction( void )
-{
-  /* Synchronize the processor */
-  _ARM_Data_synchronization_barrier();
-
-  /* Invalidate the Instruction cache */
-  arm_cache_l1_invalidate_entire_instruction();
-
-  /* Disable the Instruction cache */
-  arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
-}
-
 static inline size_t arm_cache_l1_get_data_cache_size( void )
 {
   size_t   size;
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c
index dd0dbe0a06..16a5489fcc 100644
--- a/bsps/arm/shared/cache/cache-l2c-310.c
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -56,7 +56,8 @@
 #include <bsp.h>
 #include <bsp/fatal.h>
 #include <libcpu/arm-cp15.h>
-#include <rtems/rtems/intr.h>
+#include <rtems.h>
+#include <rtems/score/smpimpl.h>
 #include <bsp/arm-release-id.h>
 #include <bsp/arm-errata.h>
 
@@ -1185,17 +1186,58 @@ _CPU_cache_disable_data( void )
   l2c_310_disable();
 }
 
+static void l2c_310_enable_instruction( void *arg )
+{
+  rtems_interrupt_level level;
+
+  (void) arg;
+
+  rtems_interrupt_local_disable(level);
+  arm_cp15_set_control( arm_cp15_get_control() | ARM_CP15_CTRL_I );
+  rtems_interrupt_local_enable(level);
+}
+
 static inline void
 _CPU_cache_enable_instruction( void )
 {
-  l2c_310_enable();
+#ifdef RTEMS_SMP
+  rtems_interrupt_level level;
+
+  rtems_interrupt_local_disable( level );
+  _SMP_Broadcast_action( l2c_310_enable_instruction, NULL );
+  rtems_interrupt_local_enable( level );
+#else
+  l2c_310_enable_instruction( NULL );
+#endif
+}
+
+static void l2c_310_disable_instruction( void *arg )
+{
+  rtems_interrupt_level level;
+
+  (void) arg;
+
+  rtems_interrupt_local_disable(level);
+  arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
+  rtems_interrupt_local_enable(level);
+
+  arm_cache_l1_invalidate_entire_instruction();
 }
 
 static inline void
 _CPU_cache_disable_instruction( void )
 {
-  arm_cache_l1_disable_instruction();
-  l2c_310_disable();
+  l2c_310_flush_entire();
+
+#ifdef RTEMS_SMP
+  rtems_interrupt_level level;
+
+  rtems_interrupt_local_disable( level );
+  _SMP_Broadcast_action( l2c_310_disable_instruction, NULL );
+  rtems_interrupt_local_enable( level );
+#else
+  l2c_310_disable_instruction( NULL );
+#endif
 }
 
 static inline void