2009-05-05 Jennifer Averett <jennifer.averett@OARcorp.com>

* mpc6xx/mmu/bat.c, new-exceptions/e500_raw_exc_init.c,
	new-exceptions/raw_exception.h, new-exceptions/bspsupport/irq_supp.h,
	shared/include/cpuIdent.c: Removed warnings. Split
	bsp_irq_dispatch_list to allow non-standard/non-existant pics to call
	with interrupts off.

c/src/lib/libcpu/powerpc/ChangeLog

@@ -1,3 +1,11 @@
+2009-05-05	Jennifer Averett <jennifer.averett@OARcorp.com>
+
+	* mpc6xx/mmu/bat.c, new-exceptions/e500_raw_exc_init.c,
+	new-exceptions/raw_exception.h, new-exceptions/bspsupport/irq_supp.h,
+	shared/include/cpuIdent.c: Removed warnings. Split
+	bsp_irq_dispatch_list to allow non-standard/non-existant pics to call
+	with interrupts off.
+
 2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
 
 	PR 1385/cpukit

c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c

@@ -160,7 +160,7 @@ bat_addrs_put (ubat * bat, int typ, int idx)
  * cache.
  */
 static void
-bat_addrs_init ()
+bat_addrs_init (void)
 {
   ubat bat;
 
@@ -204,7 +204,7 @@ bat_addrs_init ()
 }
 
 static void
-do_dssall ()
+do_dssall (void)
 {
   /* Before changing BATs, 'dssall' must be issued.
    * We check MSR for MSR_VE and issue a 'dssall' if
@@ -227,7 +227,7 @@ do_dssall ()
 
 /* Clear I/D bats 4..7 ONLY ON 7455 etc.  */
 static void
-clear_hi_bats ()
+clear_hi_bats (void)
 {
   do_dssall ();
   CLRBAT (DBAT4);

c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h

@@ -66,6 +66,29 @@ struct _BSP_Exception_frame;
  */
 int C_dispatch_irq_handler (struct _BSP_Exception_frame *frame, unsigned int excNum);
 
+/*
+ * Snippet to be used by PIC drivers and by bsp_irq_dispatch_list
+ * traverses list of shared handlers for a given interrupt
+ *
+ */
+
+static inline void
+bsp_irq_dispatch_list_base(
+  rtems_irq_connect_data *tbl,
+  unsigned irq,
+  rtems_irq_hdl sentinel
+)
+{
+	rtems_irq_connect_data* vchain;
+	for( vchain = &tbl[irq];
+			((int)vchain != -1 && vchain->hdl != sentinel);
+			vchain = (rtems_irq_connect_data*)vchain->next_handler )
+	{
+          vchain->hdl(vchain->handle);
+	}
+}
+
+
 /*
  * Snippet to be used by PIC drivers;
  * enables interrupts, traverses list of
@@ -90,13 +113,8 @@ bsp_irq_dispatch_list(
 	/* Enable all interrupts */
 	_ISR_Set_level(0);
 
-	rtems_irq_connect_data* vchain;
+
-	for( vchain = &tbl[irq];
+        bsp_irq_dispatch_list_base( tbl, irq, sentinel );
-			((int)vchain != -1 && vchain->hdl != sentinel);
-			vchain = (rtems_irq_connect_data*)vchain->next_handler )
-	{
-		vchain->hdl(vchain->handle);
-	}
 
 	/* Restore original level */
 	_ISR_Set_level(l_orig);

c/src/lib/libcpu/powerpc/new-exceptions/e500_raw_exc_init.c

@@ -38,7 +38,7 @@ e500_setup_raw_exceptions(void)
 	MTIVOR(35, ppc_get_vector_addr(ASM_60X_PERFMON_VECTOR));
 }
 
-void e200_setup_raw_exceptions()
+void e200_setup_raw_exceptions(void)
 {
 	if (current_ppc_cpu != PPC_e200z6) {
 		return;

c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.h

@@ -231,7 +231,8 @@ extern int ppc_get_exception_config (rtems_raw_except_global_settings** config);
 void* ppc_get_vector_addr(rtems_vector vector);
 
 int ppc_is_e500();
-void e500_setup_raw_exceptions();
+void e200_setup_raw_exceptions(void);
+void e500_setup_raw_exceptions(void);
 
 /* This variable is initialized to 'TRUE' by default;
  * BSPs which have their vectors in ROM should set it

c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c

@@ -70,7 +70,7 @@ char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu)
   return "UNKNOWN";
 }
 
-ppc_cpu_id_t get_ppc_cpu_type()
+ppc_cpu_id_t get_ppc_cpu_type(void)
 {
   unsigned int pvr;
 
@@ -185,7 +185,7 @@ ppc_cpu_id_t get_ppc_cpu_type()
   return current_ppc_cpu;
 }
 
-ppc_cpu_revision_t get_ppc_cpu_revision()
+ppc_cpu_revision_t get_ppc_cpu_revision(void)
 {
   ppc_cpu_revision_t rev = (ppc_cpu_revision_t) (_read_PVR() & 0xffff);
   current_ppc_revision = rev;