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2011-09-02 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* rtems/score/nios2-utility.h: Avoid redefines with Altera HAL.
	Declare _Nios2_ISR_Set_level().
	* nios2-context-initialize.c: Use _Nios2_ISR_Set_level().
	* nios2-isr-set-level.c: Define _Nios2_ISR_Set_level().
This commit is contained in:
Sebastian Huber
2011-09-02 07:52:30 +00:00
parent cae389ba36
commit 36c187a0cd
4 changed files with 48 additions and 13 deletions
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7
cpukit/score/cpu/nios2/ChangeLog
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@@ -1,3 +1,10 @@
2011-09-02 Sebastian Huber <sebastian.huber@embedded-brains.de>
* rtems/score/nios2-utility.h: Avoid redefines with Altera HAL.
Declare _Nios2_ISR_Set_level().
* nios2-context-initialize.c: Use _Nios2_ISR_Set_level().
* nios2-isr-set-level.c: Define _Nios2_ISR_Set_level().
2011-09-01 Sebastian Huber <sebastian.huber@embedded-brains.de> 2011-09-01 Sebastian Huber <sebastian.huber@embedded-brains.de>
* cpu.c, cpu_asm.S: Removed files. * cpu.c, cpu_asm.S: Removed files.

7
cpukit/score/cpu/nios2/nios2-context-initialize.c
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@@ -17,9 +17,11 @@
#include "config.h" #include "config.h"
#endif #endif
#include <rtems/score/cpu.h>
#include <string.h> #include <string.h>
#include <rtems/score/cpu.h>
#include <rtems/score/nios2-utility.h>
void _CPU_Context_Initialize( void _CPU_Context_Initialize(
Context_Control *context, Context_Control *context,
void *stack_area_begin, void *stack_area_begin,
@@ -34,8 +36,7 @@ void _CPU_Context_Initialize(
memset(context, 0, sizeof(*context)); memset(context, 0, sizeof(*context));
context->fp = stack; context->fp = stack;
context->status = _Nios2_ISR_Set_level( new_level, NIOS2_STATUS_PIE );
context->sp = stack; context->sp = stack;
context->ra = (uint32_t) entry_point; context->ra = (uint32_t) entry_point;
/* @todo Add EIC support. */
context->status = new_level ? 0 : 1;
} }

13
cpukit/score/cpu/nios2/nios2-isr-set-level.c
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@@ -21,10 +21,8 @@
#include <rtems/score/interr.h> #include <rtems/score/interr.h>
#include <rtems/score/nios2-utility.h> #include <rtems/score/nios2-utility.h>
void _CPU_ISR_Set_level( uint32_t new_level ) uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status )
{ {
uint32_t status = _Nios2_Get_ctlreg_status();
switch ( _Nios2_Get_ISR_status_mask() ) { switch ( _Nios2_Get_ISR_status_mask() ) {
case NIOS2_ISR_STATUS_MASK_IIC: case NIOS2_ISR_STATUS_MASK_IIC:
if ( new_level == 0 ) { if ( new_level == 0 ) {
@@ -50,5 +48,14 @@ void _CPU_ISR_Set_level( uint32_t new_level )
break; break;
} }
return status;
}
void _CPU_ISR_Set_level( uint32_t new_level )
{
uint32_t status = _Nios2_Get_ctlreg_status();
status = _Nios2_ISR_Set_level( new_level, status );
_Nios2_Set_ctlreg_status( status ); _Nios2_Set_ctlreg_status( status );
} }

34
cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
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@@ -103,16 +103,36 @@
#define NIOS2_MPUBASE_BASE_OFFSET 5 #define NIOS2_MPUBASE_BASE_OFFSET 5
#define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET) #define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET)
#define NIOS2_MPUBASE_INDEX_OFFSET 1 #define NIOS2_MPUBASE_INDEX_OFFSET 1
#define NIOS2_MPUBASE_INDEX_MASK (0x1f << NIOS2_MPUBASE_INDEX_OFFSET)
/* Avoid redefines with Altera HAL */
#ifndef NIOS2_MPUBASE_INDEX_MASK
#define NIOS2_MPUBASE_INDEX_MASK (0x1f << NIOS2_MPUBASE_INDEX_OFFSET)
#endif
#define NIOS2_MPUBASE_D (1 << 0) #define NIOS2_MPUBASE_D (1 << 0)
#define NIOS2_MPUACC_MASK_OFFSET 6 #define NIOS2_MPUACC_MASK_OFFSET 6
#define NIOS2_MPUACC_MASK_MASK (0x1ffffff << NIOS2_MPUACC_MASK_OFFSET)
/* Avoid redefines with Altera HAL */
#ifndef NIOS2_MPUACC_MASK_MASK
#define NIOS2_MPUACC_MASK_MASK (0x1ffffff << NIOS2_MPUACC_MASK_OFFSET)
#endif
#define NIOS2_MPUACC_LIMIT_OFFSET 6 #define NIOS2_MPUACC_LIMIT_OFFSET 6
#define NIOS2_MPUACC_LIMIT_MASK (0x3ffffff << NIOS2_MPUACC_LIMIT_OFFSET)
/* Avoid redefines with Altera HAL */
#ifndef NIOS2_MPUACC_LIMIT_MASK
#define NIOS2_MPUACC_LIMIT_MASK (0x3ffffff << NIOS2_MPUACC_LIMIT_OFFSET)
#endif
#define NIOS2_MPUACC_C (1 << 5) #define NIOS2_MPUACC_C (1 << 5)
#define NIOS2_MPUACC_PERM_OFFSET 2 #define NIOS2_MPUACC_PERM_OFFSET 2
#define NIOS2_MPUACC_PERM_MASK (0x7 << NIOS2_MPUACC_PERM_OFFSET)
/* Avoid redefines with Altera HAL */
#ifndef NIOS2_MPUACC_PERM_MASK
#define NIOS2_MPUACC_PERM_MASK (0x7 << NIOS2_MPUACC_PERM_OFFSET)
#endif
#define NIOS2_MPUACC_RD (1 << 1) #define NIOS2_MPUACC_RD (1 << 1)
#define NIOS2_MPUACC_WR (1 << 0) #define NIOS2_MPUACC_WR (1 << 0)
@@ -286,11 +306,11 @@ static inline uint32_t _Nios2_Get_ISR_status_bits( void )
static inline bool _Nios2_Has_internal_interrupt_controller( void ) static inline bool _Nios2_Has_internal_interrupt_controller( void )
{ {
uint32_t isr_status_mask = _Nios2_Get_ISR_status_mask(); return _Nios2_Get_ISR_status_mask() == NIOS2_ISR_STATUS_MASK_IIC;
return isr_status_mask == NIOS2_ISR_STATUS_MASK_IIC;
} }
uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status );
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */