forked from Imagelibrary/rtems
FP context switch may be called from environment with no
FPU available (ISR, int-only task) - switch FPU on for the switch and restore MSR_FP after it's done.
This commit is contained in:
@@ -1,7 +1,11 @@
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2006-06-19 Till Straumann <strauman@slac.stanford.edu>
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2006-06-19 Till Straumann <strauman@slac.stanford.edu>
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* new-exceptions/cpu.c: Never allow the FPU to be switched
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* new-exceptions/cpu.c, new-exceptions/cpu_asm.S: Never
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on for integer-only tasks (new gcc may use FP regs implicitely).
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allow the FPU to be switched on for integer-only tasks
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(new gcc may use FP regs implicitely).
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FP context switch may be called from environment with no
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FPU available (ISR, int-only task) - switch FPU on
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for the switch and restore MSR_FP after it's done.
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2006-05-16 Ralf Corsepius <ralf.corsepius@rtems.org>
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2006-05-16 Ralf Corsepius <ralf.corsepius@rtems.org>
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@@ -33,6 +33,7 @@
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#include <rtems/asm.h>
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#include <rtems/asm.h>
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#include <rtems/powerpc/powerpc.h>
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#include <rtems/powerpc/powerpc.h>
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#include <rtems/powerpc/registers.h>
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/*
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/*
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* Offsets for various Contexts
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* Offsets for various Contexts
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@@ -161,6 +162,16 @@
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PUBLIC_PROC (_CPU_Context_save_fp)
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PUBLIC_PROC (_CPU_Context_save_fp)
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PROC (_CPU_Context_save_fp):
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PROC (_CPU_Context_save_fp):
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#if (PPC_HAS_FPU == 1)
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#if (PPC_HAS_FPU == 1)
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/* A FP context switch may occur in an ISR or exception handler when the FPU is not
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* available. Therefore, we must explicitely enable it here!
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*/
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mfmsr r4
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andi. r5,r4,MSR_FP
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bne 1f
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ori r5,r4,MSR_FP
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mtmsr r5
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isync
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1:
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lwz r3, 0(r3)
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lwz r3, 0(r3)
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STF f0, FP_0(r3)
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STF f0, FP_0(r3)
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STF f1, FP_1(r3)
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STF f1, FP_1(r3)
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@@ -196,6 +207,10 @@ PROC (_CPU_Context_save_fp):
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STF f31, FP_31(r3)
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STF f31, FP_31(r3)
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mffs f2
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mffs f2
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STF f2, FP_FPSCR(r3)
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STF f2, FP_FPSCR(r3)
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bne 1f
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mtmsr r4
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isync
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1:
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#endif
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#endif
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blr
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blr
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@@ -217,6 +232,16 @@ PROC (_CPU_Context_save_fp):
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PROC (_CPU_Context_restore_fp):
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PROC (_CPU_Context_restore_fp):
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#if (PPC_HAS_FPU == 1)
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#if (PPC_HAS_FPU == 1)
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lwz r3, 0(r3)
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lwz r3, 0(r3)
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/* A FP context switch may occur in an ISR or exception handler when the FPU is not
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* available. Therefore, we must explicitely enable it here!
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*/
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mfmsr r4
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andi. r5,r4,MSR_FP
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bne 1f
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ori r5,r4,MSR_FP
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mtmsr r5
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isync
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1:
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LDF f2, FP_FPSCR(r3)
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LDF f2, FP_FPSCR(r3)
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mtfsf 255, f2
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mtfsf 255, f2
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LDF f0, FP_0(r3)
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LDF f0, FP_0(r3)
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@@ -251,6 +276,10 @@ PROC (_CPU_Context_restore_fp):
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LDF f29, FP_29(r3)
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LDF f29, FP_29(r3)
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LDF f30, FP_30(r3)
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LDF f30, FP_30(r3)
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LDF f31, FP_31(r3)
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LDF f31, FP_31(r3)
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bne 1f
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mtmsr r4
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isync
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1:
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#endif
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#endif
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blr
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blr
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