RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

Whitespace removal.

Browse Source
This commit is contained in:
Ralf Corsepius
2009-11-30 05:09:41 +00:00
parent ac7af4a359
commit 359e537416
199 changed files with 1685 additions and 1685 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
c/src/lib/libbsp/i386/i386ex/timer/timer.c
View File

@@ -1,4 +1,4 @@
/* /*
* COPYRIGHT (c) 1989-1999. * COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR). * On-Line Applications Research Corporation (OAR).
* *

18
c/src/lib/libbsp/i386/pc386/clock/ckinit.c
View File

@@ -84,7 +84,7 @@ uint32_t bsp_clock_nanoseconds_since_last_tick_tsc(void)
/****** /******
* Get nanoseconds using Pentium-compatible TSC register * Get nanoseconds using Pentium-compatible TSC register
******/ ******/
uint64_t diff_nsec; uint64_t diff_nsec;
diff_nsec = rdtsc() - pc586_tsc_at_tick; diff_nsec = rdtsc() - pc586_tsc_at_tick;
@@ -106,7 +106,7 @@ uint32_t bsp_clock_nanoseconds_since_last_tick_tsc(void)
return (uint32_t)diff_nsec; return (uint32_t)diff_nsec;
} }
uint32_t bsp_clock_nanoseconds_since_last_tick_i8254(void) uint32_t bsp_clock_nanoseconds_since_last_tick_i8254(void)
{ {
@@ -179,7 +179,7 @@ static void calibrate_tsc(void)
begin_time = rdtsc(); begin_time = rdtsc();
for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick; for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick;
i != 0; --i ) { i != 0; --i ) {
/* We know we've just completed a tick when timer goes from low to high */ /* We know we've just completed a tick when timer goes from low to high */
then_lsb = then_msb = 0xff; then_lsb = then_msb = 0xff;
do { do {
@@ -200,7 +200,7 @@ static void calibrate_tsc(void)
#if 0 #if 0
printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_per_tick / 1000000)); printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_per_tick / 1000000));
#endif #endif
pc586_tsc_per_tick /= rtems_clock_get_ticks_per_second(); pc586_tsc_per_tick /= rtems_clock_get_ticks_per_second();
} }
@@ -218,7 +218,7 @@ static void clockOn(
pc386_clock_click_count = US_TO_TICK(pc386_microseconds_per_isr); pc386_clock_click_count = US_TO_TICK(pc386_microseconds_per_isr);
#if 0 #if 0
printk( "configured usecs per tick=%d \n", printk( "configured usecs per tick=%d \n",
rtems_configuration_get_microseconds_per_tick() ); rtems_configuration_get_microseconds_per_tick() );
printk( "Microseconds per ISR =%d\n", pc386_microseconds_per_isr ); printk( "Microseconds per ISR =%d\n", pc386_microseconds_per_isr );
printk( "final ISRs per=%d\n", pc386_isrs_per_tick ); printk( "final ISRs per=%d\n", pc386_isrs_per_tick );
@@ -267,7 +267,7 @@ void Clock_driver_support_initialize_hardware(void)
{ {
bool use_tsc = false; bool use_tsc = false;
bool use_8254 = false; bool use_8254 = false;
#if (CLOCK_DRIVER_USE_TSC == 1) #if (CLOCK_DRIVER_USE_TSC == 1)
use_tsc = true; use_tsc = true;
#endif #endif
@@ -275,7 +275,7 @@ void Clock_driver_support_initialize_hardware(void)
#if (CLOCK_DRIVER_USE_8254 == 1) #if (CLOCK_DRIVER_USE_8254 == 1)
use_8254 = true; use_8254 = true;
#endif #endif
if ( !use_tsc && !use_8254 ) { if ( !use_tsc && !use_8254 ) {
if ( x86_has_tsc() ) use_tsc = true; if ( x86_has_tsc() ) use_tsc = true;
else use_8254 = true; else use_8254 = true;
@@ -284,12 +284,12 @@ void Clock_driver_support_initialize_hardware(void)
if ( use_8254 ) { if ( use_8254 ) {
/* printk( "Use 8254\n" ); */ /* printk( "Use 8254\n" ); */
Clock_driver_support_at_tick = Clock_driver_support_at_tick_empty; Clock_driver_support_at_tick = Clock_driver_support_at_tick_empty;
Clock_driver_nanoseconds_since_last_tick = Clock_driver_nanoseconds_since_last_tick =
bsp_clock_nanoseconds_since_last_tick_i8254; bsp_clock_nanoseconds_since_last_tick_i8254;
} else { } else {
/* printk( "Use TSC\n" ); */ /* printk( "Use TSC\n" ); */
Clock_driver_support_at_tick = Clock_driver_support_at_tick_tsc; Clock_driver_support_at_tick = Clock_driver_support_at_tick_tsc;
Clock_driver_nanoseconds_since_last_tick = Clock_driver_nanoseconds_since_last_tick =
bsp_clock_nanoseconds_since_last_tick_tsc; bsp_clock_nanoseconds_since_last_tick_tsc;
} }

4
c/src/lib/libbsp/i386/pc386/console/console.c
View File

@@ -228,8 +228,8 @@ console_initialize(rtems_device_major_number major,
void *arg) void *arg)
{ {
rtems_status_code status; rtems_status_code status;
/* Initialize the KBD interface */ /* Initialize the KBD interface */
kbd_init(); kbd_init();

12
c/src/lib/libbsp/i386/pc386/console/fb_vga.c
View File

@@ -86,7 +86,7 @@ rtems_device_driver frame_buffer_initialize(
printk("Error registering /dev/fb0 FBVGA framebuffer device!\n"); printk("Error registering /dev/fb0 FBVGA framebuffer device!\n");
rtems_fatal_error_occurred( status ); rtems_fatal_error_occurred( status );
} }
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }
@@ -102,13 +102,13 @@ rtems_device_driver frame_buffer_open(
if (pthread_mutex_trylock(&mutex)== 0){ if (pthread_mutex_trylock(&mutex)== 0){
/* restore previous state. for VGA this means return to text mode. /* restore previous state. for VGA this means return to text mode.
* leave out if graphics hardware has been initialized in * leave out if graphics hardware has been initialized in
* frame_buffer_initialize() * frame_buffer_initialize()
*/ */
ega_hwinit(); ega_hwinit();
printk( "FBVGA open called.\n" ); printk( "FBVGA open called.\n" );
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }
return RTEMS_UNSATISFIED; return RTEMS_UNSATISFIED;
} }
@@ -145,7 +145,7 @@ rtems_device_driver frame_buffer_read(
rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg; rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg;
rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count; rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count;
memcpy(rw_args->buffer, (const void *) (fb_fix.smem_start + rw_args->offset), rw_args->bytes_moved); memcpy(rw_args->buffer, (const void *) (fb_fix.smem_start + rw_args->offset), rw_args->bytes_moved);
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }
/* /*
@@ -160,7 +160,7 @@ rtems_device_driver frame_buffer_write(
rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg; rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg;
rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count; rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count;
memcpy( (void *) (fb_fix.smem_start + rw_args->offset), rw_args->buffer, rw_args->bytes_moved); memcpy( (void *) (fb_fix.smem_start + rw_args->offset), rw_args->buffer, rw_args->bytes_moved);
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }
static int get_fix_screen_info( struct fb_fix_screeninfo *info ) static int get_fix_screen_info( struct fb_fix_screeninfo *info )

6
c/src/lib/libbsp/i386/pc386/console/ps2_mouse.c
View File

@@ -96,10 +96,10 @@ static int isr_is_on(const rtems_irq_connect_data *irq)
} }
static rtems_irq_connect_data ps2_isr_data = { AUX_IRQ, static rtems_irq_connect_data ps2_isr_data = { AUX_IRQ,
ps2_mouse_interrupt, ps2_mouse_interrupt,
0, 0,
isr_on, isr_on,
isr_off, isr_off,
isr_is_on }; isr_is_on };
/* /*

52
c/src/lib/libbsp/i386/pc386/ide/ide.c
View File

@@ -87,7 +87,7 @@ static bool pc386_ide_status_busy (uint32_t port,
{ {
volatile uint8_t status; volatile uint8_t status;
int polls; int polls;
do do
{ {
polls = 500; polls = 500;
@@ -121,14 +121,14 @@ static bool pc386_ide_status_data_ready (uint32_t port,
{ {
volatile uint8_t status; volatile uint8_t status;
int polls; int polls;
do do
{ {
polls = 1000; polls = 1000;
while (polls) while (polls)
{ {
inport_byte (port + IDE_REGISTER_STATUS, status); inport_byte (port + IDE_REGISTER_STATUS, status);
if (((status & IDE_REGISTER_STATUS_BSY) == 0) && if (((status & IDE_REGISTER_STATUS_BSY) == 0) &&
(status & IDE_REGISTER_STATUS_DRQ)) (status & IDE_REGISTER_STATUS_DRQ))
{ {
@@ -229,7 +229,7 @@ void pc386_ide_initialize
char model_number[41]; char model_number[41];
char* p = &model_number[0]; char* p = &model_number[0];
bool data_ready; bool data_ready;
memset(model_number, 0, sizeof(model_number)); memset(model_number, 0, sizeof(model_number));
outport_byte(port+IDE_REGISTER_DEVICE_HEAD, outport_byte(port+IDE_REGISTER_DEVICE_HEAD,
@@ -240,11 +240,11 @@ void pc386_ide_initialize
*/ */
outport_byte(port+IDE_REGISTER_COMMAND, 0x00); outport_byte(port+IDE_REGISTER_COMMAND, 0x00);
if (!pc386_ide_status_busy (port, PC386_IDE_PROBE_TIMEOUT, if (!pc386_ide_status_busy (port, PC386_IDE_PROBE_TIMEOUT,
&status, pc386_ide_prestart_sleep)) &status, pc386_ide_prestart_sleep))
continue; continue;
inport_byte(port+IDE_REGISTER_STATUS, status); inport_byte(port+IDE_REGISTER_STATUS, status);
inport_byte(port+IDE_REGISTER_ERROR, error); inport_byte(port+IDE_REGISTER_ERROR, error);
inport_byte(port+IDE_REGISTER_CYLINDER_LOW, cyllsb); inport_byte(port+IDE_REGISTER_CYLINDER_LOW, cyllsb);
@@ -294,15 +294,15 @@ void pc386_ide_initialize
if (!data_ready) if (!data_ready)
continue; continue;
byte = 0; byte = 0;
while (byte < 512) while (byte < 512)
{ {
uint16_t word; uint16_t word;
if (pc386_ide_show && ((byte % 16) == 0)) if (pc386_ide_show && ((byte % 16) == 0))
printk("\n %04x : ", byte); printk("\n %04x : ", byte);
inport_word(port+IDE_REGISTER_DATA, word); inport_word(port+IDE_REGISTER_DATA, word);
if (pc386_ide_show) if (pc386_ide_show)
@@ -314,7 +314,7 @@ void pc386_ide_initialize
heads = word; heads = word;
if (byte == 12) if (byte == 12)
sectors = word; sectors = word;
if (byte >= 54 && byte < (54 + 40)) if (byte >= 54 && byte < (54 + 40))
{ {
*p = word >> 8; *p = word >> 8;
@@ -325,10 +325,10 @@ void pc386_ide_initialize
if (byte == (47 * 2)) if (byte == (47 * 2))
max_multiple_sectors = word & 0xff; max_multiple_sectors = word & 0xff;
if (byte == (49 * 2)) if (byte == (49 * 2))
capabilities = word; capabilities = word;
if (byte == (59 * 2)) if (byte == (59 * 2))
{ {
if (word & (1 << 8)) if (word & (1 << 8))
@@ -339,10 +339,10 @@ void pc386_ide_initialize
lba_sectors = word; lba_sectors = word;
if (byte == (61 * 2)) if (byte == (61 * 2))
lba_sectors |= word << 16; lba_sectors |= word << 16;
byte += 2; byte += 2;
} }
if (pc386_ide_show) if (pc386_ide_show)
printk("\nbytes read = %d\n", byte); printk("\nbytes read = %d\n", byte);
@@ -359,7 +359,7 @@ void pc386_ide_initialize
size = cylinders * heads * sectors; size = cylinders * heads * sectors;
size /= 2; size /= 2;
if (size > (1024 * 1024)) if (size > (1024 * 1024))
{ {
size = (size * 10) / (1000 * 1000); size = (size * 10) / (1000 * 1000);
@@ -378,7 +378,7 @@ void pc386_ide_initialize
left = size / 10; left = size / 10;
right = size % 10; right = size % 10;
p--; p--;
while (*p == ' ') while (*p == ' ')
{ {
@@ -390,7 +390,7 @@ void pc386_ide_initialize
minor, label, model_number, left, right, units, minor, label, model_number, left, right, units,
heads, cylinders, sectors, max_multiple_sectors * 512); heads, cylinders, sectors, max_multiple_sectors * 512);
} }
#if IDE_CLEAR_MULTI_SECTOR_COUNT #if IDE_CLEAR_MULTI_SECTOR_COUNT
if (max_multiple_sectors) if (max_multiple_sectors)
{ {
@@ -417,14 +417,14 @@ void pc386_ide_initialize
} }
} }
#endif #endif
outport_byte(port+IDE_REGISTER_DEVICE_CONTROL, outport_byte(port+IDE_REGISTER_DEVICE_CONTROL,
IDE_REGISTER_DEVICE_CONTROL_nIEN); IDE_REGISTER_DEVICE_CONTROL_nIEN);
wait(10000); wait(10000);
} }
pc386_ide_timeout = PC386_IDE_TASKING_TIMEOUT; pc386_ide_timeout = PC386_IDE_TASKING_TIMEOUT;
/* /*
* FIXME: enable interrupts, if needed * FIXME: enable interrupts, if needed
*/ */
@@ -535,7 +535,7 @@ void pc386_ide_read_block
uint16_t *lbuf; uint16_t *lbuf;
uint8_t status_val; uint8_t status_val;
int b; int b;
if (!pc386_ide_status_data_ready (port, pc386_ide_timeout, if (!pc386_ide_status_data_ready (port, pc386_ide_timeout,
&status_val, pc386_ide_tasking_sleep)) &status_val, pc386_ide_tasking_sleep))
{ {
@@ -544,7 +544,7 @@ void pc386_ide_read_block
/* FIXME: add an error here. */ /* FIXME: add an error here. */
return; return;
} }
if (status_val & IDE_REGISTER_STATUS_ERR) if (status_val & IDE_REGISTER_STATUS_ERR)
{ {
inport_byte(port+IDE_REGISTER_ERROR, status_val); inport_byte(port+IDE_REGISTER_ERROR, status_val);
@@ -553,7 +553,7 @@ void pc386_ide_read_block
} }
lbuf = (uint16_t*)((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); lbuf = (uint16_t*)((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos));
for (b = 0; b < (ATA_SECTOR_SIZE / 2); b++) for (b = 0; b < (ATA_SECTOR_SIZE / 2); b++)
{ {
inport_word(port+IDE_REGISTER_DATA,*lbuf); inport_word(port+IDE_REGISTER_DATA,*lbuf);
@@ -614,7 +614,7 @@ void pc386_ide_write_block
uint16_t *lbuf; uint16_t *lbuf;
uint8_t status_val; uint8_t status_val;
int b; int b;
if (!pc386_ide_status_data_ready (port, pc386_ide_timeout, if (!pc386_ide_status_data_ready (port, pc386_ide_timeout,
&status_val, pc386_ide_tasking_sleep)) &status_val, pc386_ide_tasking_sleep))
{ {
@@ -623,16 +623,16 @@ void pc386_ide_write_block
/* FIXME: add an error here. */ /* FIXME: add an error here. */
return; return;
} }
if (status_val & IDE_REGISTER_STATUS_ERR) if (status_val & IDE_REGISTER_STATUS_ERR)
{ {
inport_byte(port+IDE_REGISTER_ERROR, status_val); inport_byte(port+IDE_REGISTER_ERROR, status_val);
printk ("pc386_ide_write_block: error: %02x\n", status_val); printk ("pc386_ide_write_block: error: %02x\n", status_val);
return; return;
} }
lbuf = (uint16_t*)(((uint8_t*)bufs[*cbuf].buffer) + (*pos)); lbuf = (uint16_t*)(((uint8_t*)bufs[*cbuf].buffer) + (*pos));
for (b = 0; b < (ATA_SECTOR_SIZE / 2); b++) for (b = 0; b < (ATA_SECTOR_SIZE / 2); b++)
{ {
#if PC386_IDE_DEBUG_OUT #if PC386_IDE_DEBUG_OUT

10
c/src/lib/libbsp/i386/pc386/ide/idecfg.c
View File

@@ -77,13 +77,13 @@ void bsp_ide_cmdline_init(void)
bool ide1 = IDE1_DEFAULT; bool ide1 = IDE1_DEFAULT;
bool ide2 = IDE2_DEFAULT; bool ide2 = IDE2_DEFAULT;
const char* ide; const char* ide;
/* /*
* Can have: * Can have:
* --ide=0,1 * --ide=0,1
*/ */
ide = bsp_cmdline_arg ("--ide="); ide = bsp_cmdline_arg ("--ide=");
if (ide) if (ide)
{ {
int i; int i;
@@ -91,9 +91,9 @@ void bsp_ide_cmdline_init(void)
* If a command line option exists remove the defaults. * If a command line option exists remove the defaults.
*/ */
ide1 = ide2 = false; ide1 = ide2 = false;
ide += sizeof ("--ide=") - 1; ide += sizeof ("--ide=") - 1;
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
{ {
switch (ide[i]) switch (ide[i])
@@ -133,7 +133,7 @@ void bsp_ide_cmdline_init(void)
* type information. * type information.
*/ */
ide = bsp_cmdline_arg ("--ide-show"); ide = bsp_cmdline_arg ("--ide-show");
if (ide) if (ide)
pc386_ide_show = true; pc386_ide_show = true;
} }

6
c/src/lib/libbsp/i386/pc386/start/start.S
View File

@@ -104,7 +104,7 @@ speakl: jmp speakl # and SPIN!!!
/* Save multiboot info if we detect a multiboot loader */ /* Save multiboot info if we detect a multiboot loader */
cmp $0x2badb002,eax cmp $0x2badb002,eax
jne 2f jne 2f
/* We have multiboot info; let's hope DS and ES are OK... */ /* We have multiboot info; let's hope DS and ES are OK... */
movl ebx, SYM(_boot_multiboot_info_p) movl ebx, SYM(_boot_multiboot_info_p)
/* Check for memory size info and save */ /* Check for memory size info and save */
@@ -231,7 +231,7 @@ SYM (zero_bss):
jne 1f jne 1f
movl $SYM (no_sse_msg), 0(esp) movl $SYM (no_sse_msg), 0(esp)
jmp SYM(_sse_panic) jmp SYM(_sse_panic)
1: 1:
#ifdef __SSE2__ #ifdef __SSE2__
testl $0x04000000, eax testl $0x04000000, eax
jne 1f jne 1f
@@ -301,7 +301,7 @@ SYM(_boot_multiboot_cmdline):
.rept 256 /* cmd line */ .rept 256 /* cmd line */
.byte 0 .byte 0
.endr .endr
PUBLIC(_stack_size) PUBLIC(_stack_size)
SYM(_stack_size): SYM(_stack_size):
.long STACK_SIZE .long STACK_SIZE

2
c/src/lib/libbsp/i386/pc386/startup/bspgetworkarea.c
View File

@@ -94,7 +94,7 @@ void bsp_size_memory(void)
break; break;
} }
} }
topAddr = (i-1)*1024*1024 - 4; topAddr = (i-1)*1024*1024 - 4;
} else { } else {
printk( "hardcoded\n" ); printk( "hardcoded\n" );

4
c/src/lib/libbsp/i386/pc386/startup/ldsegs.S
View File

@@ -222,7 +222,7 @@ SYM(Interrupt_descriptor_table):
.rept 256 .rept 256
.word 0,0,0,0 .word 0,0,0,0
.endr .endr
/*---------------------------------------------------------------------------+ /*---------------------------------------------------------------------------+
| Descriptor of IDT | Descriptor of IDT
+--------------------------------------------------------------------------*/ +--------------------------------------------------------------------------*/
@@ -231,7 +231,7 @@ SYM(Interrupt_descriptor_table):
SYM(idtdesc): SYM(idtdesc):
.word (256*8 - 1) .word (256*8 - 1)
.long SYM (Interrupt_descriptor_table) .long SYM (Interrupt_descriptor_table)
END_DATA END_DATA
.section .m_hdr .section .m_hdr

20
c/src/lib/libbsp/m32c/m32cbsp/start/start.S
View File

@@ -3,30 +3,30 @@
Copyright (c) 2005 Red Hat Incorporated. Copyright (c) 2005 Red Hat Incorporated.
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met: modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer. notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution. documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific or promote products derived from this software without specific
prior written permission. prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
@@ -34,7 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#warning The call is "void boot_card(const char* cmdline);" #warning The call is "void boot_card(const char* cmdline);"
#warning You need to pass a NULL. #warning You need to pass a NULL.
#warning Please check and remove these errors. #warning Please check and remove these errors.
#if defined(__r8c_cpu__) || defined(__m16c_cpu__) #if defined(__r8c_cpu__) || defined(__m16c_cpu__)
#define A16 #define A16
#define A(n,w) n #define A(n,w) n

18
c/src/lib/libbsp/m32c/m32cbsp/startup/crtn.S
View File

@@ -3,30 +3,30 @@
Copyright (c) 2005 Red Hat Incorporated. Copyright (c) 2005 Red Hat Incorporated.
All rights reserved. All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met: modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer. notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution. documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific or promote products derived from this software without specific
prior written permission. prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */

10
c/src/lib/libbsp/m32c/m32cbsp/timer/timer.c
View File

@@ -37,10 +37,10 @@ void benchmark_timer_initialize(void)
{ {
benchmark_timer_interrupts = 0; benchmark_timer_interrupts = 0;
_set_var_vect (timer_ra_interrupt, ivec_timer_a0); _set_var_vect (timer_ra_interrupt, ivec_timer_a0);
TA0MR = 0x00; TA0MR = 0x00;
TA0 = 0xffff; TA0 = 0xffff;
TA0IC = 0x05; TA0IC = 0x05;
TABSR = 0x55; TABSR = 0x55;
} }
uint32_t benchmark_timer_read(void) uint32_t benchmark_timer_read(void)
@@ -49,7 +49,7 @@ uint32_t benchmark_timer_read(void)
count = 0xFFFF - TA0; count = 0xFFFF - TA0;
count += benchmark_timer_interrupts * 0xFFFFL; count += benchmark_timer_interrupts * 0xFFFFL;
if (!benchmark_timer_find_average_overhead) { if (!benchmark_timer_find_average_overhead) {
if ( count > benchmark_timer_overhead ) if ( count > benchmark_timer_overhead )
count -= benchmark_timer_overhead; count -= benchmark_timer_overhead;

2
c/src/lib/libbsp/m32r/m32rsim/start/start.S
View File

@@ -25,7 +25,7 @@ _start:
add3 r2, r2, #low(__bss_start); R2 = start of BSS add3 r2, r2, #low(__bss_start); R2 = start of BSS
seth r3, #shigh(_end) seth r3, #shigh(_end)
add3 r3, r3, #low(_end) ; R3 = end of BSS + 1 add3 r3, r3, #low(_end) ; R3 = end of BSS + 1
sub r3, r2 ; R3 = BSS size in bytes sub r3, r2 ; R3 = BSS size in bytes
mv r4, r3 mv r4, r3
srli r4, #2 ; R4 = BSS size in longwords (rounded down) srli r4, #2 ; R4 = BSS size in longwords (rounded down)

6
c/src/lib/libbsp/nios2/nios2_iss/console/console.c
View File

@@ -1,6 +1,6 @@
/* /*
* This file implements simple console IO via JTAG UART. * This file implements simple console IO via JTAG UART.
* *
* Based on no_cpu/console.c * Based on no_cpu/console.c
* COPYRIGHT (c) 1989-1999. * COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR). * On-Line Applications Research Corporation (OAR).
@@ -25,7 +25,7 @@
/* is_character_ready /* is_character_ready
* *
* If a character is available, this routine reads it and stores * If a character is available, this routine reads it and stores
* it in * it in
* reads the character and stores * reads the character and stores
* *
* Input parameters: NONE * Input parameters: NONE
@@ -92,7 +92,7 @@ int console_inbyte_nonblocking(
*/ */
void console_outbyte_polled( void console_outbyte_polled(
int port, int port,
char ch char ch
) )
{ {

6
c/src/lib/libbsp/nios2/nios2_iss/timer/timer.c
View File

@@ -74,8 +74,8 @@ void benchmark_timer_initialize( void )
ALTERA_AVALON_TIMER_CONTROL_START_MSK; ALTERA_AVALON_TIMER_CONTROL_START_MSK;
/* This is the most safe place for resetting the overflow /* This is the most safe place for resetting the overflow
counter - just _after_ we reset the timer. Depending counter - just _after_ we reset the timer. Depending
on the SOPC configuration, the counter may not be on the SOPC configuration, the counter may not be
stoppable and it doesn't make sense to assume that stoppable and it doesn't make sense to assume that
there is any "safe" period before resetting. */ there is any "safe" period before resetting. */
@@ -129,7 +129,7 @@ int benchmark_timer_read( void )
if(total < LEAST_VALID) return 0; if(total < LEAST_VALID) return 0;
if(benchmark_timer_find_average_overhead != TRUE) total-= AVG_OVERHEAD; if(benchmark_timer_find_average_overhead != TRUE) total-= AVG_OVERHEAD;
return total; return total;
} }

2
c/src/lib/libbsp/sh/gensh1/start/start.S
View File

@@ -24,7 +24,7 @@
#warning Call to boot_card has changed and needs checking. #warning Call to boot_card has changed and needs checking.
#warning The call is "void boot_card(const char* cmdline);" #warning The call is "void boot_card(const char* cmdline);"
#warning Please check and remove these warnings. #warning Please check and remove these warnings.
BEGIN_CODE BEGIN_CODE
PUBLIC(start) PUBLIC(start)
SYM (start): SYM (start):

2
c/src/lib/libbsp/sh/gensh2/start/start.S
View File

@@ -35,7 +35,7 @@
#warning Call to boot_card has changed and needs checking. #warning Call to boot_card has changed and needs checking.
#warning The call is "void boot_card(const char* cmdline);" #warning The call is "void boot_card(const char* cmdline);"
#warning Please check and remove these warnings. #warning Please check and remove these warnings.
BEGIN_CODE BEGIN_CODE
PUBLIC(start) PUBLIC(start)

2
c/src/lib/libbsp/sh/gensh4/start/start.S
View File

@@ -43,7 +43,7 @@
#warning Call to boot_card has changed and needs checking. #warning Call to boot_card has changed and needs checking.
#warning The call is "void boot_card(const char* cmdline);" #warning The call is "void boot_card(const char* cmdline);"
#warning Please check and remove these warnings. #warning Please check and remove these warnings.
BEGIN_CODE BEGIN_CODE
PUBLIC(start) PUBLIC(start)

4
c/src/lib/libbsp/sh/shsim/start/start.S
View File

@@ -25,7 +25,7 @@
#warning The call is "void boot_card(const char* cmdline);" #warning The call is "void boot_card(const char* cmdline);"
#warning You need to pass a NULL. #warning You need to pass a NULL.
#warning Please check and remove these warnings. #warning Please check and remove these warnings.
BEGIN_CODE BEGIN_CODE
PUBLIC(start) PUBLIC(start)
SYM (start): SYM (start):
@@ -62,7 +62,7 @@ SYM (start):
mov #0,r4 ! command line mov #0,r4 ! command line
mov.l main_k,r0 mov.l main_k,r0
jsr @r0 jsr @r0
! call exit ! call exit
mov r0,r4 mov r0,r4

2
c/src/lib/libbsp/shared/bspclean.c
View File

@@ -37,5 +37,5 @@ void bsp_cleanup( void )
*/ */
#if (BSP_PRESS_KEY_FOR_RESET) || (BSP_RESET_BOARD_AT_EXIT) #if (BSP_PRESS_KEY_FOR_RESET) || (BSP_RESET_BOARD_AT_EXIT)
bsp_reset(); bsp_reset();
#endif #endif
} }

2
c/src/lib/libbsp/shared/bspgetworkarea.c
View File

@@ -68,7 +68,7 @@ void bsp_get_work_area(
* you are allocating the Work Area in a new BSP. * you are allocating the Work Area in a new BSP.
*/ */
#ifdef BSP_GET_WORK_AREA_DEBUG #ifdef BSP_GET_WORK_AREA_DEBUG
{ {
void *sp = __builtin_frame_address(0); void *sp = __builtin_frame_address(0);
void *end = *work_area_start + *work_area_size; void *end = *work_area_start + *work_area_size;
printk( printk(

8
c/src/lib/libbsp/shared/bspinit.c
View File

@@ -38,7 +38,7 @@ void Init (rtems_task_argument arg)
if (boot_cmdline) if (boot_cmdline)
{ {
cmdline = malloc (strlen (boot_cmdline) + 1); cmdline = malloc (strlen (boot_cmdline) + 1);
if (cmdline) if (cmdline)
{ {
strcpy (cmdline, boot_cmdline); strcpy (cmdline, boot_cmdline);
@@ -62,7 +62,7 @@ void Init (rtems_task_argument arg)
if (argv) if (argv)
{ {
int a; int a;
command = cmdline; command = cmdline;
argv[0] = command; argv[0] = command;
@@ -76,13 +76,13 @@ void Init (rtems_task_argument arg)
argc = 0; argc = 0;
} }
} }
#ifdef RTEMS_NETWORKING #ifdef RTEMS_NETWORKING
rtems_bsdnet_initialize_network (); rtems_bsdnet_initialize_network ();
#endif #endif
result = main (argc, argv); result = main (argc, argv);
free (argv); free (argv);
free (cmdline); free (cmdline);

2
c/src/lib/libbsp/shared/include/irq-config.h
View File

@@ -7,7 +7,7 @@
*/ */
/* /*
* Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
* *
* Copyright (c) 2008, 2009 * Copyright (c) 2008, 2009
* embedded brains GmbH * embedded brains GmbH

2
c/src/lib/libbsp/shared/include/irq-generic.h
View File

@@ -7,7 +7,7 @@
*/ */
/* /*
* Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
* *
* Copyright (c) 2008, 2009 * Copyright (c) 2008, 2009
* embedded brains GmbH * embedded brains GmbH

2
c/src/lib/libbsp/shared/include/stackalloc.h
View File

@@ -41,7 +41,7 @@ extern "C" {
* *
* @code * @code
* #include <bsp/stackalloc.h> * #include <bsp/stackalloc.h>
* *
* #define CONFIGURE_INIT * #define CONFIGURE_INIT
* *
* #include <confdefs.h> * #include <confdefs.h>

2
c/src/lib/libbsp/shared/src/irq-generic.c
View File

@@ -7,7 +7,7 @@
*/ */
/* /*
* Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
* *
* Copyright (c) 2008, 2009 * Copyright (c) 2008, 2009
* embedded brains GmbH * embedded brains GmbH

12
c/src/lib/libcpu/arm/at91rm9200/clock/clock.c
View File

@@ -34,7 +34,7 @@ static unsigned long st_pimr_reload;
static void clock_isr_on(const rtems_irq_connect_data *unused) static void clock_isr_on(const rtems_irq_connect_data *unused)
{ {
/* enable timer interrupt */ /* enable timer interrupt */
ST_REG(ST_IER) = ST_SR_PITS; ST_REG(ST_IER) = ST_SR_PITS;
} }
/** /**
@@ -58,13 +58,13 @@ static void clock_isr_off(const rtems_irq_connect_data *unused)
static int clock_isr_is_on(const rtems_irq_connect_data *irq) static int clock_isr_is_on(const rtems_irq_connect_data *irq)
{ {
/* check timer interrupt */ /* check timer interrupt */
return ST_REG(ST_IMR) & ST_SR_PITS; return ST_REG(ST_IMR) & ST_SR_PITS;
} }
rtems_isr Clock_isr(rtems_vector_number vector); rtems_isr Clock_isr(rtems_vector_number vector);
/* Replace the first value with the clock's interrupt name. */ /* Replace the first value with the clock's interrupt name. */
rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ, rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,
(rtems_irq_hdl)Clock_isr, (rtems_irq_hdl)Clock_isr,
clock_isr_on, clock_isr_on,
clock_isr_off, clock_isr_off,
@@ -88,11 +88,11 @@ void Clock_driver_support_initialize_hardware(void)
(((rtems_configuration_get_microseconds_per_tick() * slck) + (1000000/2))/ 1000000); (((rtems_configuration_get_microseconds_per_tick() * slck) + (1000000/2))/ 1000000);
st_pimr_reload = st_pimr_value; st_pimr_reload = st_pimr_value;
/* read the status to clear the int */ /* read the status to clear the int */
st_str = ST_REG(ST_SR); st_str = ST_REG(ST_SR);
/* set priority */ /* set priority */
AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7); AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
/* set the timer value */ /* set the timer value */
ST_REG(ST_PIMR) = st_pimr_reload; ST_REG(ST_PIMR) = st_pimr_reload;

46
c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c
View File

@@ -1,7 +1,7 @@
/* /*
* Console driver for AT91RM9200 DBGU port * Console driver for AT91RM9200 DBGU port
* *
* This driver uses the shared console driver in * This driver uses the shared console driver in
* ...../libbsp/shared/console.c * ...../libbsp/shared/console.c
* *
* Copyright (c) 2003 by Cogent Computer Systems * Copyright (c) 2003 by Cogent Computer Systems
@@ -38,8 +38,8 @@ static void dbgu_write_polled(int minor, char c);
static int dbgu_set_attributes(int minor, const struct termios *t); static int dbgu_set_attributes(int minor, const struct termios *t);
/* Pointers to functions for handling the UART. */ /* Pointers to functions for handling the UART. */
console_fns dbgu_fns = console_fns dbgu_fns =
{ {
libchip_serial_default_probe, libchip_serial_default_probe,
dbgu_first_open, dbgu_first_open,
dbgu_last_close, dbgu_last_close,
@@ -54,23 +54,23 @@ console_fns dbgu_fns =
/* Functions called via callbacks (i.e. the ones in uart_fns */ /* Functions called via callbacks (i.e. the ones in uart_fns */
/*********************************************************************/ /*********************************************************************/
/* /*
* This is called the first time each device is opened. Since * This is called the first time each device is opened. Since
* the driver is polled, we don't have to do anything. If the driver * the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd enable interrupts here. * were interrupt driven, we'd enable interrupts here.
*/ */
static int dbgu_first_open(int major, int minor, void *arg) static int dbgu_first_open(int major, int minor, void *arg)
{ {
return 0; return 0;
} }
/* /*
* This is called the last time each device is closed. Since * This is called the last time each device is closed. Since
* the driver is polled, we don't have to do anything. If the driver * the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd disable interrupts here. * were interrupt driven, we'd disable interrupts here.
*/ */
static int dbgu_last_close(int major, int minor, void *arg) static int dbgu_last_close(int major, int minor, void *arg)
{ {
return 0; return 0;
} }
@@ -82,7 +82,7 @@ static int dbgu_last_close(int major, int minor, void *arg)
* return -1 if there's no data, otherwise return * return -1 if there's no data, otherwise return
* the character in lowest 8 bits of returned int. * the character in lowest 8 bits of returned int.
*/ */
static int dbgu_read(int minor) static int dbgu_read(int minor)
{ {
char c; char c;
console_tbl *console_entry; console_tbl *console_entry;
@@ -99,15 +99,15 @@ static int dbgu_read(int minor)
if (!(dbgu->sr & DBGU_INT_RXRDY)) { if (!(dbgu->sr & DBGU_INT_RXRDY)) {
return -1; return -1;
} }
c = dbgu->rhr & 0xff; c = dbgu->rhr & 0xff;
return c; return c;
} }
/* /*
* Write buffer to UART * Write buffer to UART
* *
* return 1 on success, -1 on error * return 1 on success, -1 on error
*/ */
@@ -133,17 +133,17 @@ static int dbgu_write(int minor, const char *buf, int len)
break; break;
} }
} }
c = (char) buf[i]; c = (char) buf[i];
dbgu->thr = c; dbgu->thr = c;
/* the TXRDY flag does not seem to update right away (is this true?) */ /* the TXRDY flag does not seem to update right away (is this true?) */
/* so we wait a bit before continuing */ /* so we wait a bit before continuing */
for (x = 0; x < 100; x++) { for (x = 0; x < 100; x++) {
dbg_dly++; /* using a global so this doesn't get optimized out */ dbg_dly++; /* using a global so this doesn't get optimized out */
} }
} }
return 1; return 1;
} }
@@ -186,7 +186,7 @@ static void dbgu_write_polled(int minor, char c)
} }
/* This is for setting baud rate, bits, etc. */ /* This is for setting baud rate, bits, etc. */
static int dbgu_set_attributes(int minor, const struct termios *t) static int dbgu_set_attributes(int minor, const struct termios *t)
{ {
return 0; return 0;
} }
@@ -197,7 +197,7 @@ static int dbgu_set_attributes(int minor, const struct termios *t)
* functions use them instead. * functions use them instead.
*/ */
/***********************************************************************/ /***********************************************************************/
/* /*
* Read from UART. This is used in the exit code, and can't * Read from UART. This is used in the exit code, and can't
* rely on interrupts. * rely on interrupts.
*/ */
@@ -208,7 +208,7 @@ int dbgu_poll_read(int minor)
/* /*
* Write a character to the console. This is used by printk() and * Write a character to the console. This is used by printk() and
* maybe other low level functions. It should not use interrupts or any * maybe other low level functions. It should not use interrupts or any
* RTEMS system calls. It needs to be very simple * RTEMS system calls. It needs to be very simple
*/ */

10
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h
View File

@@ -32,7 +32,7 @@ typedef volatile unsigned long vulong;
#define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c)) #define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
/* Control Register - 32 of them */ /* Control Register - 32 of them */
#define AIC_CTL_BASE 0xFFFFF100 #define AIC_CTL_BASE 0xFFFFF100
#define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f)) #define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
/* Register Offsets */ /* Register Offsets */
@@ -103,9 +103,9 @@ typedef volatile unsigned long vulong;
/* AIC_SMR */ /* AIC_SMR */
#define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0) #define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0)
#define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */ #define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */
#define AIC_SMR_SRC_EDGE_LOW (1 << 5) #define AIC_SMR_SRC_EDGE_LOW (1 << 5)
#define AIC_SMR_SRC_LVL_HI (2 << 5) #define AIC_SMR_SRC_LVL_HI (2 << 5)
#define AIC_SMR_SRC_EDGE_HI (3 << 5) #define AIC_SMR_SRC_EDGE_HI (3 << 5)
/**************************************************************************/ /**************************************************************************/
/* Debug Unit */ /* Debug Unit */
@@ -192,7 +192,7 @@ typedef volatile unsigned long vulong;
* Note that each of the following peripherals has it's own * Note that each of the following peripherals has it's own
* set of these registers starting at offset 0x100 from it's * set of these registers starting at offset 0x100 from it's
* base address: DBGU, SPI, USART and SSC * base address: DBGU, SPI, USART and SSC
* To access the DMA for a peripheral, use the macro for that * To access the DMA for a peripheral, use the macro for that
* peripheral but with these register offsets * peripheral but with these register offsets
**************************************************************************/ **************************************************************************/
/* Register Offsets */ /* Register Offsets */

2
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2003 by Cogent Computer Systems * Copyright (c) 2003 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com> * Written by Mike Kelly <mike@cogcomp.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *

6
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2003 by Cogent Computer Systems * Copyright (c) 2003 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com> * Written by Mike Kelly <mike@cogcomp.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -104,7 +104,7 @@
#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ #define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */
#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ #define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */
#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ #define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */
/* Receive Status Register, EMAC_RSR, Offset 0x20 */ /* Receive Status Register, EMAC_RSR, Offset 0x20 */
#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ #define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */
#define EMAC_RSR_REC BIT1 /* 1 = Frame received */ #define EMAC_RSR_REC BIT1 /* 1 = Frame received */
@@ -137,7 +137,7 @@
#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ #define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */
#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ #define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */
#define EMAC_MAN_HIGH BIT30 /* Must be set */ #define EMAC_MAN_HIGH BIT30 /* Must be set */
#define EMAC_MAN_LOW BIT31 #define EMAC_MAN_LOW BIT31
/* /*
* Bit assignments for Receive Buffer Descriptor * Bit assignments for Receive Buffer Descriptor

86
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2002 by Cogent Computer Systems * Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com> * Written by Mike Kelly <mike@cogcomp.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -59,16 +59,16 @@
* *
* PORT A * PORT A
*/ */
#define GPIO_0 BIT0 #define GPIO_0 BIT0
#define GPIO_1 BIT1 #define GPIO_1 BIT1
#define GPIO_2 BIT2 #define GPIO_2 BIT2
#define GPIO_3 BIT3 #define GPIO_3 BIT3
#define GPIO_4 BIT4 #define GPIO_4 BIT4
#define GPIO_5 BIT5 #define GPIO_5 BIT5
#define GPIO_6 BIT6 #define GPIO_6 BIT6
#define GPIO_7 BIT7 #define GPIO_7 BIT7
#define GPIO_8 BIT8 #define GPIO_8 BIT8
#define GPIO_9 BIT9 #define GPIO_9 BIT9
#define GPIO_10 BIT10 #define GPIO_10 BIT10
#define GPIO_11 BIT11 #define GPIO_11 BIT11
#define GPIO_12 BIT12 #define GPIO_12 BIT12
@@ -92,16 +92,16 @@
#define GPIO_30 BIT30 #define GPIO_30 BIT30
#define GPIO_31 BIT31 #define GPIO_31 BIT31
/* PORT B */ /* PORT B */
#define GPIO_32 BIT0 #define GPIO_32 BIT0
#define GPIO_33 BIT1 #define GPIO_33 BIT1
#define GPIO_34 BIT2 #define GPIO_34 BIT2
#define GPIO_35 BIT3 #define GPIO_35 BIT3
#define GPIO_36 BIT4 #define GPIO_36 BIT4
#define GPIO_37 BIT5 #define GPIO_37 BIT5
#define GPIO_38 BIT6 #define GPIO_38 BIT6
#define GPIO_39 BIT7 #define GPIO_39 BIT7
#define GPIO_40 BIT8 #define GPIO_40 BIT8
#define GPIO_41 BIT9 #define GPIO_41 BIT9
#define GPIO_42 BIT10 #define GPIO_42 BIT10
#define GPIO_43 BIT11 #define GPIO_43 BIT11
#define GPIO_44 BIT12 #define GPIO_44 BIT12
@@ -125,16 +125,16 @@
#define GPIO_62 BIT30 #define GPIO_62 BIT30
#define GPIO_63 BIT31 #define GPIO_63 BIT31
/* PORT C */ /* PORT C */
#define GPIO_64 BIT0 #define GPIO_64 BIT0
#define GPIO_65 BIT1 #define GPIO_65 BIT1
#define GPIO_66 BIT2 #define GPIO_66 BIT2
#define GPIO_67 BIT3 #define GPIO_67 BIT3
#define GPIO_68 BIT4 #define GPIO_68 BIT4
#define GPIO_69 BIT5 #define GPIO_69 BIT5
#define GPIO_70 BIT6 #define GPIO_70 BIT6
#define GPIO_71 BIT7 #define GPIO_71 BIT7
#define GPIO_72 BIT8 #define GPIO_72 BIT8
#define GPIO_73 BIT9 #define GPIO_73 BIT9
#define GPIO_74 BIT10 #define GPIO_74 BIT10
#define GPIO_75 BIT11 #define GPIO_75 BIT11
#define GPIO_76 BIT12 #define GPIO_76 BIT12
@@ -158,16 +158,16 @@
#define GPIO_94 BIT30 #define GPIO_94 BIT30
#define GPIO_95 BIT31 #define GPIO_95 BIT31
/* PORT D */ /* PORT D */
#define GPIO_96 BIT0 #define GPIO_96 BIT0
#define GPIO_97 BIT1 #define GPIO_97 BIT1
#define GPIO_98 BIT2 #define GPIO_98 BIT2
#define GPIO_99 BIT3 #define GPIO_99 BIT3
#define GPIO_100 BIT4 #define GPIO_100 BIT4
#define GPIO_101 BIT5 #define GPIO_101 BIT5
#define GPIO_102 BIT6 #define GPIO_102 BIT6
#define GPIO_103 BIT7 #define GPIO_103 BIT7
#define GPIO_104 BIT8 #define GPIO_104 BIT8
#define GPIO_105 BIT9 #define GPIO_105 BIT9
#define GPIO_106 BIT10 #define GPIO_106 BIT10
#define GPIO_107 BIT11 #define GPIO_107 BIT11
#define GPIO_108 BIT12 #define GPIO_108 BIT12
@@ -376,9 +376,9 @@
#define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */ #define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */
#define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */ #define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */
#define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */ #define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */
/* Port D, Alternate Function B */ /* Port D, Alternate Function B */
#define PIOC_ASR_TSYNC BIT7 /* ETM Sync */ #define PIOC_ASR_TSYNC BIT7 /* ETM Sync */
#define PIOC_ASR_TCLK BIT8 /* ETM Clock */ #define PIOC_ASR_TCLK BIT8 /* ETM Clock */
#define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */ #define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */

2
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2002 by Cogent Computer Systems * Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com> * Written by Mike Kelly <mike@cogcomp.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *

2
c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2002 by Cogent Computer Systems * Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com> * Written by Mike Kelly <mike@cogcomp.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *

2
c/src/lib/libcpu/arm/at91rm9200/include/bits.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2002 by Cogent Computer Systems * Copyright (c) 2002 by Cogent Computer Systems
* Written by Mike Kelly <mike@cogcomp.com> * Written by Mike Kelly <mike@cogcomp.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *

8
c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 Interrupt handler * Atmel AT91RM9200 Interrupt handler
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -12,7 +12,7 @@
* $Id$ * $Id$
*/ */
#define __asm__ #define __asm__
.globl bsp_interrupt_dispatch .globl bsp_interrupt_dispatch
bsp_interrupt_dispatch : bsp_interrupt_dispatch :
/* /*
@@ -21,7 +21,7 @@ bsp_interrupt_dispatch :
* and load vector into r0 and handler address into r1. * and load vector into r0 and handler address into r1.
*/ */
ldr r0, =0xFFFFF100 /* AIC_CTL_BASE + AIC_IVR */ ldr r0, =0xFFFFF100 /* AIC_CTL_BASE + AIC_IVR */
ldr r1, [r0] ldr r1, [r0]
str r1, [r0] /* write back in case we are using protect */ str r1, [r0] /* write back in case we are using protect */
ldr r0, =0xFFFFF108 /* AIC_CTL_BASE + AIC_ISR */ ldr r0, =0xFFFFF108 /* AIC_CTL_BASE + AIC_ISR */
@@ -35,7 +35,7 @@ bsp_interrupt_dispatch :
IRQ_return: IRQ_return:
ldr r2, =0xFFFFF130 /* AIC_CTL_BASE + AIC_EIOCR */ ldr r2, =0xFFFFF130 /* AIC_CTL_BASE + AIC_EIOCR */
str r1, [r2] str r1, [r2]
ldmia sp!,{lr} ldmia sp!,{lr}
mov pc, lr mov pc, lr

6
c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 Interrupt handler * Atmel AT91RM9200 Interrupt handler
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -17,8 +17,8 @@
extern void default_int_handler(void); extern void default_int_handler(void);
/* /*
* Interrupt system initialization. Disable interrupts, clear * Interrupt system initialization. Disable interrupts, clear
* any that are pending. * any that are pending.
*/ */
void BSP_rtems_irq_mngt_init(void) void BSP_rtems_irq_mngt_init(void)

34
c/src/lib/libcpu/arm/at91rm9200/irq/irq.c
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 Interrupt handler * Atmel AT91RM9200 Interrupt handler
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -34,52 +34,52 @@ static int isValidInterrupt(int irq)
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
/* /*
* Check if default handler is actually connected. If not, issue * Check if default handler is actually connected. If not, issue
* an error. Note: irq->name is a number corresponding to the * an error. Note: irq->name is a number corresponding to the
* sources PID (see the at91rm9200_pid for this mapping). We * sources PID (see the at91rm9200_pid for this mapping). We
* convert it to a long word offset to get source's vector register * convert it to a long word offset to get source's vector register
*/ */
if (AIC_SVR_REG(irq->name * 4) != (uint32_t) default_int_handler) { if (AIC_SVR_REG(irq->name * 4) != (uint32_t) default_int_handler) {
return 0; return 0;
} }
rtems_interrupt_disable(level); rtems_interrupt_disable(level);
/* /*
* store the new handler * store the new handler
*/ */
AIC_SVR_REG(irq->name * 4) = (uint32_t) irq->hdl; AIC_SVR_REG(irq->name * 4) = (uint32_t) irq->hdl;
/* /*
* unmask interrupt * unmask interrupt
*/ */
AIC_CTL_REG(AIC_IECR) = 1 << irq->name; AIC_CTL_REG(AIC_IECR) = 1 << irq->name;
/* /*
* Enable interrupt on device * Enable interrupt on device
*/ */
if(irq->on) { if(irq->on) {
irq->on(irq); irq->on(irq);
} }
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 1; return 1;
} }
/* /*
* Remove and interrupt handler * Remove and interrupt handler
*/ */
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -96,7 +96,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* mask interrupt * mask interrupt
*/ */
AIC_CTL_REG(AIC_IDCR) = 1 << irq->name; AIC_CTL_REG(AIC_IDCR) = 1 << irq->name;
/* /*
* Disable interrupt on device * Disable interrupt on device
*/ */
@@ -108,7 +108,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value * restore the default irq value
*/ */
AIC_SVR_REG(irq->name * 4) = (uint32_t) default_int_handler; AIC_SVR_REG(irq->name * 4) = (uint32_t) default_int_handler;
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 1; return 1;

10
c/src/lib/libcpu/arm/at91rm9200/irq/irq.h
View File

@@ -2,7 +2,7 @@
* Interrupt handler Header file * Interrupt handler Header file
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -24,7 +24,7 @@ extern "C" {
/* /*
* Include some preprocessor value also used by assember code * Include some preprocessor value also used by assember code
*/ */
#include <rtems.h> #include <rtems.h>
#include <at91rm9200.h> #include <at91rm9200.h>
@@ -35,7 +35,7 @@ extern void default_int_handler();
/* possible interrupt sources on the AT91RM9200 */ /* possible interrupt sources on the AT91RM9200 */
#define AT91RM9200_INT_FIQ 0 #define AT91RM9200_INT_FIQ 0
#define AT91RM9200_INT_SYSIRQ 1 #define AT91RM9200_INT_SYSIRQ 1
#define AT91RM9200_INT_PIOA 2 #define AT91RM9200_INT_PIOA 2
#define AT91RM9200_INT_PIOB 3 #define AT91RM9200_INT_PIOB 3
#define AT91RM9200_INT_PIOC 4 #define AT91RM9200_INT_PIOC 4
#define AT91RM9200_INT_PIOD 5 #define AT91RM9200_INT_PIOD 5
@@ -71,7 +71,7 @@ extern void default_int_handler();
/* we can treat the AT91RM9200 AIC_SVR_BASE as */ /* we can treat the AT91RM9200 AIC_SVR_BASE as */
/* a vector table */ /* a vector table */
#define VECTOR_TABLE AIC_SVR_BASE #define VECTOR_TABLE AIC_SVR_BASE
typedef unsigned char rtems_irq_level; typedef unsigned char rtems_irq_level;
typedef unsigned char rtems_irq_trigger; typedef unsigned char rtems_irq_trigger;
@@ -117,7 +117,7 @@ void BSP_rtems_irq_mngt_init();
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
/* /*
* function to get the current RTEMS irq handler for ptr->name. * function to get the current RTEMS irq handler for ptr->name.
*/ */
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);

2
c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c
View File

@@ -2,7 +2,7 @@
* Atmel AT91RM9200 PMC functions * Atmel AT91RM9200 PMC functions
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *

6
c/src/lib/libcpu/arm/at91rm9200/timer/timer.c
View File

@@ -4,7 +4,7 @@
* This uses timer 0 for timing measurments. * This uses timer 0 for timing measurments.
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -16,7 +16,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted. * the number of microseconds since benchmark_timer_initialize() exitted.
* *
* It is important that the timer start/stop overhead be determined * It is important that the timer start/stop overhead be determined
* when porting or modifying this code. * when porting or modifying this code.
* *
* $Id$ * $Id$
@@ -31,7 +31,7 @@ uint16_t tstart;
bool benchmark_timer_find_average_overhead; bool benchmark_timer_find_average_overhead;
uint32_t tick_time; uint32_t tick_time;
/* /*
* Set up TC0 - * Set up TC0 -
* timer_clock2 (MCK/8) * timer_clock2 (MCK/8)
* capture mode - this shouldn't matter * capture mode - this shouldn't matter
*/ */

12
c/src/lib/libcpu/arm/at91rm9200/usart/usart.c
View File

@@ -1,10 +1,10 @@
/* /*
* Driver for AT91RM9200 USART ports * Driver for AT91RM9200 USART ports
* *
* COPYRIGHT (c) 2006-2009. * COPYRIGHT (c) 2006-2009.
* NCB - Sistemas Embarcados Ltda. (Brazil) * NCB - Sistemas Embarcados Ltda. (Brazil)
* Fernando Nicodemos <fgnicodemos@terra.com.br> * Fernando Nicodemos <fgnicodemos@terra.com.br>
* *
* and * and
* *
* COPYRIGHT (c) 1989-2009. * COPYRIGHT (c) 1989-2009.
@@ -60,7 +60,7 @@ at91rm9200_usart_regs_t *usart_get_base(int minor)
if (console_entry == NULL) if (console_entry == NULL)
return 0; return 0;
port = (at91rm9200_usart_regs_t *) console_entry->ulCtrlPort1; port = (at91rm9200_usart_regs_t *) console_entry->ulCtrlPort1;
//printk( "minor=%d entry=%p port=%p\n", minor, console_entry, port ); //printk( "minor=%d entry=%p port=%p\n", minor, console_entry, port );
@@ -241,11 +241,11 @@ static int usart_set_attributes(int minor, const struct termios *t)
mode |= US_MR_PAR_NONE; mode |= US_MR_PAR_NONE;
baud_requested = t->c_cflag & CBAUD; baud_requested = t->c_cflag & CBAUD;
/* If not, set the dbgu console baud as USART baud default */ /* If not, set the dbgu console baud as USART baud default */
if (!baud_requested) if (!baud_requested)
baud_requested = BSP_get_baud(); baud_requested = BSP_get_baud();
baud = rtems_termios_baud_to_number(baud_requested); baud = rtems_termios_baud_to_number(baud_requested);
brgr = (at91rm9200_get_mck() / 16) / baud; brgr = (at91rm9200_get_mck() / 16) / baud;

20
c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c
View File

@@ -35,7 +35,7 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
3, /* unused for ARM cpus */ 3, /* unused for ARM cpus */
0 }; /* unused for ARM cpus */ 0 }; /* unused for ARM cpus */
/* If you follow the code, this is never used, so any value /* If you follow the code, this is never used, so any value
* should work * should work
*/ */
#define CLOCK_VECTOR 0 #define CLOCK_VECTOR 0
@@ -72,16 +72,16 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
* - enable it * - enable it
* - clear any pending interrupts * - clear any pending interrupts
* *
* Since you may want the clock always running, you can * Since you may want the clock always running, you can
* enable interrupts here. If you do so, the clock_isr_on(), * enable interrupts here. If you do so, the clock_isr_on(),
* clock_isr_off(), and clock_isr_is_on() functions can be * clock_isr_off(), and clock_isr_is_on() functions can be
* NOPs. * NOPs.
*/ */
/* set timer to generate interrupt every rtems_configuration_get_microseconds_per_tick() /* set timer to generate interrupt every rtems_configuration_get_microseconds_per_tick()
* MR0/(LPC22xx_Fpclk/(PR0+1)) = 10/1000 = 0.01s * MR0/(LPC22xx_Fpclk/(PR0+1)) = 10/1000 = 0.01s
*/ */
#define Clock_driver_support_initialize_hardware() \ #define Clock_driver_support_initialize_hardware() \
do { \ do { \
T0TCR &= 0; /* disable and clear timer 0, set to */ \ T0TCR &= 0; /* disable and clear timer 0, set to */ \
@@ -95,7 +95,7 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
} while (0) } while (0)
/** /**
* Do whatever you need to shut the clock down and remove the * Do whatever you need to shut the clock down and remove the
* interrupt handler. Since this normally only gets called on * interrupt handler. Since this normally only gets called on
* RTEMS shutdown, you may not need to do anything other than * RTEMS shutdown, you may not need to do anything other than
* remove the ISR. * remove the ISR.
@@ -110,12 +110,12 @@ rtems_irq_connect_data clock_isr_data = {LPC22xx_INTERRUPT_TIMER0,
uint32_t bsp_clock_nanoseconds_since_last_tick(void) uint32_t bsp_clock_nanoseconds_since_last_tick(void)
{ {
uint32_t clicks; uint32_t clicks;
clicks = T0TC; /*T0TC is the 32bit time counter 0*/ clicks = T0TC; /*T0TC is the 32bit time counter 0*/
return (uint32_t) (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000; return (uint32_t) (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000;
} }
#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick #define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick

6
c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h
View File

@@ -2,7 +2,7 @@
* Philips LPC22XX/LPC21xx Register definitions * Philips LPC22XX/LPC21xx Register definitions
* *
* Copyright (c) 2006 by Ray <rayx.cn@gmail.com> * Copyright (c) 2006 by Ray <rayx.cn@gmail.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -318,7 +318,7 @@
#define CAN5TDA3 (*((volatile unsigned long *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDA3 (*((volatile unsigned long *) 0xE0054058)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */
#define CAN5TDB3 (*((volatile unsigned long *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */ #define CAN5TDB3 (*((volatile unsigned long *) 0xE005405C)) /* lpc2119\lpc2129\lpc2292\lpc2294 only */
#ifdef CONFIG_ARCH_LPC22xx #ifdef CONFIG_ARCH_LPC22xx
#define CAN6MOD (*((volatile unsigned long *) 0xE0058000)) /* lpc2292\lpc2294 only */ #define CAN6MOD (*((volatile unsigned long *) 0xE0058000)) /* lpc2292\lpc2294 only */
#define CAN6CMR (*((volatile unsigned long *) 0xE0058004)) /* lpc2292\lpc2294 only */ #define CAN6CMR (*((volatile unsigned long *) 0xE0058004)) /* lpc2292\lpc2294 only */
#define CAN6GSR (*((volatile unsigned long *) 0xE0058008)) /* lpc2292\lpc2294 only */ #define CAN6GSR (*((volatile unsigned long *) 0xE0058008)) /* lpc2292\lpc2294 only */
@@ -455,7 +455,7 @@
/* /*
Register define for constant Register define for constant
*/ */
#define REG_U0RBR 0xE000C000 #define REG_U0RBR 0xE000C000
#define REG_U1RBR 0xE0010000 #define REG_U1RBR 0xE0010000

6
c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S
View File

@@ -12,8 +12,8 @@
* $Id$ * $Id$
*/ */
#define __asm__ #define __asm__
/* /*
* BSP specific interrupt handler for INT or FIQ. In here * BSP specific interrupt handler for INT or FIQ. In here
* you do determine which interrupt happened and call its * you do determine which interrupt happened and call its
* handler. * handler.
@@ -30,7 +30,7 @@ bsp_interrupt_dispatch :
* From source, determine offset into expanded vector table * From source, determine offset into expanded vector table
* and load handler address into r0. * and load handler address into r0.
*/ */
ldr r0, =0xFFFFF030 /* Read the vector number */ ldr r0, =0xFFFFF030 /* Read the vector number */
ldr r0, [r0] ldr r0, [r0]
#ifdef __thumb__ #ifdef __thumb__

12
c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c
View File

@@ -1,6 +1,6 @@
/* /*
* NXP/Philips LPC22XX/LPC21xx Interrupt handler * NXP/Philips LPC22XX/LPC21xx Interrupt handler
* Ray 2007 <rayx.cn@gmail.com> to support LPC ARM * Ray 2007 <rayx.cn@gmail.com> to support LPC ARM
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -16,8 +16,8 @@
extern void default_int_handler(void); extern void default_int_handler(void);
/* /*
* Interrupt system initialization. Disable interrupts, clear * Interrupt system initialization. Disable interrupts, clear
* any that are pending. * any that are pending.
*/ */
void BSP_rtems_irq_mngt_init(void) void BSP_rtems_irq_mngt_init(void)
@@ -33,7 +33,7 @@ void BSP_rtems_irq_mngt_init(void)
for (i=0; i<BSP_MAX_INT; i++) { for (i=0; i<BSP_MAX_INT; i++) {
*(vectorTable + i) = (long)(default_int_handler); *(vectorTable + i) = (long)(default_int_handler);
} }
/* /*
* Set IRQHandler * Set IRQHandler
*/ */
@@ -56,10 +56,10 @@ void BSP_rtems_irq_mngt_init(void)
* In case we must find an ABORT error, * In case we must find an ABORT error,
* enable the next lines and set a breakpoint * enable the next lines and set a breakpoint
* in ABORTHandler. * in ABORTHandler.
*/ */
#if 1 #if 1
DATA_ABORT_VECTOR_ADDR = 0xE59FF018; DATA_ABORT_VECTOR_ADDR = 0xE59FF018;
#endif #endif
/* /*
* Init the Vectored Interrupt Controller (VIC) * Init the Vectored Interrupt Controller (VIC)

20
c/src/lib/libcpu/arm/lpc22xx/irq/irq.c
View File

@@ -1,7 +1,7 @@
/* /*
* Philps LPC22XX Interrupt handler * Philps LPC22XX Interrupt handler
* *
* Copyright (c) 2006 by Ray<rayx.cn@gmail.com> to support LPC ARM * Copyright (c) 2006 by Ray<rayx.cn@gmail.com> to support LPC ARM
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -37,11 +37,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_interrupt_level level; rtems_interrupt_level level;
rtems_irq_hdl *bsp_tbl; rtems_irq_hdl *bsp_tbl;
int *vic_cntl; int *vic_cntl;
bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase; bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase;
vic_cntl=(int *)VICVectCntlBase; vic_cntl=(int *)VICVectCntlBase;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -66,8 +66,8 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
*/ */
vic_cntl[irq->name] = 0x20 | irq->name; vic_cntl[irq->name] = 0x20 | irq->name;
VICIntEnable |= 1 << irq->name; VICIntEnable |= 1 << irq->name;
if(irq->on) if(irq->on)
{ {
irq->on(irq); irq->on(irq);
@@ -75,11 +75,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 1; return 1;
} }
/* /*
* Remove and interrupt handler * Remove and interrupt handler
* *
* You should only have to add the code to mask the interrupt. * You should only have to add the code to mask the interrupt.
@@ -91,7 +91,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_irq_hdl *bsp_tbl; rtems_irq_hdl *bsp_tbl;
bsp_tbl = (rtems_irq_hdl *)&VICVectAddr0; bsp_tbl = (rtems_irq_hdl *)&VICVectAddr0;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -116,7 +116,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value * restore the default irq value
*/ */
bsp_tbl[irq->name] = default_int_handler; bsp_tbl[irq->name] = default_int_handler;
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 1; return 1;

14
c/src/lib/libcpu/arm/lpc22xx/irq/irq.h
View File

@@ -1,8 +1,8 @@
/* /*
* Interrupt handler Header file * Interrupt handler Header file
* *
* Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -25,7 +25,7 @@ extern "C" {
/* /*
* Include some preprocessor value also used by assember code * Include some preprocessor value also used by assember code
*/ */
#include <rtems.h> #include <rtems.h>
#include <lpc22xx.h> #include <lpc22xx.h>
@@ -66,7 +66,7 @@ extern void default_int_handler();
#define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */ #define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */
#define BSP_MAX_INT 28 #define BSP_MAX_INT 28
#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) #define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L)
#define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L) #define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L)
#define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL) #define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL)
#define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L) #define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L)
@@ -77,7 +77,7 @@ extern void default_int_handler();
#define IRQ_ISR_ADDR (*(u_long *)0x00000038L) #define IRQ_ISR_ADDR (*(u_long *)0x00000038L)
#define FIQ_ISR_ADDR (*(u_long *)0x0000003CL) #define FIQ_ISR_ADDR (*(u_long *)0x0000003CL)
typedef unsigned char rtems_irq_level; typedef unsigned char rtems_irq_level;
typedef unsigned char rtems_irq_trigger; typedef unsigned char rtems_irq_trigger;
@@ -91,7 +91,7 @@ typedef int (*rtems_irq_is_enabled)(const struct __rtems_irq_connect_data__*);
//extern rtems_irq_hdl bsp_vector_table[BSP_MAX_INT]; //extern rtems_irq_hdl bsp_vector_table[BSP_MAX_INT];
#define VECTOR_TABLE VICVectAddrBase #define VECTOR_TABLE VICVectAddrBase
typedef struct __rtems_irq_connect_data__ { typedef struct __rtems_irq_connect_data__ {
/* IRQ line */ /* IRQ line */
rtems_irq_number name; rtems_irq_number name;
@@ -127,7 +127,7 @@ void BSP_rtems_irq_mngt_init();
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
/* /*
* function to get the current RTEMS irq handler for ptr->name. * function to get the current RTEMS irq handler for ptr->name.
*/ */
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);

8
c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h
View File

@@ -11,16 +11,16 @@
#define TCR_ENABLE_BIT 0 #define TCR_ENABLE_BIT 0
#define TCR_RESET_BIT 1 #define TCR_RESET_BIT 1
// The channel name which is used in matching, in fact they represent // The channel name which is used in matching, in fact they represent
// corresponding Match Register // corresponding Match Register
#define CH_MAXNUM 4 #define CH_MAXNUM 4
#define CH0 0 #define CH0 0
#define CH1 1 #define CH1 1
#define CH2 2 #define CH2 2
#define CH3 3 #define CH3 3
// The channel name which is used in capturing, in fact they represent // The channel name which is used in capturing, in fact they represent
// corresponding Capture Register // corresponding Capture Register
#define CPCH_MAXNUM 4 #define CPCH_MAXNUM 4
#define CPCH0 0 #define CPCH0 0
#define CPCH1 1 #define CPCH1 1

6
c/src/lib/libcpu/arm/lpc22xx/timer/timer.c
View File

@@ -2,7 +2,7 @@
* RTL22xx board Timer driver * RTL22xx board Timer driver
* *
* This uses Timer1 for timing measurments. * This uses Timer1 for timing measurments.
* *
* By Ray xu<rayx.cn@gmail.com>, modify form Mc9328mxl RTEMS DSP * By Ray xu<rayx.cn@gmail.com>, modify form Mc9328mxl RTEMS DSP
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
@@ -16,7 +16,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted. * the number of microseconds since benchmark_timer_initialize() exitted.
* *
* It is important that the timer start/stop overhead be determined * It is important that the timer start/stop overhead be determined
* when porting or modifying this code. * when porting or modifying this code.
* *
* $Id$ * $Id$
@@ -31,7 +31,7 @@ uint32_t g_freq;
bool benchmark_timer_find_average_overhead; bool benchmark_timer_find_average_overhead;
/* /*
* Set up Timer 1 * Set up Timer 1
*/ */

10
c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c
View File

@@ -37,12 +37,12 @@ rtems_irq_connect_data clock_isr_data = {
.isOn = clock_isr_is_on, .isOn = clock_isr_is_on,
}; };
/* If you follow the code, this is never used, so any value /* If you follow the code, this is never used, so any value
* should work * should work
*/ */
#define CLOCK_VECTOR 0 #define CLOCK_VECTOR 0
/** /**
* When we get the clock interrupt * When we get the clock interrupt
* - clear the interrupt bit? * - clear the interrupt bit?
@@ -72,9 +72,9 @@ rtems_irq_connect_data clock_isr_data = {
* - enable it * - enable it
* - clear any pending interrupts * - clear any pending interrupts
* *
* Since you may want the clock always running, you can * Since you may want the clock always running, you can
* enable interrupts here. If you do so, the clock_isr_on(), * enable interrupts here. If you do so, the clock_isr_on(),
* clock_isr_off(), and clock_isr_is_on() functions can be * clock_isr_off(), and clock_isr_is_on() functions can be
* NOPs. * NOPs.
*/ */
#define Clock_driver_support_initialize_hardware() \ #define Clock_driver_support_initialize_hardware() \
@@ -95,7 +95,7 @@ rtems_irq_connect_data clock_isr_data = {
} while (0) } while (0)
/** /**
* Do whatever you need to shut the clock down and remove the * Do whatever you need to shut the clock down and remove the
* interrupt handler. Since this normally only gets called on * interrupt handler. Since this normally only gets called on
* RTEMS shutdown, you may not need to do anything other than * RTEMS shutdown, you may not need to do anything other than
* remove the ISR. * remove the ISR.

10
c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2003 by Cogent Computer Systems * Copyright (c) 2003 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com> * Written by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -75,12 +75,12 @@
#define MC9328MXL_TMR_TCTL_CAP_FALL (2 << 6) #define MC9328MXL_TMR_TCTL_CAP_FALL (2 << 6)
#define MC9328MXL_TMR_TCTL_CAP_ANY (3 << 6) #define MC9328MXL_TMR_TCTL_CAP_ANY (3 << 6)
#define MC9328MXL_TMR_TCTL_OM (bit(5)) #define MC9328MXL_TMR_TCTL_OM (bit(5))
#define MC9328MXL_TMR_TCTL_IRQEN (bit(4)) #define MC9328MXL_TMR_TCTL_IRQEN (bit(4))
#define MC9328MXL_TMR_TCTL_CLKSRC_STOP (0 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_STOP (0 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 (1 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 (1 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16 (2 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16 (2 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_TIN (3 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_TIN (3 << 1)
#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1) #define MC9328MXL_TMR_TCTL_CLKSRC_32KHX (4 << 1)
#define MC9328MXL_TMR_TCTL_TEN (bit(0)) #define MC9328MXL_TMR_TCTL_TEN (bit(0))
#define MC9328MXL_UART1_RXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00))) #define MC9328MXL_UART1_RXD (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00)))
@@ -221,7 +221,7 @@ typedef struct {
#define MC9328MXL_UART_CR3_INVT (bit(1)) #define MC9328MXL_UART_CR3_INVT (bit(1))
#define MC9328MXL_UART_CR3_BPEN (bit(0)) #define MC9328MXL_UART_CR3_BPEN (bit(0))
#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10) #define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)
#define MC9328MXL_UART_CR4_INVR (bit(9)) #define MC9328MXL_UART_CR4_INVR (bit(9))
#define MC9328MXL_UART_CR4_ENIRI (bit(8)) #define MC9328MXL_UART_CR4_ENIRI (bit(8))
#define MC9328MXL_UART_CR4_WKEN (bit(7)) #define MC9328MXL_UART_CR4_WKEN (bit(7))
@@ -313,7 +313,7 @@ typedef struct {
#define MC9328MXL_PLL_SPCTL_MFI_SHIFT (10) #define MC9328MXL_PLL_SPCTL_MFI_SHIFT (10)
#define MC9328MXL_PLL_SPCTL_MFN_MASK (0x000003ff) #define MC9328MXL_PLL_SPCTL_MFN_MASK (0x000003ff)
#define MC9328MXL_PLL_SPCTL_MFN_SHIFT (0) #define MC9328MXL_PLL_SPCTL_MFN_SHIFT (0)
#define MC9328MXL_GPIOA_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00))) #define MC9328MXL_GPIOA_DDIR (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00)))
#define MC9328MXL_GPIOA_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04))) #define MC9328MXL_GPIOA_OCR1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04)))

6
c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S
View File

@@ -12,8 +12,8 @@
* $Id$ * $Id$
*/ */
#define __asm__ #define __asm__
/* /*
* BSP specific interrupt handler for INT or FIQ. In here * BSP specific interrupt handler for INT or FIQ. In here
* you do determine which interrupt happened and call its * you do determine which interrupt happened and call its
* handler. * handler.
@@ -29,7 +29,7 @@ bsp_interrupt_dispatch :
ldr r1, [r0] ldr r1, [r0]
mov r1, r1, LSR #16 /* get the NIVECTOR into 16 LSbits */ mov r1, r1, LSR #16 /* get the NIVECTOR into 16 LSbits */
/* find the ISR's address based on the vector */ /* find the ISR's address based on the vector */
ldr r0, =bsp_vector_table ldr r0, =bsp_vector_table
mov r1, r1, LSL #3 /* Shift vector to get offset into table */ mov r1, r1, LSL #3 /* Shift vector to get offset into table */
add r1, r0, r1 /* r1 has address of vector entry */ add r1, r0, r1 /* r1 has address of vector entry */

6
c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c
View File

@@ -2,7 +2,7 @@
* Motorola MC9328MXL Interrupt handler * Motorola MC9328MXL Interrupt handler
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -17,8 +17,8 @@
extern void default_int_handler(void); extern void default_int_handler(void);
/* /*
* Interrupt system initialization. Disable interrupts, clear * Interrupt system initialization. Disable interrupts, clear
* any that are pending. * any that are pending.
*/ */
void BSP_rtems_irq_mngt_init(void) void BSP_rtems_irq_mngt_init(void)

10
c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c
View File

@@ -2,7 +2,7 @@
* Motorola MC9328MXL Interrupt handler * Motorola MC9328MXL Interrupt handler
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -38,7 +38,7 @@ static int isValidInterrupt(int irq)
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -65,13 +65,13 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
irq->on(irq); irq->on(irq);
} }
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 1; return 1;
} }
/* /*
* Remove and interrupt handler * Remove and interrupt handler
* *
* You should only have to add the code to mask the interrupt. * You should only have to add the code to mask the interrupt.

114
c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h
View File

@@ -2,7 +2,7 @@
* Interrupt handler Header file * Interrupt handler Header file
* *
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -27,7 +27,7 @@ extern "C" {
/* /*
* Include some preprocessor value also used by assember code * Include some preprocessor value also used by assember code
*/ */
#include <rtems.h> #include <rtems.h>
#include <mc9328mxl.h> #include <mc9328mxl.h>
@@ -37,72 +37,72 @@ extern void default_int_handler();
**********************************************************************/ **********************************************************************/
/* possible interrupt sources on the MC9328MXL */ /* possible interrupt sources on the MC9328MXL */
#define BSP_INT_UART3_PFERR 0 #define BSP_INT_UART3_PFERR 0
#define BSP_INT_UART3_RTS 1 #define BSP_INT_UART3_RTS 1
#define BSP_INT_UART3_DTR 2 #define BSP_INT_UART3_DTR 2
#define BSP_INT_UART3_UARTC 3 #define BSP_INT_UART3_UARTC 3
#define BSP_INT_UART3_TX 4 #define BSP_INT_UART3_TX 4
#define BSP_INT_PEN_UP 5 #define BSP_INT_PEN_UP 5
#define BSP_INT_CSI 6 #define BSP_INT_CSI 6
#define BSP_INT_MMA_MAC 7 #define BSP_INT_MMA_MAC 7
#define BSP_INT_MMA 8 #define BSP_INT_MMA 8
#define BSP_INT_COMP 9 #define BSP_INT_COMP 9
#define BSP_INT_MSIRQ 10 #define BSP_INT_MSIRQ 10
#define BSP_INT_GPIO_PORTA 11 #define BSP_INT_GPIO_PORTA 11
#define BSP_INT_GPIO_PORTB 12 #define BSP_INT_GPIO_PORTB 12
#define BSP_INT_GPIO_PORTC 13 #define BSP_INT_GPIO_PORTC 13
#define BSP_INT_LCDC 14 #define BSP_INT_LCDC 14
#define BSP_INT_SIM_IRQ 15 #define BSP_INT_SIM_IRQ 15
#define BSP_INT_SIM_DATA 16 #define BSP_INT_SIM_DATA 16
#define BSP_INT_RTC 17 #define BSP_INT_RTC 17
#define BSP_INT_RTC_SAM 18 #define BSP_INT_RTC_SAM 18
#define BSP_INT_UART2_PFERR 19 #define BSP_INT_UART2_PFERR 19
#define BSP_INT_UART2_RTS 20 #define BSP_INT_UART2_RTS 20
#define BSP_INT_UART2_DTR 21 #define BSP_INT_UART2_DTR 21
#define BSP_INT_UART2_UARTC 22 #define BSP_INT_UART2_UARTC 22
#define BSP_INT_UART2_TX 23 #define BSP_INT_UART2_TX 23
#define BSP_INT_UART2_RX 24 #define BSP_INT_UART2_RX 24
#define BSP_INT_UART1_PFERR 25 #define BSP_INT_UART1_PFERR 25
#define BSP_INT_UART1_RTS 26 #define BSP_INT_UART1_RTS 26
#define BSP_INT_UART1_DTR 27 #define BSP_INT_UART1_DTR 27
#define BSP_INT_UART1_UARTC 28 #define BSP_INT_UART1_UARTC 28
#define BSP_INT_UART1_TX 29 #define BSP_INT_UART1_TX 29
#define BSP_INT_UART1_RX 30 #define BSP_INT_UART1_RX 30
#define BSP_INT_RES31 31 #define BSP_INT_RES31 31
#define BSP_INT_RES32 32 #define BSP_INT_RES32 32
#define BSP_INT_PEN_DATA 33 #define BSP_INT_PEN_DATA 33
#define BSP_INT_PWM 34 #define BSP_INT_PWM 34
#define BSP_INT_MMC_IRQ 35 #define BSP_INT_MMC_IRQ 35
#define BSP_INT_SSI2_TX 36 #define BSP_INT_SSI2_TX 36
#define BSP_INT_SSI2_RX 37 #define BSP_INT_SSI2_RX 37
#define BSP_INT_SSI2_ERR 38 #define BSP_INT_SSI2_ERR 38
#define BSP_INT_I2C 39 #define BSP_INT_I2C 39
#define BSP_INT_SPI2 40 #define BSP_INT_SPI2 40
#define BSP_INT_SPI1 41 #define BSP_INT_SPI1 41
#define BSP_INT_SSI_TX 42 #define BSP_INT_SSI_TX 42
#define BSP_INT_SSI_TX_ERR 43 #define BSP_INT_SSI_TX_ERR 43
#define BSP_INT_SSI_RX 44 #define BSP_INT_SSI_RX 44
#define BSP_INT_SSI_RX_ERR 45 #define BSP_INT_SSI_RX_ERR 45
#define BSP_INT_TOUCH 46 #define BSP_INT_TOUCH 46
#define BSP_INT_USBD0 47 #define BSP_INT_USBD0 47
#define BSP_INT_USBD1 48 #define BSP_INT_USBD1 48
#define BSP_INT_USBD2 49 #define BSP_INT_USBD2 49
#define BSP_INT_USBD3 50 #define BSP_INT_USBD3 50
#define BSP_INT_USBD4 51 #define BSP_INT_USBD4 51
#define BSP_INT_USBD5 52 #define BSP_INT_USBD5 52
#define BSP_INT_USBD6 53 #define BSP_INT_USBD6 53
#define BSP_INT_UART3_RX 54 #define BSP_INT_UART3_RX 54
#define BSP_INT_BTSYS 55 #define BSP_INT_BTSYS 55
#define BSP_INT_BTTIM 56 #define BSP_INT_BTTIM 56
#define BSP_INT_BTWUI 57 #define BSP_INT_BTWUI 57
#define BSP_INT_TIMER2 58 #define BSP_INT_TIMER2 58
#define BSP_INT_TIMER1 59 #define BSP_INT_TIMER1 59
#define BSP_INT_DMA_ERR 60 #define BSP_INT_DMA_ERR 60
#define BSP_INT_DMA 61 #define BSP_INT_DMA 61
#define BSP_INT_GPIO_PORTD 62 #define BSP_INT_GPIO_PORTD 62
#define BSP_INT_WDT 63 #define BSP_INT_WDT 63
#define BSP_MAX_INT 64 #define BSP_MAX_INT 64
typedef struct { typedef struct {
rtems_irq_hdl vector; rtems_irq_hdl vector;
rtems_irq_hdl_param data; rtems_irq_hdl_param data;

14
c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c
View File

@@ -5,7 +5,7 @@
* *
* Copyright (c) 2004 Cogent Computer Systems * Copyright (c) 2004 Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com> * Written by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -17,7 +17,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted. * the number of microseconds since benchmark_timer_initialize() exitted.
* *
* It is important that the timer start/stop overhead be determined * It is important that the timer start/stop overhead be determined
* when porting or modifying this code. * when porting or modifying this code.
* *
* $Id$ * $Id$
@@ -32,13 +32,13 @@ uint32_t g_freq;
bool benchmark_timer_find_average_overhead; bool benchmark_timer_find_average_overhead;
/* /*
* Set up Timer 1 * Set up Timer 1
*/ */
void benchmark_timer_initialize( void ) void benchmark_timer_initialize( void )
{ {
MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 |
MC9328MXL_TMR_TCTL_FRR | MC9328MXL_TMR_TCTL_FRR |
MC9328MXL_TMR_TCTL_TEN); MC9328MXL_TMR_TCTL_TEN);
/* set prescaler to 1 (register value + 1) */ \ /* set prescaler to 1 (register value + 1) */ \
@@ -80,12 +80,12 @@ int benchmark_timer_read( void )
total = (t - g_start); total = (t - g_start);
/* convert to nanoseconds */ /* convert to nanoseconds */
total = (total * 1000)/ g_freq; total = (total * 1000)/ g_freq;
if ( benchmark_timer_find_average_overhead == 1 ) { if ( benchmark_timer_find_average_overhead == 1 ) {
return (int) total; return (int) total;
} else if ( total < LEAST_VALID ) { } else if ( total < LEAST_VALID ) {
return 0; return 0;
} }
/* /*
* Somehow convert total into microseconds * Somehow convert total into microseconds

50
c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c
View File

@@ -31,8 +31,8 @@ static void ffuart_write_polled(int minor, char c);
static int ffuart_set_attributes(int minor, const struct termios *t); static int ffuart_set_attributes(int minor, const struct termios *t);
/* Pointers to functions for handling the UART. */ /* Pointers to functions for handling the UART. */
console_fns ffuart_fns = console_fns ffuart_fns =
{ {
libchip_serial_default_probe, libchip_serial_default_probe,
ffuart_first_open, ffuart_first_open,
ffuart_last_close, ffuart_last_close,
@@ -45,23 +45,23 @@ console_fns ffuart_fns =
}; };
/* /*
* This is called the first time each device is opened. Since * This is called the first time each device is opened. Since
* the driver is polled, we don't have to do anything. If the driver * the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd enable interrupts here. * were interrupt driven, we'd enable interrupts here.
*/ */
static int ffuart_first_open(int major, int minor, void *arg) static int ffuart_first_open(int major, int minor, void *arg)
{ {
return 0; return 0;
} }
/* /*
* This is called the last time each device is closed. Since * This is called the last time each device is closed. Since
* the driver is polled, we don't have to do anything. If the driver * the driver is polled, we don't have to do anything. If the driver
* were interrupt driven, we'd disable interrupts here. * were interrupt driven, we'd disable interrupts here.
*/ */
static int ffuart_last_close(int major, int minor, void *arg) static int ffuart_last_close(int major, int minor, void *arg)
{ {
return 0; return 0;
} }
@@ -73,7 +73,7 @@ static int ffuart_last_close(int major, int minor, void *arg)
* return -1 if there's no data, otherwise return * return -1 if there's no data, otherwise return
* the character in lowest 8 bits of returned int. * the character in lowest 8 bits of returned int.
*/ */
static int ffuart_read(int minor) static int ffuart_read(int minor)
{ {
char c; char c;
console_tbl *console_entry; console_tbl *console_entry;
@@ -90,15 +90,15 @@ static int ffuart_read(int minor)
if (!(ffuart->lsr & FULL_RECEIVE)) { if (!(ffuart->lsr & FULL_RECEIVE)) {
return -1; return -1;
} }
c = ffuart->rbr & 0xff; c = ffuart->rbr & 0xff;
return c; return c;
} }
/* /*
* Write buffer to UART * Write buffer to UART
* *
* return 1 on success, -1 on error * return 1 on success, -1 on error
*/ */
@@ -124,7 +124,7 @@ static int ffuart_write(int minor, const char *buf, int len)
break; break;
} }
} }
c = (char) buf[i]; c = (char) buf[i];
#if ON_SKYEYE != 1 #if ON_SKYEYE != 1
if(c=='\n'){ if(c=='\n'){
@@ -140,14 +140,14 @@ static int ffuart_write(int minor, const char *buf, int len)
} }
#endif #endif
ffuart->rbr = c; ffuart->rbr = c;
/* the TXRDY flag does not seem to update right away (is this true?) */ /* the TXRDY flag does not seem to update right away (is this true?) */
/* so we wait a bit before continuing */ /* so we wait a bit before continuing */
for (x = 0; x < 100; x++) { for (x = 0; x < 100; x++) {
dbg_dly++; /* using a global so this doesn't get optimized out */ dbg_dly++; /* using a global so this doesn't get optimized out */
} }
} }
return 1; return 1;
} }
@@ -155,7 +155,7 @@ static int ffuart_write(int minor, const char *buf, int len)
static void ffuart_init(int minor) static void ffuart_init(int minor)
{ {
console_tbl *console_entry; console_tbl *console_entry;
ffuart_reg_t *ffuart; ffuart_reg_t *ffuart;
unsigned int divisor; unsigned int divisor;
@@ -163,11 +163,11 @@ static void ffuart_init(int minor)
console_entry = BSP_get_uart_from_minor(minor); console_entry = BSP_get_uart_from_minor(minor);
if (console_entry == NULL) { if (console_entry == NULL) {
return; return;
} }
ffuart = (ffuart_reg_t *)console_entry->ulCtrlPort1; ffuart = (ffuart_reg_t *)console_entry->ulCtrlPort1;
ffuart->lcr |= DLAB; ffuart->lcr |= DLAB;
/*Set the Bound*/ /*Set the Bound*/
@@ -191,7 +191,7 @@ static void ffuart_write_polled(int minor, char c)
} }
/* This is for setting baud rate, bits, etc. */ /* This is for setting baud rate, bits, etc. */
static int ffuart_set_attributes(int minor, const struct termios *t) static int ffuart_set_attributes(int minor, const struct termios *t)
{ {
return 0; return 0;
} }
@@ -202,7 +202,7 @@ static int ffuart_set_attributes(int minor, const struct termios *t)
* functions use them instead. * functions use them instead.
*/ */
/***********************************************************************/ /***********************************************************************/
/* /*
* Read from UART. This is used in the exit code, and can't * Read from UART. This is used in the exit code, and can't
* rely on interrupts. * rely on interrupts.
*/ */
@@ -213,7 +213,7 @@ int ffuart_poll_read(int minor)
/* /*
* Write a character to the console. This is used by printk() and * Write a character to the console. This is used by printk() and
* maybe other low level functions. It should not use interrupts or any * maybe other low level functions. It should not use interrupts or any
* RTEMS system calls. It needs to be very simple * RTEMS system calls. It needs to be very simple
*/ */

2
c/src/lib/libcpu/arm/pxa255/include/ffuart.h
View File

@@ -47,4 +47,4 @@ typedef struct {
#define FULL_RECEIVE 0x01 #define FULL_RECEIVE 0x01
#endif #endif

4
c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S
View File

@@ -1,7 +1,7 @@
/* /*
* PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com> * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
@@ -10,7 +10,7 @@
*/ */
#define __asm__ #define __asm__
.globl bsp_interrupt_dispatch .globl bsp_interrupt_dispatch
bsp_interrupt_dispatch : bsp_interrupt_dispatch :
/* /*

6
c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c
View File

@@ -1,7 +1,7 @@
/* /*
* PXA255 interrupt controller by Yang Xi <hiyangxi@gmail.com> * PXA255 interrupt controller by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
@@ -20,8 +20,8 @@ void dummy_handler(uint32_t vector)
void (*IRQ_table[PRIMARY_IRQS])(uint32_t vector); void (*IRQ_table[PRIMARY_IRQS])(uint32_t vector);
/* /*
* Interrupt system initialization. Disable interrupts, clear * Interrupt system initialization. Disable interrupts, clear
* any that are pending. * any that are pending.
*/ */
void BSP_rtems_irq_mngt_init(void) void BSP_rtems_irq_mngt_init(void)

34
c/src/lib/libcpu/arm/pxa255/irq/irq.c
View File

@@ -1,7 +1,7 @@
/* /*
* PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com> * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
@@ -32,54 +32,54 @@ static int isValidInterrupt(int irq)
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
/* /*
* Check if default handler is actually connected. If not, issue * Check if default handler is actually connected. If not, issue
* an error. Note: irq->name is a number corresponding to the * an error. Note: irq->name is a number corresponding to the
* interrupt number . We * interrupt number . We
* convert it to a long word offset to get source's vector register * convert it to a long word offset to get source's vector register
*/ */
if (IRQ_table[irq->name] != dummy_handler) { if (IRQ_table[irq->name] != dummy_handler) {
return 0; return 0;
} }
_CPU_ISR_Disable(level); _CPU_ISR_Disable(level);
/* /*
* store the new handler * store the new handler
*/ */
IRQ_table[irq->name] = irq->hdl; IRQ_table[irq->name] = irq->hdl;
/* /*
* unmask interrupt * unmask interrupt
*/ */
XSCALE_INT_ICMR = XSCALE_INT_ICMR | 1 << irq->name; XSCALE_INT_ICMR = XSCALE_INT_ICMR | 1 << irq->name;
/* /*
* Enable interrupt on device * Enable interrupt on device
*/ */
if(irq->on) { if(irq->on) {
irq->on(irq); irq->on(irq);
} }
_CPU_ISR_Enable(level); _CPU_ISR_Enable(level);
return 1; return 1;
} }
/* /*
* Remove and interrupt handler * Remove and interrupt handler
*/ */
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -96,7 +96,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* mask interrupt * mask interrupt
*/ */
XSCALE_INT_ICMR = XSCALE_INT_ICMR & (~(1 << irq->name)); XSCALE_INT_ICMR = XSCALE_INT_ICMR & (~(1 << irq->name));
/* /*
* Disable interrupt on device * Disable interrupt on device
*/ */
@@ -108,7 +108,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value * restore the default irq value
*/ */
IRQ_table[irq->name] = dummy_handler; IRQ_table[irq->name] = dummy_handler;
_CPU_ISR_Enable(level); _CPU_ISR_Enable(level);
return 1; return 1;

6
c/src/lib/libcpu/arm/pxa255/irq/irq.h
View File

@@ -1,7 +1,7 @@
/* /*
* Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com> * Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
@@ -21,7 +21,7 @@ extern "C" {
/* /*
* Include some preprocessor value also used by assember code * Include some preprocessor value also used by assember code
*/ */
#include <rtems.h> #include <rtems.h>
#include <pxa255.h> #include <pxa255.h>
@@ -77,7 +77,7 @@ void BSP_rtems_irq_mngt_init();
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
/* /*
* function to get the current RTEMS irq handler for ptr->name. * function to get the current RTEMS irq handler for ptr->name.
*/ */
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr); int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);

6
c/src/lib/libcpu/arm/pxa255/timer/timer.c
View File

@@ -8,7 +8,7 @@
* Timer_initialize() and Read_timer(). Read_timer() usually returns * Timer_initialize() and Read_timer(). Read_timer() usually returns
* the number of microseconds since Timer_initialize() exitted. * the number of microseconds since Timer_initialize() exitted.
* *
* It is important that the timer start/stop overhead be determined * It is important that the timer start/stop overhead be determined
* when porting or modifying this code. * when porting or modifying this code.
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
@@ -29,7 +29,7 @@ bool benchmark_timer_find_average_overhead;
bool benchmark_timer_is_initialized = false; bool benchmark_timer_is_initialized = false;
/* /*
* Use the timer count register to measure. * Use the timer count register to measure.
* The frequency of it is 3.4864MHZ * The frequency of it is 3.4864MHZ
* The longest period we are able to capture is 4G/3.4864MHZ * The longest period we are able to capture is 4G/3.4864MHZ
*/ */
@@ -62,7 +62,7 @@ int benchmark_timer_read(void)
total -= tick_time; total -= tick_time;
else else
total += 0xffffffff - tick_time; /*Round up but not overflow*/ total += 0xffffffff - tick_time; /*Round up but not overflow*/
if ( benchmark_timer_find_average_overhead == true ) if ( benchmark_timer_find_average_overhead == true )
return total; /*Counter cycles*/ return total; /*Counter cycles*/

4
c/src/lib/libcpu/arm/s3c2400/clock/support.c
View File

@@ -41,10 +41,10 @@ uint32_t get_UCLK(void)
/* return HCLK frequency */ /* return HCLK frequency */
uint32_t get_HCLK(void) uint32_t get_HCLK(void)
{ {
if (rCLKDIVN & 0x2) if (rCLKDIVN & 0x2)
return get_FCLK()/2; return get_FCLK()/2;
else else
return get_FCLK(); return get_FCLK();
} }
/* return PCLK frequency */ /* return PCLK frequency */

2
c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h
View File

@@ -472,7 +472,7 @@ typedef union
unsigned long all; unsigned long all;
} LCDCON1; } LCDCON1;
typedef union { typedef union {
struct { struct {
unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */
/* VSYNC pulse's high level width by counting the */ /* VSYNC pulse's high level width by counting the */

14
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S
View File

@@ -14,24 +14,24 @@
*/ */
#define __asm__ #define __asm__
/* /*
* Function to obtain, execute an IT handler and acknowledge the IT * Function to obtain, execute an IT handler and acknowledge the IT
*/ */
.globl bsp_interrupt_dispatch .globl bsp_interrupt_dispatch
bsp_interrupt_dispatch : bsp_interrupt_dispatch :
ldr r0, =0x14400014 /* Read rINTOFFSET */ ldr r0, =0x14400014 /* Read rINTOFFSET */
ldr r1, [r0] ldr r1, [r0]
ldr r0, =bsp_vector_table ldr r0, =bsp_vector_table
ldr r0, [r0, r1, LSL #2] /* Read the address */ ldr r0, [r0, r1, LSL #2] /* Read the address */
stmdb sp!,{lr} stmdb sp!,{lr}
ldr lr, =IRQ_return /* prepare the return from handler */ ldr lr, =IRQ_return /* prepare the return from handler */
mov pc, r0 mov pc, r0
IRQ_return: IRQ_return:

2
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c
View File

@@ -18,7 +18,7 @@
extern void default_int_handler(); extern void default_int_handler();
void BSP_rtems_irq_mngt_init() void BSP_rtems_irq_mngt_init()
{ {
long *vectorTable; long *vectorTable;
int i; int i;

8
c/src/lib/libcpu/arm/s3c2400/irq/irq.c
View File

@@ -41,7 +41,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_irq_hdl *HdlTable; rtems_irq_hdl *HdlTable;
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -53,7 +53,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
if (*(HdlTable + irq->name) != default_int_handler) { if (*(HdlTable + irq->name) != default_int_handler) {
return 0; return 0;
} }
rtems_interrupt_disable(level); rtems_interrupt_disable(level);
/* /*
@@ -78,7 +78,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{ {
rtems_irq_hdl *HdlTable; rtems_irq_hdl *HdlTable;
rtems_interrupt_level level; rtems_interrupt_level level;
if (!isValidInterrupt(irq->name)) { if (!isValidInterrupt(irq->name)) {
return 0; return 0;
} }
@@ -103,7 +103,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
* restore the default irq value * restore the default irq value
*/ */
*(HdlTable + irq->name) = default_int_handler; *(HdlTable + irq->name) = default_int_handler;
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 1; return 1;

60
c/src/lib/libcpu/arm/s3c2400/irq/irq.h
View File

@@ -23,7 +23,7 @@ extern "C" {
/* /*
* Include some preprocessor value also used by assember code * Include some preprocessor value also used by assember code
*/ */
#include <rtems.h> #include <rtems.h>
#include <s3c2400.h> #include <s3c2400.h>
@@ -41,35 +41,35 @@ extern void default_int_handler();
#define BSP_EINT5 5 #define BSP_EINT5 5
#define BSP_EINT6 6 #define BSP_EINT6 6
#define BSP_EINT7 7 #define BSP_EINT7 7
#define BSP_INT_TICK 8 #define BSP_INT_TICK 8
#define BSP_INT_WDT 9 #define BSP_INT_WDT 9
#define BSP_INT_TIMER0 10 #define BSP_INT_TIMER0 10
#define BSP_INT_TIMER1 11 #define BSP_INT_TIMER1 11
#define BSP_INT_TIMER2 12 #define BSP_INT_TIMER2 12
#define BSP_INT_TIMER3 13 #define BSP_INT_TIMER3 13
#define BSP_INT_TIMER4 14 #define BSP_INT_TIMER4 14
#define BSP_INT_UERR01 15 #define BSP_INT_UERR01 15
#define _res0 16 #define _res0 16
#define BSP_INT_DMA0 17 #define BSP_INT_DMA0 17
#define BSP_INT_DMA1 18 #define BSP_INT_DMA1 18
#define BSP_INT_DMA2 19 #define BSP_INT_DMA2 19
#define BSP_INT_DMA3 20 #define BSP_INT_DMA3 20
#define BSP_INT_MMC 21 #define BSP_INT_MMC 21
#define BSP_INT_SPI 22 #define BSP_INT_SPI 22
#define BSP_INT_URXD0 23 #define BSP_INT_URXD0 23
#define BSP_INT_URXD1 24 #define BSP_INT_URXD1 24
#define BSP_INT_USBD 25 #define BSP_INT_USBD 25
#define BSP_INT_USBH 26 #define BSP_INT_USBH 26
#define BSP_INT_IIC 27 #define BSP_INT_IIC 27
#define BSP_INT_UTXD0 28 #define BSP_INT_UTXD0 28
#define BSP_INT_UTXD1 29 #define BSP_INT_UTXD1 29
#define BSP_INT_RTC 30 #define BSP_INT_RTC 30
#define BSP_INT_ADC 31 #define BSP_INT_ADC 31
#define BSP_MAX_INT 32 #define BSP_MAX_INT 32
extern void *bsp_vector_table; extern void *bsp_vector_table;
#define VECTOR_TABLE &bsp_vector_table #define VECTOR_TABLE &bsp_vector_table
/* /*
* Type definition for RTEMS managed interrupts * Type definition for RTEMS managed interrupts
*/ */
@@ -101,9 +101,9 @@ typedef struct __rtems_irq_connect_data__ {
* It is usually called immediately AFTER connecting the interrupt handler. * It is usually called immediately AFTER connecting the interrupt handler.
* RTEMS may well need such a function when restoring normal interrupt * RTEMS may well need such a function when restoring normal interrupt
* processing after a debug session. * processing after a debug session.
* *
*/ */
rtems_irq_enable on; rtems_irq_enable on;
/* /*
* function for disabling interrupts at device level (ONLY!). * function for disabling interrupts at device level (ONLY!).
@@ -178,7 +178,7 @@ void BSP_rtems_irq_mngt_init();
* 4) perform rescheduling when necessary, * 4) perform rescheduling when necessary,
* 5) restore the C scratch registers... * 5) restore the C scratch registers...
* 6) restore initial execution flow * 6) restore initial execution flow
* *
*/ */
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);

22
c/src/lib/libcpu/arm/s3c2400/timer/timer.c
View File

@@ -14,7 +14,7 @@
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted. * the number of microseconds since benchmark_timer_initialize() exitted.
* *
* It is important that the timer start/stop overhead be determined * It is important that the timer start/stop overhead be determined
* when porting or modifying this code. * when porting or modifying this code.
* *
* $Id$ * $Id$
@@ -29,7 +29,7 @@ uint32_t g_freq;
bool benchmark_timer_find_average_overhead; bool benchmark_timer_find_average_overhead;
/* /*
* Set up Timer 1 * Set up Timer 1
*/ */
@@ -37,7 +37,7 @@ void benchmark_timer_initialize( void )
{ {
uint32_t cr; uint32_t cr;
/* stop TIMER1*/ /* stop TIMER1*/
cr=rTCON & 0xFFFFF0FF; cr=rTCON & 0xFFFFF0FF;
rTCON=(cr | (0x0 << 8)); rTCON=(cr | (0x0 << 8));
@@ -45,15 +45,15 @@ void benchmark_timer_initialize( void )
cr=rTCFG1 & 0xFFFFFF0F; cr=rTCFG1 & 0xFFFFFF0F;
rTCFG1=(cr | (0<<4)); rTCFG1=(cr | (0<<4));
/* input freq=PLCK/2 Mhz*/ /* input freq=PLCK/2 Mhz*/
g_freq = get_PCLK() / 2000; g_freq = get_PCLK() / 2000;
rTCNTB1 = 0xFFFF; rTCNTB1 = 0xFFFF;
/* start TIMER1 with manual reload */ /* start TIMER1 with manual reload */
cr=rTCON & 0xFFFFF0FF; cr=rTCON & 0xFFFFF0FF;
rTCON=(cr | (0x1 << 9)); rTCON=(cr | (0x1 << 9));
rTCON=(cr | (0x1 << 8)); rTCON=(cr | (0x1 << 8));
g_start = rTCNTO1; g_start = rTCNTO1;
} }
@@ -83,16 +83,16 @@ int benchmark_timer_read( void )
* interrupts since the timer was initialized and clicks since the last * interrupts since the timer was initialized and clicks since the last
* interrupts. * interrupts.
*/ */
total = (g_start - t); total = (g_start - t);
/* convert to microseconds */ /* convert to microseconds */
total = (total*1000) / g_freq; total = (total*1000) / g_freq;
if ( benchmark_timer_find_average_overhead == 1 ) { if ( benchmark_timer_find_average_overhead == 1 ) {
return (int) total; return (int) total;
} else if ( total < LEAST_VALID ) { } else if ( total < LEAST_VALID ) {
return 0; return 0;
} }
/* /*

58
c/src/lib/libcpu/arm/s3c2410/irq/irq.h
View File

@@ -23,7 +23,7 @@ extern "C" {
/* /*
* Include some preprocessor value also used by assember code * Include some preprocessor value also used by assember code
*/ */
#include <rtems.h> #include <rtems.h>
#include <s3c2410.h> #include <s3c2410.h>
@@ -40,34 +40,34 @@ extern void default_int_handler();
#define BSP_EINT4_7 4 #define BSP_EINT4_7 4
#define BSP_EINT8_23 5 #define BSP_EINT8_23 5
#define BSP_nBATT_FLT 7 #define BSP_nBATT_FLT 7
#define BSP_INT_TICK 8 #define BSP_INT_TICK 8
#define BSP_INT_WDT 9 #define BSP_INT_WDT 9
#define BSP_INT_TIMER0 10 #define BSP_INT_TIMER0 10
#define BSP_INT_TIMER1 11 #define BSP_INT_TIMER1 11
#define BSP_INT_TIMER2 12 #define BSP_INT_TIMER2 12
#define BSP_INT_TIMER3 13 #define BSP_INT_TIMER3 13
#define BSP_INT_TIMER4 14 #define BSP_INT_TIMER4 14
#define BSP_INT_UART2 15 #define BSP_INT_UART2 15
#define BSP_INT_LCD 16 #define BSP_INT_LCD 16
#define BSP_INT_DMA0 17 #define BSP_INT_DMA0 17
#define BSP_INT_DMA1 18 #define BSP_INT_DMA1 18
#define BSP_INT_DMA2 19 #define BSP_INT_DMA2 19
#define BSP_INT_DMA3 20 #define BSP_INT_DMA3 20
#define BSP_INT_SDI 21 #define BSP_INT_SDI 21
#define BSP_INT_SPI0 22 #define BSP_INT_SPI0 22
#define BSP_INT_UART1 23 #define BSP_INT_UART1 23
#define BSP_INT_USBD 25 #define BSP_INT_USBD 25
#define BSP_INT_USBH 26 #define BSP_INT_USBH 26
#define BSP_INT_IIC 27 #define BSP_INT_IIC 27
#define BSP_INT_UART0 28 #define BSP_INT_UART0 28
#define BSP_INT_SPI1 29 #define BSP_INT_SPI1 29
#define BSP_INT_RTC 30 #define BSP_INT_RTC 30
#define BSP_INT_ADC 31 #define BSP_INT_ADC 31
#define BSP_MAX_INT 32 #define BSP_MAX_INT 32
extern void *bsp_vector_table; extern void *bsp_vector_table;
#define VECTOR_TABLE &bsp_vector_table #define VECTOR_TABLE &bsp_vector_table
/* /*
* Type definition for RTEMS managed interrupts * Type definition for RTEMS managed interrupts
*/ */
@@ -99,9 +99,9 @@ typedef struct __rtems_irq_connect_data__ {
* It is usually called immediately AFTER connecting the interrupt handler. * It is usually called immediately AFTER connecting the interrupt handler.
* RTEMS may well need such a function when restoring normal interrupt * RTEMS may well need such a function when restoring normal interrupt
* processing after a debug session. * processing after a debug session.
* *
*/ */
rtems_irq_enable on; rtems_irq_enable on;
/* /*
* function for disabling interrupts at device level (ONLY!). * function for disabling interrupts at device level (ONLY!).
@@ -176,7 +176,7 @@ void BSP_rtems_irq_mngt_init();
* 4) perform rescheduling when necessary, * 4) perform rescheduling when necessary,
* 5) restore the C scratch registers... * 5) restore the C scratch registers...
* 6) restore initial execution flow * 6) restore initial execution flow
* *
*/ */
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);

8
c/src/lib/libcpu/arm/shared/arm920/mmu.c
View File

@@ -108,9 +108,9 @@ void mmu_init(mmu_sect_map_t *map)
while (sects > 0) { while (sects > 0) {
lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20, lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
MMU_SECT_AP_ALL, MMU_SECT_AP_ALL,
0, 0,
c, c,
b); b);
pbase++; pbase++;
vbase++; vbase++;
@@ -249,4 +249,4 @@ void mmu_set_cpu_async_mode(void)
reg |= 0xc0000000; reg |= 0xc0000000;
mmu_set_ctrl(reg); mmu_set_ctrl(reg);
} }

4
c/src/lib/libcpu/bfin/cache/cache.c vendored
View File

@@ -1,5 +1,5 @@
/* Blackfin Cache Support /* Blackfin Cache Support
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -9,7 +9,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include <bsp.h> #include <bsp.h>

4
c/src/lib/libcpu/bfin/clock/clock.c
View File

@@ -1,5 +1,5 @@
/* RTEMS Clock Tick Driver for Blackfin. Uses Blackfin Core Timer. /* RTEMS Clock Tick Driver for Blackfin. Uses Blackfin Core Timer.
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -9,7 +9,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include <stdlib.h> #include <stdlib.h>

32
c/src/lib/libcpu/bfin/clock/rtc.c
View File

@@ -10,7 +10,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include "tod.h" #include "tod.h"
@@ -21,7 +21,7 @@
/* The following are inside RTEMS -- we are violating visibility!!! /* The following are inside RTEMS -- we are violating visibility!!!
* Perhaps an API could be defined to get days since 1 Jan. * Perhaps an API could be defined to get days since 1 Jan.
*/ */
extern const uint16_t _TOD_Days_to_date[2][13]; extern const uint16_t _TOD_Days_to_date[2][13];
/* /*
@@ -42,8 +42,8 @@ void setRealTimeFromRTEMS (void)
{ {
rtems_time_of_day time_buffer; rtems_time_of_day time_buffer;
rtems_status_code status; rtems_status_code status;
status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer ); status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer );
if (status == RTEMS_SUCCESSFUL){ if (status == RTEMS_SUCCESSFUL){
setRealTime(&time_buffer); setRealTime(&time_buffer);
} }
@@ -56,9 +56,9 @@ void setRealTimeFromRTEMS (void)
void setRealTimeToRTEMS (void) void setRealTimeToRTEMS (void)
{ {
rtems_time_of_day time_buffer; rtems_time_of_day time_buffer;
getRealTime(&time_buffer); getRealTime(&time_buffer);
rtems_clock_set( &time_buffer ); rtems_clock_set( &time_buffer );
} }
/* /*
@@ -70,16 +70,16 @@ int setRealTime(
{ {
uint32_t days; uint32_t days;
rtems_time_of_day tod_temp; rtems_time_of_day tod_temp;
tod_temp = *tod; tod_temp = *tod;
days = (tod_temp.year - TOD_BASE_YEAR) * 365 + \ days = (tod_temp.year - TOD_BASE_YEAR) * 365 + \
_TOD_Days_to_date[0][tod_temp.month] + tod_temp.day - 1; _TOD_Days_to_date[0][tod_temp.month] + tod_temp.day - 1;
if (tod_temp.month < 3) if (tod_temp.month < 3)
days += Leap_years_until_now (tod_temp.year - 1); days += Leap_years_until_now (tod_temp.year - 1);
else else
days += Leap_years_until_now (tod_temp.year); days += Leap_years_until_now (tod_temp.year);
*((uint32_t volatile *)RTC_STAT) = (days << RTC_STAT_DAYS_SHIFT)| *((uint32_t volatile *)RTC_STAT) = (days << RTC_STAT_DAYS_SHIFT)|
(tod_temp.hour << RTC_STAT_HOURS_SHIFT)| (tod_temp.hour << RTC_STAT_HOURS_SHIFT)|
(tod_temp.minute << RTC_STAT_MINUTES_SHIFT)| (tod_temp.minute << RTC_STAT_MINUTES_SHIFT)|
@@ -99,21 +99,21 @@ void getRealTime(
uint32_t days, rtc_reg; uint32_t days, rtc_reg;
rtems_time_of_day tod_temp = { 0, 0, 0 }; rtems_time_of_day tod_temp = { 0, 0, 0 };
int n, Leap_year; int n, Leap_year;
rtc_reg = *((uint32_t volatile *)RTC_STAT); rtc_reg = *((uint32_t volatile *)RTC_STAT);
days = (rtc_reg >> RTC_STAT_DAYS_SHIFT) + 1; days = (rtc_reg >> RTC_STAT_DAYS_SHIFT) + 1;
/* finding year */ /* finding year */
tod_temp.year = days/365 + TOD_BASE_YEAR; tod_temp.year = days/365 + TOD_BASE_YEAR;
if (days%365 > Leap_years_until_now (tod_temp.year - 1)) { if (days%365 > Leap_years_until_now (tod_temp.year - 1)) {
days = (days%365) - Leap_years_until_now (tod_temp.year - 1); days = (days%365) - Leap_years_until_now (tod_temp.year - 1);
} else { } else {
tod_temp.year--; tod_temp.year--;
days = (days%365) + 365 - Leap_years_until_now (tod_temp.year - 1); days = (days%365) + 365 - Leap_years_until_now (tod_temp.year - 1);
} }
/* finding month and day */ /* finding month and day */
Leap_year = (((!(tod_temp.year%4)) && (tod_temp.year%100)) || Leap_year = (((!(tod_temp.year%4)) && (tod_temp.year%100)) ||
(!(tod_temp.year%400)))?1:0; (!(tod_temp.year%400)))?1:0;
for (n=1; n<=12; n++) { for (n=1; n<=12; n++) {

4
c/src/lib/libcpu/bfin/clock/tod.h
View File

@@ -1,5 +1,5 @@
/* tod.h /* tod.h
* *
* Real Time Clock definitions for eZKit533. * Real Time Clock definitions for eZKit533.
* *
* Copyright (c) 2006 by Atos Automacao Industrial Ltda. * Copyright (c) 2006 by Atos Automacao Industrial Ltda.
@@ -11,7 +11,7 @@
* http://www.rtems.com/license/LICENSE. * http://www.rtems.com/license/LICENSE.
* *
* $Id$ * $Id$
*/ */
#ifndef TOD_H #ifndef TOD_H

2
c/src/lib/libcpu/bfin/include/sicRegs.h
View File

@@ -17,7 +17,7 @@
#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) #define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c)
#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) #define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010)
#define SIC_IAR_PITCH 0x04 #define SIC_IAR_PITCH 0x04
#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) #define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010)
#if SIC_IAR_COUNT > 1 #if SIC_IAR_COUNT > 1
#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) #define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014)

4
c/src/lib/libcpu/bfin/interrupt/interrupt.c
View File

@@ -1,5 +1,5 @@
/* Support for Blackfin interrupt controller /* Support for Blackfin interrupt controller
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -9,7 +9,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include <rtems/libio.h> #include <rtems/libio.h>

2
c/src/lib/libcpu/bfin/interrupt/interrupt.h
View File

@@ -73,7 +73,7 @@ void bfin_interrupt_enable_all(int source, bool enable);
/* disable a source independently of the individual ISR enables (starts /* disable a source independently of the individual ISR enables (starts
out all enabled) */ out all enabled) */
void bfin_interrupt_enable_global(int source, bool enable); void bfin_interrupt_enable_global(int source, bool enable);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

4
c/src/lib/libcpu/bfin/mmu/mmu.c
View File

@@ -1,5 +1,5 @@
/* Blackfin MMU Support /* Blackfin MMU Support
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -9,7 +9,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>

4
c/src/lib/libcpu/bfin/serial/spi.c
View File

@@ -1,7 +1,7 @@
/* placeholder (just a shell) */ /* placeholder (just a shell) */
/* SPI driver for Blackfin /* SPI driver for Blackfin
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -11,7 +11,7 @@
* *
* $Id$ * $Id$
*/ */
#include <stdlib.h> #include <stdlib.h>
#include <rtems.h> #include <rtems.h>

2
c/src/lib/libcpu/bfin/serial/spi.h
View File

@@ -40,7 +40,7 @@ typedef struct {
extern rtems_libi2c_bus_ops_t bfin_spi_libi2c_bus_ops; extern rtems_libi2c_bus_ops_t bfin_spi_libi2c_bus_ops;
void bfin_spi_isr(int source); void bfin_spi_isr(int source);

10
c/src/lib/libcpu/bfin/serial/twi.c
View File

@@ -1,7 +1,7 @@
/* this is not much more than a shell; it does not do anything useful yet */ /* this is not much more than a shell; it does not do anything useful yet */
/* TWI (I2C) driver for Blackfin /* TWI (I2C) driver for Blackfin
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -11,7 +11,7 @@
* *
* $Id$ * $Id$
*/ */
#include <stdlib.h> #include <stdlib.h>
#include <rtems.h> #include <rtems.h>
@@ -49,9 +49,9 @@ rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) {
if (channel < 0 || channel >= N_BFIN_TWI) if (channel < 0 || channel >= N_BFIN_TWI)
return RTEMS_INVALID_NUMBER; return RTEMS_INVALID_NUMBER;
base = config->base; base = config->base;
twi[channel].base = base; twi[channel].base = base;
result = rtems_semaphore_create(rtems_build_name('t','w','i','s'), result = rtems_semaphore_create(rtems_build_name('t','w','i','s'),
0, 0,
@@ -77,7 +77,7 @@ rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) {
TWI_CONTROL_TWI_ENA; TWI_CONTROL_TWI_ENA;
BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ? BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ?
((8 << TWI_CLKDIV_CLKHI_SHIFT) | ((8 << TWI_CLKDIV_CLKHI_SHIFT) |
(17 << TWI_CLKDIV_CLKLOW_SHIFT)) : (17 << TWI_CLKDIV_CLKLOW_SHIFT)) :
((33 << TWI_CLKDIV_CLKHI_SHIFT) | ((33 << TWI_CLKDIV_CLKHI_SHIFT) |
(67 << TWI_CLKDIV_CLKLOW_SHIFT)); (67 << TWI_CLKDIV_CLKLOW_SHIFT));
BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0; BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0;

16
c/src/lib/libcpu/bfin/serial/uart.c
View File

@@ -1,5 +1,5 @@
/* UART driver for Blackfin /* UART driver for Blackfin
* *
* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
* written by Allan Hessenflow <allanh@kallisti.com> * written by Allan Hessenflow <allanh@kallisti.com>
* *
@@ -9,7 +9,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include <rtems/libio.h> #include <rtems/libio.h>
@@ -34,7 +34,7 @@ static void initializeHardware(int minor) {
uint16_t r; uint16_t r;
base = uartsConfig->channels[minor].base_address; base = uartsConfig->channels[minor].base_address;
*(uint16_t volatile *) (base + UART_IER_OFFSET) = 0; *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
if (uartsConfig->channels[minor].force_baud) if (uartsConfig->channels[minor].force_baud)
@@ -60,12 +60,12 @@ static void initializeHardware(int minor) {
static int pollRead(int minor) { static int pollRead(int minor) {
int c; int c;
char *base; char *base;
base = uartsConfig->channels[minor].base_address; base = uartsConfig->channels[minor].base_address;
/* check to see if driver is using interrupts so this call will be /* check to see if driver is using interrupts so this call will be
harmless (though non-functional) in case some debug code tries to harmless (though non-functional) in case some debug code tries to
use it */ use it */
if (!uartsConfig->channels[minor].use_interrupts && if (!uartsConfig->channels[minor].use_interrupts &&
*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR) *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
c = *((uint16_t volatile *) (base + UART_RBR_OFFSET)); c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
@@ -87,7 +87,7 @@ char bfin_uart_poll_read(int minor) {
void bfin_uart_poll_write(int minor, char c) { void bfin_uart_poll_write(int minor, char c) {
char *base; char *base;
base = uartsConfig->channels[minor].base_address; base = uartsConfig->channels[minor].base_address;
while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE)) while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
@@ -158,7 +158,7 @@ static int pollWrite(int minor, const char *buf, int len) {
static void enableInterrupts(int minor) { static void enableInterrupts(int minor) {
char *base; char *base;
base = uartsConfig->channels[minor].base_address; base = uartsConfig->channels[minor].base_address;
*(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI | *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI |

2
c/src/lib/libcpu/bfin/serial/uart.h
View File

@@ -50,7 +50,7 @@ rtems_device_driver bfin_uart_open(rtems_device_major_number major,
void bfin_uart_isr(int source); void bfin_uart_isr(int source);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

12
c/src/lib/libcpu/bfin/timer/timer.c
View File

@@ -4,7 +4,7 @@
* Suite. Each measured time period is demarcated by calls to * Suite. Each measured time period is demarcated by calls to
* benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns * benchmark_timer_initialize() and benchmark_timer_read(). benchmark_timer_read() usually returns
* the number of microseconds since benchmark_timer_initialize() exitted. * the number of microseconds since benchmark_timer_initialize() exitted.
* *
* Copyright (c) 2006 by Atos Automacao Industrial Ltda. * Copyright (c) 2006 by Atos Automacao Industrial Ltda.
* written by Alain Schaefer <alain.schaefer@easc.ch> * written by Alain Schaefer <alain.schaefer@easc.ch>
* and Antonio Giovanini <antonio@atos.com.br> * and Antonio Giovanini <antonio@atos.com.br>
@@ -15,7 +15,7 @@
* *
* $Id$ * $Id$
*/ */
#include <rtems.h> #include <rtems.h>
#include <bsp.h> #include <bsp.h>
@@ -26,7 +26,7 @@ bool benchmark_timer_find_average_overhead;
/* /*
* benchmark_timer_initialize * benchmark_timer_initialize
* *
* Blackfin processor has a counter for clock cycles. * Blackfin processor has a counter for clock cycles.
*/ */
void benchmark_timer_initialize( void ) void benchmark_timer_initialize( void )
@@ -40,7 +40,7 @@ void benchmark_timer_initialize( void )
asm ("R2 = SYSCFG;"); asm ("R2 = SYSCFG;");
asm ("BITSET(R2,1);"); asm ("BITSET(R2,1);");
asm ("SYSCFG = R2"); asm ("SYSCFG = R2");
} }
/* /*
@@ -64,7 +64,7 @@ int benchmark_timer_read( void )
uint32_t total; uint32_t total;
register uint32_t cycles asm ("R2"); register uint32_t cycles asm ("R2");
/* stop counter */ /* stop counter */
asm("R2 = SYSCFG;"); asm("R2 = SYSCFG;");
asm("BITCLR(R2,1);"); asm("BITCLR(R2,1);");
asm("SYSCFG = R2;"); asm("SYSCFG = R2;");
@@ -74,7 +74,7 @@ int benchmark_timer_read( void )
clicks = cycles; /* Clock cycles */ clicks = cycles; /* Clock cycles */
/* converting to microseconds */ /* converting to microseconds */
total = clicks / (CCLK/1000000); total = clicks / (CCLK/1000000);
if ( benchmark_timer_find_average_overhead == 1 ) if ( benchmark_timer_find_average_overhead == 1 )
return total; /* in XXX microsecond units */ return total; /* in XXX microsecond units */

2
c/src/lib/libcpu/m68k/shared/misc/m68kidle.c
View File

@@ -28,7 +28,7 @@
* *
* Output parameters: NONE * Output parameters: NONE
*/ */
void *_CPU_Thread_Idle_body( uintptr_t ignored ) void *_CPU_Thread_Idle_body( uintptr_t ignored )
{ {
#if defined(mcf5272) #if defined(mcf5272)

2
c/src/lib/libcpu/m68k/shared/misc/memProbe.c
View File

@@ -1,4 +1,4 @@
/* /*
* Address Probing for M68k/ColdFire * Address Probing for M68k/ColdFire
*/ */

22
c/src/lib/libcpu/mips/au1x00/include/au1x00.h
View File

@@ -3,7 +3,7 @@
* *
* Copyright (c) 2005 by Cogent Computer Systems * Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com> * Written by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -189,15 +189,15 @@
#define MEM_STADDR3 0x11003f00 #define MEM_STADDR3 0x11003f00
/* /*
* SDCS0 - * SDCS0 -
* SDCS1 - * SDCS1 -
* SDCS2 - * SDCS2 -
*/ */
#define MEM_SDMODE0 0x00552229 #define MEM_SDMODE0 0x00552229
#define MEM_SDMODE1 0x00552229 #define MEM_SDMODE1 0x00552229
#define MEM_SDMODE2 0x00552229 #define MEM_SDMODE2 0x00552229
#define MEM_SDADDR0 0x001003F8 #define MEM_SDADDR0 0x001003F8
#define MEM_SDADDR1 0x001023F8 #define MEM_SDADDR1 0x001023F8
#define MEM_SDADDR2 0x001043F8 #define MEM_SDADDR2 0x001043F8
@@ -245,7 +245,7 @@
#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) #define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00))
#define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04)) #define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04))
#define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08)) #define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08))
#define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c)) #define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c))
@@ -315,7 +315,7 @@ typedef struct {
uint32_t _rsv0; uint32_t _rsv0;
uint32_t _rsv1; uint32_t _rsv1;
} au1x00_macdma_rx_t; } au1x00_macdma_rx_t;
typedef struct { typedef struct {
volatile uint32_t stat; volatile uint32_t stat;
@@ -323,7 +323,7 @@ typedef struct {
volatile uint32_t len; volatile uint32_t len;
uint32_t _rsv0; uint32_t _rsv0;
} au1x00_macdma_tx_t; } au1x00_macdma_tx_t;
#define AU1X00_MAC_CTRL_RA (bit(31)) #define AU1X00_MAC_CTRL_RA (bit(31))
#define AU1X00_MAC_CTRL_EM (bit(30)) #define AU1X00_MAC_CTRL_EM (bit(30))
#define AU1X00_MAC_CTRL_DO (bit(23)) #define AU1X00_MAC_CTRL_DO (bit(23))
@@ -392,7 +392,7 @@ typedef struct {
#define AU1X00_MAC_DMA_TXSTAT_PR (bit(31)) #define AU1X00_MAC_DMA_TXSTAT_PR (bit(31))
#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) #define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10)
#define AU1X00_MAC_DMA_TXSTAT_LO (bit(9)) #define AU1X00_MAC_DMA_TXSTAT_LO (bit(9))
#define AU1X00_MAC_DMA_TXSTAT_DF (bit(8)) #define AU1X00_MAC_DMA_TXSTAT_DF (bit(8))
#define AU1X00_MAC_DMA_TXSTAT_UR (bit(7)) #define AU1X00_MAC_DMA_TXSTAT_UR (bit(7))
@@ -425,8 +425,8 @@ typedef struct {
volatile uint32_t enable; volatile uint32_t enable;
} au1x00_uart_t; } au1x00_uart_t;
extern au1x00_uart_t *uart0; extern au1x00_uart_t *uart0;
extern au1x00_uart_t *uart3; extern au1x00_uart_t *uart3;
/* /*
* Interrupt Vector Numbers * Interrupt Vector Numbers

4
c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/* /*
* This file contains the maximum number of vectors. This can not * This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model. * be determined without knowing the RTEMS CPU model.
* *
* COPYRIGHT (c) 1989-2000. * COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR). * On-Line Applications Research Corporation (OAR).

20
c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c
View File

@@ -1,9 +1,9 @@
/* /*
* Au1x00 Interrupt Vectoring * Au1x00 Interrupt Vectoring
* *
* Copyright (c) 2005 by Cogent Computer Systems * Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com> * Written by Jay Monkman <jtm@lopingdog.com>
* *
* The license and distribution terms for this file may be * The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* *
@@ -44,7 +44,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if ( cause & 0x80 ) { if ( cause & 0x80 ) {
unsigned long zero = 0; unsigned long zero = 0;
/* /*
* I don't see a good way to disable the compare * I don't see a good way to disable the compare
* interrupt, so let's just ignore it. * interrupt, so let's just ignore it.
*/ */
asm volatile ("mtc0 %0, $11\n" :: "r" (zero)); asm volatile ("mtc0 %0, $11\n" :: "r" (zero));
@@ -56,23 +56,23 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if ( cause & 0x40 ) { if ( cause & 0x40 ) {
CALL_ISR( AU1X00_IRQ_PERF, frame ); CALL_ISR( AU1X00_IRQ_PERF, frame );
} }
/* Interrupt controller 0 */ /* Interrupt controller 0 */
if ( cause & 0x0c ) { if ( cause & 0x0c ) {
call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR); call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
} }
/* Interrupt controller 1 */ /* Interrupt controller 1 */
if ( cause & 0x30 ) { if ( cause & 0x30 ) {
call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR); call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
} }
/* SW[0] */ /* SW[0] */
if ( cause & 0x01 ) if ( cause & 0x01 )
CALL_ISR( AU1X00_IRQ_SW0, frame ); CALL_ISR( AU1X00_IRQ_SW0, frame );
/* SW[1] */ /* SW[1] */
if ( cause & 0x02 ) if ( cause & 0x02 )
CALL_ISR( AU1X00_IRQ_SW1, frame ); CALL_ISR( AU1X00_IRQ_SW1, frame );
} }
@@ -90,8 +90,8 @@ void mips_default_isr( int vector )
} }
static void call_vectored_isr( static void call_vectored_isr(
CPU_Interrupt_frame *frame, CPU_Interrupt_frame *frame,
uint32_t cause, uint32_t cause,
void *ctrlr void *ctrlr
) )
{ {

10
c/src/lib/libcpu/mips/clock/ckinit.c
View File

@@ -84,7 +84,7 @@ uint32_t Clock_isrs; /* ISRs until next tick */
/* /*
* These are set by clock driver during its init * These are set by clock driver during its init
*/ */
rtems_device_major_number rtems_clock_major = ~0; rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor; rtems_device_minor_number rtems_clock_minor;
@@ -160,7 +160,7 @@ void Install_clock(
* Hardware specific initialize goes here * Hardware specific initialize goes here
*/ */
mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * mips_timer_rate = rtems_configuration_get_microseconds_per_tick() *
bsp_clicks_per_microsecond; bsp_clicks_per_microsecond;
mips_set_timer( mips_timer_rate ); mips_set_timer( mips_timer_rate );
mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK); mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
@@ -195,13 +195,13 @@ rtems_device_driver Clock_initialize(
) )
{ {
Install_clock( Clock_isr ); Install_clock( Clock_isr );
/* /*
* make major/minor avail to others such as shared memory driver * make major/minor avail to others such as shared memory driver
*/ */
rtems_clock_major = major; rtems_clock_major = major;
rtems_clock_minor = minor; rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL; return RTEMS_SUCCESSFUL;
} }

2
c/src/lib/libcpu/mips/clock/clock.S
View File

@@ -1,4 +1,4 @@
/* clock.s /* clock.s
* *
* This file contains the assembly code for the IDT 4650 clock driver. * This file contains the assembly code for the IDT 4650 clock driver.
* *

36
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
View File

@@ -172,8 +172,8 @@ MG5UART_STATIC int mg5uart_set_attributes(
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART, MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER, MG5UART_COMMAND_REGISTER,
(cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
@@ -305,8 +305,8 @@ MG5UART_STATIC int mg5uart_open(
MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
MG5UART_SETREG( pMG5UART, MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER, MG5UART_COMMAND_REGISTER,
cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
rtems_interrupt_enable(Irql); rtems_interrupt_enable(Irql);
@@ -352,8 +352,8 @@ MG5UART_STATIC int mg5uart_close(
rtems_interrupt_disable(Irql); rtems_interrupt_disable(Irql);
cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
MG5UART_SETREG( pMG5UART, MG5UART_SETREG( pMG5UART,
MG5UART_COMMAND_REGISTER, MG5UART_COMMAND_REGISTER,
(cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
rtems_interrupt_enable(Irql); rtems_interrupt_enable(Irql);
@@ -393,7 +393,7 @@ MG5UART_STATIC void mg5uart_write_polled(
*/ */
timeout = 2000; timeout = 2000;
while( --timeout ) while( --timeout )
{ {
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
@@ -411,7 +411,7 @@ MG5UART_STATIC void mg5uart_write_polled(
*/ */
#if 0 #if 0
if(_System_state_Is_up(_System_state_Get())) if(_System_state_Is_up(_System_state_Get()))
{ {
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
} }
@@ -473,8 +473,8 @@ __ISR(rx_ready, MG5UART_IRQ_RX_READY)
MG5UART_STATIC void mg5uart_process_isr_rx_error( MG5UART_STATIC void mg5uart_process_isr_rx_error(
int minor, int minor,
uint32_t mask uint32_t mask
) )
{ {
uint32_t pMG5UART; uint32_t pMG5UART;
@@ -524,7 +524,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
{ {
uint32_t pMG5UART; uint32_t pMG5UART;
int shift; int shift;
pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX);
@@ -533,7 +533,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
shift = MONGOOSEV_UART0_IRQ_SHIFT; shift = MONGOOSEV_UART0_IRQ_SHIFT;
else else
shift = MONGOOSEV_UART1_IRQ_SHIFT; shift = MONGOOSEV_UART1_IRQ_SHIFT;
MG5UART_SETREG( MG5UART_SETREG(
pMG5UART, pMG5UART,
MG5UART_STATUS_REGISTER, MG5UART_STATUS_REGISTER,
@@ -549,7 +549,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr(
* There are no more characters to transmit. The tx interrupts are be cleared * There are no more characters to transmit. The tx interrupts are be cleared
* by writing data to the uart, so just disable the tx interrupt sources. * by writing data to the uart, so just disable the tx interrupt sources.
*/ */
Console_Port_Data[minor].bActive = FALSE; Console_Port_Data[minor].bActive = FALSE;
/* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */ /* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */
@@ -659,7 +659,7 @@ MG5UART_STATIC int mg5uart_write_support_int(
MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf); MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
if( Console_Port_Data[minor].bActive == FALSE ) if( Console_Port_Data[minor].bActive == FALSE )
{ {
Console_Port_Data[minor].bActive = TRUE; Console_Port_Data[minor].bActive = TRUE;
mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL); mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL);
@@ -690,7 +690,7 @@ MG5UART_STATIC int mg5uart_write_support_polled(
/* /*
* poll each byte in the string out of the port. * poll each byte in the string out of the port.
*/ */
while (nwrite < len) while (nwrite < len)
{ {
mg5uart_write_polled(minor, *buf++); mg5uart_write_polled(minor, *buf++);
nwrite++; nwrite++;
@@ -734,11 +734,11 @@ MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled(
status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
} }
if ( status & MONGOOSEV_UART_RX_READY ) if ( status & MONGOOSEV_UART_RX_READY )
{ {
return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER); return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
} }
else else
{ {
return -1; return -1;
} }

4
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
View File

@@ -20,13 +20,13 @@
#ifndef _MG5UART_MULTIPLIER #ifndef _MG5UART_MULTIPLIER
#define _MG5UART_MULTIPLIER 1 #define _MG5UART_MULTIPLIER 1
#define _MG5UART_NAME(_X) _X #define _MG5UART_NAME(_X) _X
#define _MG5UART_TYPE uint32_t #define _MG5UART_TYPE uint32_t
#endif #endif
#define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \ #define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \
(_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER )) (_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER ))
/* /*
* MG5UART Get Register Routine * MG5UART Get Register Routine
*/ */

10
c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
View File

@@ -122,10 +122,10 @@
#define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013 #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013
#define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F #define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F
/* /*
* The Peripheral Interrupt Status, Cause, and Mask registers have the * The Peripheral Interrupt Status, Cause, and Mask registers have the
* same bit assignments although some revisions of the document have * same bit assignments although some revisions of the document have
* the Cause and Status registers incorrect. * the Cause and Status registers incorrect.
*/ */
#define MONGOOSEV_UART0_IRQ_SHIFT 11 #define MONGOOSEV_UART0_IRQ_SHIFT 11
@@ -193,7 +193,7 @@
** Peripheral Command bits (non-uart, those are defined above) ** Peripheral Command bits (non-uart, those are defined above)
*/ */
#define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT #define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT
#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT #define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT

8
c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c
View File

@@ -1,6 +1,6 @@
/* /*
* This file contains the maximum number of vectors. This can not * This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model. * be determined without knowing the RTEMS CPU model.
* *
* COPYRIGHT (c) 1989-2000. * COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR). * On-Line Applications Research Corporation (OAR).
@@ -17,9 +17,9 @@
*/ */
/* /*
* The Synova Mongoose-V attached one of the eight interrupt bits * The Synova Mongoose-V attached one of the eight interrupt bits
* to a Peripheral Function Interrupt Cause Register on-CPU. * to a Peripheral Function Interrupt Cause Register on-CPU.
* This results in: 2 software interrupts, 5 interrupts * This results in: 2 software interrupts, 5 interrupts
* through the IP bits, and 32 more from the PFICR. Some of * through the IP bits, and 32 more from the PFICR. Some of
* these are reserved but for simplicity in processing, we * these are reserved but for simplicity in processing, we
* reserve slots for those bits anyway. * reserve slots for those bits anyway.

18
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
View File

@@ -91,7 +91,7 @@ int assertSoftwareInterrupt( uint32_t n )
static volatile uint32_t _ivcause, _ivsr; static volatile uint32_t _ivcause, _ivsr;
static uint32_t READ_CAUSE(void) static uint32_t READ_CAUSE(void)
{ {
mips_get_cause( _ivcause ); mips_get_cause( _ivcause );
_ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */ _ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
@@ -140,7 +140,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
if ( cshifted & 0x01 ) /* SW[0] */ if ( cshifted & 0x01 ) /* SW[0] */
{ {
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame ); CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
} }
if ( cshifted & 0x02 ) /* SW[1] */ if ( cshifted & 0x02 ) /* SW[1] */
{ {
CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame ); CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame );
@@ -156,7 +156,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x4 ); CLR_ISR_FLAG( 0x4 );
if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect; if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
} }
if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/
{ {
SET_ISR_FLAG( 0x8 ); SET_ISR_FLAG( 0x8 );
@@ -164,7 +164,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x8 ); CLR_ISR_FLAG( 0x8 );
if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect; if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
} }
if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */ if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */
{ {
SET_ISR_FLAG( 0x10 ); SET_ISR_FLAG( 0x10 );
@@ -172,7 +172,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x10 ); CLR_ISR_FLAG( 0x10 );
if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect; if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
} }
if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */ if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */
{ {
SET_ISR_FLAG( 0x20 ); SET_ISR_FLAG( 0x20 );
@@ -180,7 +180,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
CLR_ISR_FLAG( 0x20 ); CLR_ISR_FLAG( 0x20 );
if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect; if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
} }
if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */ if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */
{ {
SET_ISR_FLAG( 0x40 ); SET_ISR_FLAG( 0x40 );
@@ -198,7 +198,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
/* /*
for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 ) for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 )
{ {
if ( pf_icr & pf_mask ) if ( pf_icr & pf_mask )
{ {
@@ -208,7 +208,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
pf_reset |= pf_mask; pf_reset |= pf_mask;
if( (cshifted = READ_CAUSE()) & 0xff ) break; if( (cshifted = READ_CAUSE()) & 0xff ) break;
} }
} }
*/ */
/* /*
@@ -217,7 +217,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
* way thru a full 32 bits. pf_mask shifts left 8 bits at a time * way thru a full 32 bits. pf_mask shifts left 8 bits at a time
* to serve as a interrupt cause test mask. * to serve as a interrupt cause test mask.
*/ */
for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
{ {
if ( pf_icr & pf_mask ) if ( pf_icr & pf_mask )
{ {

Some files were not shown because too many files have changed in this diff Show More