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Whitespace removal.

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This commit is contained in:
Ralf Corsepius
2009-11-30 05:09:41 +00:00
parent ac7af4a359
commit 359e537416
199 changed files with 1685 additions and 1685 deletions
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14
c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S
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@@ -24,11 +24,11 @@ codemove:
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
1: lwzu r0,4(r8)
stwu r0,4(r7)
stwu r0,4(r7)
bdnz 1b
b 4f
@@ -38,23 +38,23 @@ codemove:
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: cmplw r4,r5
5: cmplw r4,r5
dcbst 0,r4
add r4,r4,r6
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: cmplw r4,r5
6: cmplw r4,r5
icbi 0,r4
add r4,r4,r6
blt 6b

16
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq.c
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@@ -40,7 +40,7 @@ SPR_RW(PPC405_TSR)
/* legacy mode for bookE DEC exception;
* to avoid the double layer of function calls
* (dec_handler_bookE -> C_dispatch_irq_handler -> user handler)
* it is preferrable for the user to hook the DEC
* it is preferrable for the user to hook the DEC
* exception directly.
* However, the legacy mode works with less modifications
* of user code.
@@ -52,11 +52,11 @@ int C_dispatch_dec_handler_bookE (BSP_Exception_frame *frame, unsigned int excNu
* re-enables MSR_EE.
* Note that PPC405 uses a different SPR# for TSR
*/
if ( ppc_cpu_is_bookE()==PPC_BOOKE_405)
if ( ppc_cpu_is_bookE()==PPC_BOOKE_405)
_write_PPC405_TSR( BOOKE_TSR_DIS );
else
_write_BOOKE_TSR( BOOKE_TSR_DIS );
return C_dispatch_irq_handler(frame, ASM_DEC_VECTOR);
return C_dispatch_irq_handler(frame, ASM_DEC_VECTOR);
}
/*
@@ -348,7 +348,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
for ( i = config->irqBase; i < config->irqBase + config->irqNb; i++ ) {
for( vchain = &rtems_hdl_tbl[i];
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
vchain = (rtems_irq_connect_data*)vchain->next_handler )
{
if (vchain->on)
@@ -361,9 +361,9 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
/* Do NOT disable; there might be boards with cascaded
* interrupt controllers where the BSP (incorrectly) does
* not ignore the cascaded interrupts in BSP_disable_irq_at_pic()!
* Instead, we rely on BSP_setup_the_pic() for a good
* initial configuration.
*
* Instead, we rely on BSP_setup_the_pic() for a good
* initial configuration.
*
BSP_disable_irq_at_pic(i);
*/
}
@@ -374,7 +374,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
{
ppc_exc_set_handler(ASM_EXT_VECTOR, C_dispatch_irq_handler);
if ( ppc_cpu_is_bookE() ) {
if ( ppc_cpu_is_bookE() ) {
/* bookE decrementer interrupt needs to be cleared BEFORE
* dispatching the user ISR (because the user ISR is called
* with EE enabled)

2
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/irq_supp.h
View File

@@ -8,7 +8,7 @@
#ifndef IRQ_SHARED_IRQ_C_GLUE_H
#define IRQ_SHARED_IRQ_C_GLUE_H
/*
/*
* This header describes the routines that are needed by the shared
* version of 'irq.c' (implementing the RTEMS irq API). They
* must be provided by the BSP.

6
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c
View File

@@ -21,7 +21,7 @@
*
* The timer_isr prints a message then polls
* the variable 'timer_poll' while it has the value
* of the timer # then sets it to -1 and prints
* of the timer # then sets it to -1 and prints
* the 'leave' message.
*
* To test nested interrupts:
@@ -49,7 +49,7 @@
* The timer IRQs can be unhooked with
* timer_instdis( 0, 0, period );
* timer_instdis( 1, 0, period );
*/
*/
#include <rtems.h>
#include <rtems/bspIo.h>
#include <bsp/openpic.h>
@@ -74,7 +74,7 @@ uint32_t lat = (OpenPIC->Global.Timer[(int)p].Current_Count & 0x7fffffff);
while ( timer_poll == (int)p )
;
timer_poll = -1;
printk("Leaving ISR (%i)\n",(int)p);
}

2
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc-code-copy.c
View File

@@ -36,4 +36,4 @@ void ppc_code_copy(void *dest, const void *src, size_t n)
rtems_cache_invalidate_multiple_instruction_lines(dest, n);
ppc_synchronize_instructions();
}
}
}

20
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h
View File

@@ -59,7 +59,7 @@
* 3. load register with vector info
* 4. branch
*
*/
*/
/*
*****************************************************************************
@@ -99,7 +99,7 @@ ppc_exc_min_prolog_async_\_NAME:
stw r1, ppc_exc_lock_\_PRI@sdarel(r13)
/* We have no stack frame yet; store VECTOR_REGISTER in special area;
* a higher-priority (critical) interrupt uses a different area
* (hence the different prologue snippets) (\PRI)
* (hence the different prologue snippets) (\PRI)
*/
stw VECTOR_REGISTER, ppc_exc_vector_register_\_PRI@sdarel(r13)
/* Load vector.
@@ -131,7 +131,7 @@ ppc_exc_min_prolog_sync_\_NAME:
ba wrap_nopush_\_FLVR
.endm
/*
*****************************************************************************
* MACRO: TEST_1ST_OPCODE_crit
@@ -199,7 +199,7 @@ ppc_exc_min_prolog_sync_\_NAME:
GET_INTERRUPT_MASK mask=SCRATCH_REGISTER_1
/* EQ(cr0) = ((interrupt_mask & MSR_CE) == 0) */
andis. SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_CE@h
beq TEST_LOCK_crit_done_\_FLVR
beq TEST_LOCK_crit_done_\_FLVR
/* STD interrupt could have been interrupted before executing the 1st
* instruction which sets the lock; check this case by looking at the
@@ -212,7 +212,7 @@ ppc_exc_min_prolog_sync_\_NAME:
* *(PC) == 'stw r1, ppc_exc_lock_std@sdarel(r13)'
*
*/
/* check lock */
lwz SCRATCH_REGISTER_1, ppc_exc_lock_std@sdarel(r13)
cmplwi CR_LOCK, SCRATCH_REGISTER_1, 0
@@ -544,7 +544,7 @@ wrap_change_msr_done_\_FLVR:
* We add FRAME_LINK_SPACE to the frame pointer because the high level
* handler expects a BSP_Exception_frame structure.
*/
addi r3, FRAME_REGISTER, FRAME_LINK_SPACE
addi r3, FRAME_REGISTER, FRAME_LINK_SPACE
/*
* Second parameter = vector number (r4 is the VECTOR_REGISTER)
@@ -611,7 +611,7 @@ wrap_handler_done_\_FLVR:
LA SCRATCH_REGISTER_0, ppc_exc_wrapup
/* First parameter = exception frame pointer + FRAME_LINK_SPACE */
addi r3, FRAME_REGISTER, FRAME_LINK_SPACE
addi r3, FRAME_REGISTER, FRAME_LINK_SPACE
/* Call ppc_exc_wrapup() */
mtctr SCRATCH_REGISTER_0
@@ -633,7 +633,7 @@ wrap_restore_msr_done_\_FLVR:
lwz FRAME_REGISTER, FRAME_OFFSET(r1)
/* Restore XER and CTR */
lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1)
lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1)
lwz SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1)
mtxer SCRATCH_REGISTER_0
mtctr SCRATCH_REGISTER_1
@@ -728,7 +728,7 @@ wrap_restore_non_volatile_regs_\_FLVR:
/* Restore small data area anchor (SYSV) */
lwz r13, GPR13_OFFSET(r1)
/* r14 is the FRAME_REGISTER and will be restored elsewhere */
/* Restore non-volatile registers r15 .. r31 */
@@ -742,7 +742,7 @@ wrap_restore_non_volatile_regs_\_FLVR:
wrap_call_global_handler_\_FLVR:
/* First parameter = exception frame pointer + FRAME_LINK_SPACE */
addi r3, FRAME_REGISTER, FRAME_LINK_SPACE
addi r3, FRAME_REGISTER, FRAME_LINK_SPACE
/* Load global handler address */
LW SCRATCH_REGISTER_0, globalExceptHdl

4
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h
View File

@@ -40,7 +40,7 @@ extern "C" {
typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned int vector);
/*
* Bits in MSR that are enabled during execution of exception handlers / ISRs
* Bits in MSR that are enabled during execution of exception handlers / ISRs
* (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should
* be set to 0 during initialization)
*
@@ -95,7 +95,7 @@ typedef uint32_t ppc_exc_min_prolog_t[4];
/* Templates are ppc_raw_except_func BUT they must be exactly 16 bytes */
typedef rtems_raw_except_func ppc_exc_min_prolog_template_t;
/*
/*
* Expand a prolog template into 'buf' using vector 'vec'
*/
void

2
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
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@@ -12,7 +12,7 @@
*
* Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
*
* Copyright (C) 2009 embedded brains GmbH.
* Copyright (C) 2009 embedded brains GmbH.
*
* Derived from file "libcpu/powerpc/new-exceptions/bspsupport/vectors_init.c".
* Derived from file "libcpu/powerpc/new-exceptions/e500_raw_exc_init.c".

4
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_naked.S
View File

@@ -106,7 +106,7 @@ wrap_change_msr_done_naked:
* We add FRAME_LINK_SPACE to the frame pointer because the high level
* handler expects a BSP_Exception_frame structure.
*/
addi r3, r1, FRAME_LINK_SPACE
addi r3, r1, FRAME_LINK_SPACE
/*
* Second parameter = vector number (r4 is the VECTOR_REGISTER)
@@ -127,7 +127,7 @@ wrap_change_msr_done_naked:
wrap_restore_msr_done_naked:
/* Restore XER and CTR */
lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1)
lwz SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1)
lwz SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1)
mtxer SCRATCH_REGISTER_0
mtctr SCRATCH_REGISTER_1

2
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_prologue.c
View File

@@ -9,7 +9,7 @@
/*
* Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
*
* Copyright (C) 2009 embedded brains GmbH.
* Copyright (C) 2009 embedded brains GmbH.
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at

40
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
View File

@@ -7,29 +7,29 @@
* @brief PowerPC Exceptions API.
*/
/*
* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
* Canon Centre Recherche France.
/*
* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
* Canon Centre Recherche France.
*
* Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
*
* Copyright (C) 2009 embedded brains GmbH.
*
* Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
* to support 603, 603e, 604, 604e exceptions
*
* Moved to "libcpu/powerpc/new-exceptions" and consolidated
* by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* to be common for all PPCs with new exceptions.
*
*
* Copyright (C) 2009 embedded brains GmbH.
*
* Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
* to support 603, 603e, 604, 604e exceptions
*
* Moved to "libcpu/powerpc/new-exceptions" and consolidated
* by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* to be common for all PPCs with new exceptions.
*
* Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h".
* Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h".
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */
@@ -413,7 +413,7 @@ typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector);
/**
* @brief Bits for MSR update.
*
* Bits in MSR that are enabled during execution of exception handlers / ISRs
* Bits in MSR that are enabled during execution of exception handlers / ISRs
* (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should
* be set to 0 during initialization)
*

6
c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
View File

@@ -123,7 +123,7 @@ void _CPU_Context_Initialize(
#if (PPC_ABI == PPC_ABI_SVR4)
/*
* SVR4 says R2 is for 'system-reserved' use; it cannot hurt to
* SVR4 says R2 is for 'system-reserved' use; it cannot hurt to
* propagate R2 to all task contexts.
*/
{ uint32_t r2 = 0;
@@ -171,8 +171,8 @@ void _CPU_Install_interrupt_stack( void )
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
proc_ptr *old_handler
)
{
BSP_panic("_CPU_ISR_install_vector called\n");
}